X9250
®
Low Noise/Low Power/SPI Bus/256 Taps
Data Sheet
April 18, 2006
DESCRIPTION
Quad Digitally Controlled Potentiometers
(XDCP™)
The X9250 integrates 4 digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated circuit.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
FN8165.2
Four potentiometers in one package
256 resistor taps/pot - 0.4% resolution
SPI serial interface
Wiper resistance, 40Ω typical @ VCC = 5V
Four nonvolatile data registers for each pot
Nonvolatile storage of wiper position
Standby current < 5µA max (total package)
Power supplies
—VCC = 2.7V to 5.5V
—V+ = 2.7V to 5.5V
—V– = -2.7V to -5.5V
100kΩ, 50kΩ total pot resistance
High reliability
—Endurance – 100,000 data changes per bit per
register
—Register data retention - 100 years
24 Ld SOIC, 24 Ld TSSOP
Dual supply version of X9251
Pb-free plus anneal available (RoHS compliant)
The digitally controlled potentiometer is implemented
using 255 resistive elements in a series array.
Between each element are tap points connected to the
wiper terminal through switches. The position of the
wiper on the array is controlled by the user through the
SPI bus interface. Each potentiometer has associated
with it a volatile Wiper Counter Register (WCR) and 4
nonvolatile Data Registers (DR0:DR3) that can be
directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the
resistor array though the switches. Power up recalls
the contents of DR0 to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
BLOCK DIAGRAM
VCC
VSS
V+
V-
Pot 0
R0 R1
R2 R3
HOLD
CS
SCK
SO
SI
A0
A1
Interface
and
Control
Circuitry
VH0/RH0
Wiper
Counter
Register
(WCR)
VL0/RL0
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 2
VH2/RH2
VL2/RL2
VW0/RW0
VW2/RW2
VW1/RW1
VW3/RW3
8
Data
WP
R0 R1
R2 R3
1
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot1
VH1/RH1
VL1/RL1
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 3
VH3/RH3
VL3/RH3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9250
Ordering Information
PART NUMBER
PART
MARKING
VCC LIMITS (V)
POTENTIOMETER
ORGANIZATION (kΩ)
TEMP. RANGE
(°C)
5 ±10%
100
0 to 70
24 Ld SOIC (300mil) M24.3
PACKAGE
PKG. DWG. #
X9250TS24*
X9250TS
X9250TS24Z* (Note)
X9250TS Z
0 to 70
24 Ld SOIC (300mil) M24.3
(Pb-free)
X9250TS24I*
X9250TS I
-40 to 85
24 Ld SOIC (300mil) M24.3
X9250TS24IZ* (Note)
X9250TS ZI
-40 to 85
24 Ld SOIC (300mil) M24.3
(Pb-free)
X9250TV24
X9250TV
0 to 70
24 Ld TSSOP
(4.4mm)
MDP0044
X9250TV24Z (Note)
X9250TV Z
0 to 70
24 Ld TSSOP
(4.4mm) (Pb-free)
MDP0044
X9250TV24I
X9250TV I
-40 to 85
24 Ld TSSOP
(4.4mm)
MDP0044
X9250TV24IZ (Note)
X9250TV ZI
-40 to 85
24 Ld TSSOP
(4.4mm) (Pb-free)
MDP0044
X9250US24*
X9250US
X9250US24Z* (Note)
50
0 to 70
24 Ld SOIC (300mil) M24.3
X9250US Z
0 to 70
24 Ld SOIC (300mil) M24.3
(Pb-free)
X9250US24I*
X9250US I
-40 to 85
24 Ld SOIC (300mil) M24.3
X9250US24IZ* (Note)
X9250US ZI
-40 to 85
24 Ld SOIC (300mil) M24.3
(Pb-free)
X9250UV24
X9250UV
0 to 70
24 Ld TSSOP
(4.4mm)
MDP0044
X9250UV24Z (Note)
X9250UV Z
0 to 70
24 Ld TSSOP
(4.4mm) (Pb-free)
MDP0044
X9250UV24I
X9250UV I
-40 to 85
24 Ld TSSOP
(4.4mm)
MDP0044
X9250UV24IZ (Note)
X9250UV ZI
-40 to 85
24 Ld TSSOP
(4.4mm) (Pb-free)
MDP0044
X9250TS24-2.7*
X9250TS F
-2.7 to 5.5
100
X9250TS24Z-2.7* (Note) X9250TS ZF
0 to 70
24 Ld SOIC (300mil) M24.3
0 to 70
24 Ld SOIC (300mil) M24.3
(Pb-free)
X9250TS24I-2.7*
X9250TS G
-40 to 85
24 Ld SOIC (300mil) M24.3
X9250TS24IZ-2.7*
(Note)
X9250TS ZG
-40 to 85
24 Ld SOIC (300mil) M24.3
(Pb-free)
X9250TV24-2.7
X9250TV F
X9250TV24Z-2.7 (Note) X9250TV ZF
X9250TV24I-2.7
X9250TV G
X9250TV24IZ-2.7 (Note) X9250TV ZG
X9250US24-2.7*
X9250US F
X9250US24Z-2.7* (Note) X9250US ZF
X9250US24I-2.7*
X9250US G
2
50
0 to 70
24 Ld TSSOP
(4.4mm)
MDP0044
0 to 70
24 Ld TSSOP
(4.4mm) (Pb-free)
MDP0044
-40 to 85
24 Ld TSSOP
(4.4mm)
MDP0044
-40 to 85
24 Ld TSSOP
(4.4mm) (Pb-free)
MDP0044
0 to 70
24 Ld SOIC (300mil) M24.3
0 to 70
24 Ld SOIC (300mil) M24.3
(Pb-free)
-40 to 85
24 Ld SOIC (300mil) M24.3
FN8165.2
April 18, 2006
X9250
Ordering Information (Continued)
PART NUMBER
PART
MARKING
X9250US24IZ-2.7*
(Note)
X9250US ZG
X9250UV24-2.7
X9250UV F
X9250UV24Z-2.7 (Note) X9250UV ZF
X9250UV24I-2.7
X9250UV G
X9250UV24IZ-2.7 (Note) X9250UV ZG
VCC LIMITS (V)
POTENTIOMETER
ORGANIZATION (kΩ)
TEMP. RANGE
(°C)
-2.7 to 5.5
50
-40 to 85
PACKAGE
PKG. DWG. #
24 Ld SOIC (300mil) M24.3
(Pb-free)
0 to 70
24 Ld TSSOP
(4.4mm)
MDP0044
0 to 70
24 Ld TSSOP
(4.4mm) (Pb-free)
MDP0044
-40 to 85
24 Ld TSSOP
(4.4mm)
MDP0044
-40 to 85
24 Ld TSSOP
(4.4mm) (Pb-free)
MDP0044
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3
FN8165.2
April 18, 2006
X9250
PIN DESCRIPTIONS
VW/RW (VW0/RW0 - VW3/RW3)
Serial Output (SO)
The wiper pins are equivalent to the wiper terminal of a
mechanical potentiometer.
SO is a serial data output pin. During a read cycle,
data is shifted out on this pin. Data is clocked out by
the falling edge of the serial clock.
Serial Input
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.
Hardware Write Protect Input (WP)
The WP pin when LOW prevents nonvolatile writes to
the Data Registers.
Analog Supplies (V+, V-)
The analog supplies V+, V- are the supply voltages for
the XDCP analog section.
PIN CONFIGURATION
Serial Clock (SCK)
The SCK input is used to clock data into and out of the
X9250.
SOIC/TSSOP
Chip Select (CS)
When CS is HIGH, the X9250 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS LOW enables the X9250, placing it
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
Hold (HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought LOW while SCK is LOW. To resume
communication, HOLD is brought HIGH, again while
SCK is LOW. If the pause feature is not used, HOLD
should be held HIGH at all times.
S0
1
24
HOLD
A0
2
23
SCK
VW3/RW3
3
22
VL2/RL2
VH3/RH3
4
21
VH2/RL2
VL3/RL3
5
20
VW2/RW2
V+
6
19
V–
VCC
7
18
VSS
VL0/RL0
8
17
VW1/RW1
VH0/RH0
9
16
VH1/RH1
VW0/RW0
10
15
VL1/RL1
CS
11
14
A1
WP
12
13
SI
PIN NAMES
Symbol
SCK
Device Address (A0 - A1)
The address inputs are used to set the least significant
2 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with
the X9250. A maximum of 4 devices may occupy the
SPI serial bus.
Potentiometer Pins
VH/RH (VH0/RH0 - VH3/RH3), VL/RL (VL0/RL0 VL3/RL3)
The RH and RL pins are equivalent to the terminal
connections on a mechanical potentiometer.
4
X9250
Description
Serial Clock
SI, SO
Serial Data
A0-A1
Device Address
VH0/RH0–VH3/RH3,
VL0/RL0–VL3/RL3
Potentiometer Pins
(terminal equivalent)
VW0/RW0–VW3/RW3
Potentiometer Pins
(wiper equivalent)
WP
Hardware Write Protection
V+,V-
Analog Supplies
VCC
System Supply Voltage
VSS
System Ground
NC
No Connection
FN8165.2
April 18, 2006
X9250
Wiper Counter Register (WCR)
DEVICE DESCRIPTION
Serial Interface
The X9250 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS must be
LOW and the HOLD and WP pins must be HIGH
during the entire operation.
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
Array Description
The X9250 is comprised of four resistor arrays. Each
array contains 255 discrete resistive segments that
are connected in series. The physical ends of each
array are equivalent to the fixed terminals of a
mechanical potentiometer (VH/RH and VL/RL inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(VW/RW) output. Within each individual array only one
switch may be turned on at a time.
These switches are controlled by a Wiper Counter
Register (WCR). The 8 bits of the WCR are decoded
to select, and enable, one of 256 switches.
The X9250 contains four Wiper Counter Registers,
one for each XDCP potentiometer. The WCR is
equivalent to a serial-in, parallel-out register/counter
with its outputs decoded to select one of 256 switches
along its resistor array. The contents of the WCR can
be altered in four ways: it may be written directly by
the host via the write Wiper Counter Register
instruction (serial load); it may be written indirectly by
transferring the contents of one of four associated
Data Registers via the XFR Data Register or Global
XFR Data Register instructions (parallel load); it can
be modified one step at a time by the
increment/decrement instruction. Finally, it is loaded
with the contents of its Data Register zero (DR0) upon
power-up.
The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9250 is powereddown. Although the register is automatically loaded
with the value in R0 upon power-up, this may be
different from the value present at power-down.
Data Registers
Each potentiometer has four 8-bit nonvolatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Counter
Register. All operations changing data in one of the
Data Registers is a nonvolatile operation and will take
a maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.
Data Register Detail
(MSB)
5
(LSB)
D7
D6
D5
D4
D3
D2
D1
D0
NV
NV
NV
NV
NV
NV
NV
NV
FN8165.2
April 18, 2006
X9250
Figure 1. Detailed Potentiometer Block Diagram
(One of Four Arrays)
Serial Data Path
VH/RH
Serial
Bus
Input
From Interface
Circuitry
Register 0
8
Register 2
8
Parallel
Bus
Input
Wiper
Counter
Register
(WCR)
Register 3
If WCR = 00[H] then VW/RW = VL/RL
If WCR = FF[H] then VW/RW = VH/RH
C
o
u
n
t
e
r
Register 1
UP/DN
Modified SCK
D
e
c
o
d
e
Inc/Dec
Logic
UP/DN
VL/RL
CLK
VW/RW
Write in Process
Figure 2. Identification Byte Format
The contents of the Data Registers are saved to
nonvolatile memory when the CS pin goes from LOW
to HIGH after a complete write sequence is received
by the device. The progress of this internal write
operation can be monitored by a write in process bit
(WIP). The WIP bit is read with a read status
command.
Device Type
Identifier
0
1
0
1
0
0
A1
A0
Device Address
INSTRUCTIONS
Instruction Byte
Identification (ID) Byte
The next byte sent to the X9250 contains the
instruction and register pointer information. The four
most significant bits are the instruction. The next four
bits point to one of the four pots and, when applicable,
they point to one of four associated registers. The
format is shown below in Figure 3.
The first byte sent to the X9250 from the host,
following a CS going HIGH to LOW, is called the
Identification byte. The most significant four bits of the
slave address are a device type identifier, for the
X9250 this is fixed as 0101[B] (refer to Figure 2).
The two least significant bits in the ID byte select one
of four devices on the bus. The physical device
address is defined by the state of the A0 - A1 input
pins. The X9250 compares the serial data stream with
the address input state; a successful compare of both
address bits is required for the X9250 to successfully
continue the command sequence. The A0 - A1 inputs
can be actively driven by CMOS input signals or tied to
VCC or VSS.
Figure 3. Instruction Byte Format
Register
Select
I3
I2
I1
Instructions
I0
R1
R0
P1
P0
Pot Select
The remaining two bits in the slave byte must be set to 0.
6
FN8165.2
April 18, 2006
X9250
The four high order bits of the instruction byte specify
the operation. The next two bits (R1 and R0) select
one of the four registers that is to be acted upon when
a register oriented instruction is issued. The last two
bits (P1 and P0) selects which one of the four
potentiometers is to be affected by the instruction.
Five instructions require a three-byte sequence to
complete. These instructions transfer data between
the host and the X9250; either between the host and
one of the data registers or directly between the host
and the Wiper Counter Register. These instructions
are:
Four of the ten instructions are two bytes in length and
end with the transmission of the instruction byte.
These instructions are:
– Read Wiper Counter Register—read the current
wiper position of the selected pot,
– XFR Data Register to Wiper Counter Register—This
transfers the contents of one specified Data Register
to the associated Wiper Counter Register.
– XFR Wiper Counter Register to Data Register—This
transfers the contents of the specified Wiper
Counter Register to the specified associated Data
Register.
– Global XFR Data Register to Wiper Counter Regiter—
This transfers the contents of all specified Data Registers to the associated Wiper Counter Registers.
– Global XFR Wiper Counter Register to Data Regiter—
This transfers the contents of all Wiper Counter
Registers to the specified associated Data Registers.
The basic sequence of the two byte instructions is
illustrated in Figure 4. These two-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
wiper to this action will be delayed by tWRL. A transfer
from the WCR (current wiper position), to a Data
Register is a write to nonvolatile memory and takes a
minimum of tWR to complete. The transfer can occur
between one of the four potentiometers and one of its
associated registers; or it may occur globally, where
the transfer occurs between all potentiometers and one
associated register.
7
– Write Wiper Counter Register—change current
wiper position of the selected pot,
– Read Data Register—read the contents of the
selected data register;
– Write Data Register—write a new value to the
selected data register.
– Read Status—This command returns the contents
of the WIP bit which indicates if the internal write
cycle is in progress.
The sequence of these operations is shown in Figure
5 and Figure 6.
The final command is Increment/Decrement. It is
different from the other commands, because it’s length
is indeterminate. Once the command is issued, the
master can clock the selected wiper up and/or down in
one resistor segment steps; thereby, providing a fine
tuning capability to the host. For each SCK clock pulse
(tHIGH) while SI is HIGH, the selected wiper will move
one resistor segment towards the VH/RH terminal.
Similarly, for each SCK clock pulse while SI is LOW,
the selected wiper will move one resistor segment
towards the VL/RL terminal. A detailed illustration of the
sequence and timing for this operation are shown in
Figure 7 and Figure 8.
FN8165.2
April 18, 2006
X9250
Figure 4. Two-Byte Instruction Sequence
CS
SCK
SI
0
1
0
1
0
0
A1
A0
I3
I2
I1
I0
R1 R0
P1 P0
Figure 5. Three-Byte Instruction Sequence (Write)
CS
SCL
SI
0
1
0
0
1
0
A1 A0
I3
I2
I1 I0
R1 R0 P1 P0
D7 D6 D5 D4 D3 D2 D1 D0
Figure 6. Three-Byte Instruction Sequence (Read)
CS
SCL
SI
Don’t Care
0
1
0
0
1
0
A1 A0
I3
I2
I1 I0
R1 R0 P1 P0
S0
D7 D6 D5 D4 D3 D2 D1 D0
Figure 7. Increment/Decrement Instruction Sequence
CS
SCK
SI
0
1
0
1
0
8
0
A1 A0
I3
I2
I1
I0
0
0
P1
P0
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
FN8165.2
April 18, 2006
X9250
Figure 8. Increment/Decrement Timing Limits
tWRID
SCK
SI
Voltage Out
VW/RW
INC/DEC CMD Issued
Table 1. Instruction Set
I3
1
I2
0
Instruction Set
I1 I0 R1 R0
0
1
0
0
1
0
1
0
0
0
P1
P0
1
0
1
1
R1
R0
P1
P0
Write Data Register
1
1
0
0
R1
R0
P1
P0
XFR Data Register to
Wiper Counter Register
1
1
0
1
R1
R0
P1
P0
XFR Wiper Counter
Register to Data Register
1
1
1
0
R1
R0
P1
P0
Global XFR Data Register
to Wiper Counter Register
0
0
0
1
R1
R0
0
0
Global XFR Wiper Counter
Register to Data Register
1
0
0
0
R1
R0
0
0
Increment/Decrement
Wiper Counter Register
Read Status (WIP bit)
0
0
1
0
0
0
P1
P0
0
1
0
1
0
0
0
1
Instruction
Read Wiper Counter
Register
Write Wiper Counter
Register
Read Data Register
9
P1
P1
P0
P0
Operation
Read the contents of the Wiper Counter
Register pointed to by P1- P0
Write new value to the Wiper Counter Register
pointed to by P1- P0
Read the contents of the Data Register
pointed to by P1- P0 and R1- R0
Write new value to the Data Register pointed to
by P1- P0 and R1- R0
Transfer the contents of the Data Register
pointed to by R1- R0 to the Wiper Counter
Register pointed to by P1- P0
Transfer the contents of the Wiper Counter
Register pointed to by P1- P0 to the Register
pointed to by R1- R0
Transfer the contents of the Data Registers
pointed to by R1- R0 of all four pots to their
respective Wiper Counter Register
Transfer the contents of all Wiper Counter
Registers to their respective data Registers
pointed to by R1- R0 of all four pots
Enable Increment/decrement of the Wiper
Counter Register pointed to by P1- P0
Read the status of the internal write cycle, by
checking the WIP bit.
FN8165.2
April 18, 2006
X9250
Instruction Format
Notes: (1)
(2)
(2)
(3)
“A1 ~ A0”: stands for the device addresses sent by the master.
WPx refers to wiper position data in the Counter Register
“I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
“D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
Read Wiper Counter Register(WCR)
device type
identifier
device
addresses
CS
Falling
Edge 0 1 0 1 0 0 A A
1 0
instruction
opcode
1
0
0
1
WCR
addresses
0
0
P
1
wiper position
(sent by X9250 on SO)
CS
W W W W W W W W Rising
P
P P P P P P P P Edge
0
7 6 5 4 3 2 1 0
Write Wiper Counter Register (WCR)
device type
identifier
device
addresses
CS
Falling
Edge 0 1 0 1 0 0 A A
1 0
instruction
opcode
1
0
1
0
WCR
addresses
0
0
P
1
Data Byte
(sent by Host on SI)
CS
W W W W W W W W Rising
P
P P P P P P P P Edge
0
7 6 5 4 3 2 1 0
Read Data Register (DR)
device type
identifier
device
addresses
CS
Falling
Edge 0 1 0 1 0 0
A
1
A
0
instruction
opcode
DR and WCR
addresses
1 0 1 1
R
1
R
0
P
1
Data Byte
(sent by X9250 on SO)
CS
W W W W W W W W Rising
P
P P P P P P P P Edge
0
7 6 5 4 3 2 1 0
Write Data Register (DR)
device type
identifier
device
addresses
CS
Falling
Edge 0 1 0 1 0 0
A
1
A
0
instruction
opcode
DR and WCR
addresses
1 1 0 0
R
1
R
0
P
1
Data Byte
(sent by host on SI)
CS
W W W W W W W W Rising
P
P P P P P P P P Edge
0
7 6 5 4 3 2 1 0
HIGH-VOLTAGE
WRITE CYCLE
Transfer Data Register (DR) to Wiper Counter Register (WCR)
device type
device
instruction
DR and WCR
CS
CS
identifier
addresses
opcode
addresses
Falling
Rising
Edge 0 1 0 1 0 0 A A 1 1 0 1 R1 R0 P1 P0 Edge
1 0
10
FN8165.2
April 18, 2006
X9250
Transfer Wiper Counter Register (WCR) to Data Register (DR)
device type
device
CS
identifier
addresses
Falling
Edge 0 1 0 1 0 0 A A
1 0
instruction
opcode
DR and WCR
addresses
1 1 1 0
R
1
R
0
P
1
CS
Rising
P Edge
0
HIGH-VOLTAGE
WRITE CYCLE
Increment/Decrement Wiper Counter Register (WCR)
device type
device
instruction
WCR
increment/decrement
CS
CS
identifier
addresses
opcode
addresses
(sent by master on SI)
Falling
Rising
Edge 0 1 0 1 0 0 A A 0 0 1 0 X X P P I/D I/D . . . . I/D I/D Edge
1 0
1 0
Global Transfer Data Register (DR) to Wiper Counter Register (WCR)
device type
device
instruction
DR
CS
CS
identifier
addresses
opcode
addresses
Falling
Rising
Edge 0 1 0 1 0 0 A A 0 0 0 1 R R 0 0 Edge
1 0
1 0
Global Transfer Wiper Counter Register (WCR) to Data Register (DR)
device type
device
instruction
DR
CS
CS
identifier
addresses
opcode
addresses
Falling
Rising
Edge 0 1 0 1 0 0 A A 1 0 0 0 R R 0 0 Edge
1 0
1 0
HIGH-VOLTAGE
WRITE CYCLE
Read Status
device type
identifier
device
addresses
instruction
opcode
Data Byte
(sent by X9250 on SO)
CS
CS
Falling
W Rising
Edge 0 1 0 1 0 0 A A 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 I Edge
1 0
P
11
FN8165.2
April 18, 2006
X9250
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias ........................ -65 to +135°C
Storage temperature ............................. -65 to +150°C
Voltage on SCK, SCL or any address input
with respect to VSS ................................. -1V to +7V
Voltage on V+ (referenced to VSS)........................ 10V
Voltage on V- (referenced to VSS)........................-10V
(V+) - (V-) .............................................................. 12V
Any VH/RH ..............................................................V+
Any VL/RL.................................................................VLead temperature (soldering, 10s) .................... 300°C
IW (10s) ............................................................±15mA
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
RECOMMENDED OPERATING CONDITIONS
Temp
Commercial
Industrial
Min.
0°C
-40°C
Max.
+70°C
+85°C
Device
X9250
X9250-2.7
Supply Voltage (VCC) Limits(4)
5V ± 10%
2.7V to 5.5V
POTENTIOMETER CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Limits
Symbol
Max.
Unit
End to end resistance tolerance
±20
%
Power rating
50
mW
IW
Wiper current
±7.5
mA
RW
Wiper resistance
Vv+
Voltage on V+ pin
VvVTERM
Parameter
Voltage on V- pin
Min.
Typ.
250
Ω
X9250
+4.5
+5.5
V
X9250-2.7
+2.7
+5.5
X9250
-5.5
-4.5
X9250-2.7
-5.5
-2.7
V-
V+
150
Voltage on any VH/RH or VL/RL pin
Noise
Resolution (4)
Temperature coefficient of RTOTAL
0.6
%
Ratiometric Temperature
Coefficient
CH/CL/CW
Potentiometer Capacitances
±1
MI(3)
±0.6
MI(3)
Ref: 1kHz
Vw(n)(actual) - Vw(n)(expected)
Vw(n + 1 - [Vw(n) + MI]
ppm/°C
±20
10/10/25
Wiper current = ± 1mA
V
dBV
±300
25°C, each pot
V
-120
Absolute linearity (1)
Relative linearity (2)
Test Conditions
ppm/°C
pF
See Circuit #3
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size.
(3) MI = RTOT/255 or (VH/RH - VL/RL)/255, single pot
(4) Individual array resolutions.
12
FN8165.2
April 18, 2006
X9250
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
ICC1
VCC supply current
(active)
400
µA
fSCK = 2MHz, SO = Open,
Other Inputs = VSS
ICC2
VCC supply current
(nonvolatile write)
1
mA
fSCK = 2MHz, SO = Open,
Other Inputs = VSS
ISB
VCC current (standby)
5
µA
SCK = SI = VSS, Addr. = VSS
ILI
Input leakage current
10
µA
VIN = VSS to VCC
ILO
Output leakage current
10
µA
VOUT = VSS to VCC
VIH
Input HIGH voltage
VCC x 0.7
VCC + 0.1
V
VIL
Input LOW voltage
-0.5
VCC x 0.3
V
VOL
Output LOW voltage
0.4
V
IOL = 3mA
ENDURANCE AND DATA RETENTION
Parameter
Min.
Unit
Minimum endurance
100,000
Data changes per bit per register
Data retention
100
Years
CAPACITANCE
Symbol
COUT
(5)
CIN(5)
Test
Max.
Unit
Test Conditions
Output capacitance (SO)
8
pF
VOUT = 0V
Input capacitance (A0, A1, SI, and SCK, CS)
6
pF
VIN = 0V
POWER-UP TIMING
Symbol
tPUR(6)
tPUW(6)
tR VCC(7)
Parameter
Max.
Unit
Power-up to initiation of read operation
1
ms
Power-up to initiation of write operation
5
ms
50
V/msec
VCC power up ramp rate
Min.
0.2
POWER UP AND DOWN REQUIREMENT
The are no restrictions on the sequencing of the bias supplies VCC, V+, and V- provided that all three supplies reach
their final values within 1msec of each other. At all times, the voltages on the potentiometer pins must be less than V+
and more than V-. The recall of the wiper position from nonvolatile memory is not in effect until all supplies reach their
final value. The VCC ramp rate spec is always in effect.
Notes: (5) This parameter is periodically sampled and not 100% tested
(6) tPUR and tPUW are the delays required from the time the third (last) power supply (VCC, V+ or V-) is stable until the specific instruction can be
issued. These parameters are periodically sampled and not 100% tested.
(7) Sample tested only.
A.C. TEST CONDITIONS
Input pulse levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
10ns
Input and output timing level
VCC x 0.5
13
FN8165.2
April 18, 2006
X9250
Circuit #3 SPICE Macro Model
EQUIVALENT A.C. LOAD CIRCUIT
5V
RTOTAL
RH
CH
CW
RL
CL
2.7V
1533Ω
10pF
SDA Output
10pF
25pF
100pF
100pF
RW
AC TIMING
Symbol
Parameter
Min.
Max.
Unit
2.0
MHz
fSCK
SSI/SPI clock frequency
tCYC
SSI/SPI clock cycle time
500
ns
tWH
SSI/SPI clock high time
200
ns
tWL
SSI/SPI clock low time
200
ns
tLEAD
Lead time
250
ns
tLAG
Lag time
250
ns
tSU
SI, SCK, HOLD and CS input setup time
50
ns
tH
SI, SCK, HOLD and CS input hold time
75
ns
tRI
SI, SCK, HOLD and CS input rise time
2
µs
tFI
SI, SCK, HOLD and CS input fall time
2
µs
500
ns
100
ns
tDIS
SO output disable Time
tV
SO output valid time
tHO
SO output hold time
tRO
SO output rise time
tFO
SO output fall time
tHOLD
0
0
ns
50
50
ns
ns
HOLD time
400
ns
tHSU
HOLD setup time
100
ns
tHH
HOLD hold time
100
ns
tHZ
HOLD low to output in high Z
100
ns
tLZ
HOLD high to output in low Z
100
ns
TI
Noise suppression time constant at SI, SCK, HOLD and CS inputs
TBD
ns
tCS
CS deselect time
2
µs
tWPASU
WP, A0 and A1 setup time
0
ns
tWPAH
WP, A0 and A1 hold time
0
ns
14
FN8165.2
April 18, 2006
X9250
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
Parameter
tWR
High-voltage write cycle time (store instructions)
Typ.
Max.
Unit
5
10
ms
XDCP TIMING
Symbol
Max.
Unit
Wiper response time after the third (last) power supply is stable
10
µs
tWRL
Wiper response time after instruction issued (all load instructions)
10
µs
tWRID
Wiper response time from an active SCL/SCK edge (increment/decrement instruction)
40
µs
tWRPO
Parameter
Min.
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
TIMING DIAGRAMS
Input Timing
tCS
CS
tCYC
tLEAD
SCK
tSU
SI
SO
tH
MSB
tWL
tLAG
...
tWH
...
tRI
tFI
LSB
High Impedance
15
FN8165.2
April 18, 2006
X9250
Output Timing
CS
SCK
...
tV
tDIS
...
MSB
SO
SI
tHO
LSB
ADDR
Hold Timing
CS
tHSU
tHH
SCK
...
tRO
tFO
SO
tHZ
tLZ
SI
tHOLD
HOLD
XDCP Timing (for all Load Instructions)
CS
SCK
SI
...
MSB
...
tWRL
LSB
VWx
SO
High Impedance
16
FN8165.2
April 18, 2006
X9250
XDCP Timing (for Increment/Decrement Instruction)
CS
SCK
...
tWRID
...
VWx
SI
SO
ADDR
Inc/Dec
Inc/Dec
...
High Impedance
Write Protect and Device Address Pins Timing
(Any Instruction)
CS
tWPASU
WP
tWPAH
A0
A1
17
FN8165.2
April 18, 2006
X9250
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
+VR
VR
VW/RW
I
Three terminal Potentiometer;
Variable voltage divider
Two terminal Variable Resistor;
Variable current
Application Circuits
Noninverting Amplifier
VS
Voltage Regulator
+
VO
–
VIN
VO (REG)
317
R1
R2
Iadj
R1
R2
VO = (1+R2/R1)VS
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
Offset Voltage Adjustment
R1
Comparator with Hysterisis
R2
VS
VS
–
+
100kΩ
–
VO
+
+12V
10kΩ
R1
}
10kΩ
}
TL072
10kΩ
VO
R2
VUL = {R1/(R1+R2) VO(max)
VLL = {R1/(R1+R2) VO(min)
-12V
18
FN8165.2
April 18, 2006
X9250
Application Circuits (continued)
Attenuator
Filter
C
VS
R2
R1
–
VS
+
R
VO
+
VO
–
R3
R4
R2
R1 = R2 = R3 = R4 = 10kΩ
R1
GO = 1 + R2/R1
fc = 1/(2πRC)
V O = G VS
-1/2 ≤ G ≤ +1/2
R2
}
VS
R1
}
Inverting Amplifier
Equivalent L-R Circuit
R2
C1
–
VS
VO
+
+
–
R1
ZIN
V O = G VS
G = - R2/R1
R3
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R1 + R3) >> R2
C
R2
–
+
R1
–
} RA
+
} RB
frequency ∝ R1, R2, C
amplitude ∝ RA, RB
19
FN8165.2
April 18, 2006
X9250
TSSOP Package Outline Drawing
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at
http://www.intersil.com/design/packages/index.asp
20
FN8165.2
April 18, 2006
X9250
Small Outline Plastic Packages (SOIC)
M24.3 (JEDEC MS-013-AD ISSUE C)
N
24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
H
0.25(0.010) M
B M
INCHES
E
SYMBOL
-B1
2
3
L
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
A1
B
C
0.10(0.004)
0.25(0.010) M
C A M
MIN
MAX
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
A1
0.0040
0.0118
0.10
0.30
-
B
0.013
0.020
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.5985
0.6141
15.20
15.60
3
E
0.2914
0.2992
7.40
7.60
4
e
α
B S
0.05 BSC
1.27 BSC
-
H
0.394
0.419
10.00
10.65
-
h
0.010
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
N
α
NOTES:
MILLIMETERS
24
0°
24
8°
0°
7
8°
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 4/06
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
21
FN8165.2
April 18, 2006
X9250
Printer Friendly Version
Quad Digitally Controlled Potentiometer (XDCP™)
Datasheets,
Related Docs
& Simulations
Description
Key
Features
Parametric
Data
Ordering Information
Design-In
Status
Temp.
Package
X9250TS24
Active
Comm
24 Ld SOIC
5
5.20
X9250TS24-2.7
Active
Comm
24 Ld SOIC
3
5.73
X9250TS24-2.7T1
Active
Comm 24 Ld SOIC T+R
5
5.73
X9250TS24I
Active
Ind
24 Ld SOIC
5
6.51
X9250TS24I-2.7
Active
Ind
24 Ld SOIC
5
7.16
X9250TS24I-2.7T1
Active
Ind
24 Ld SOIC T+R
5
7.16
X9250TS24I-2.7T2
Active
Ind
24 Ld SOIC T+R
5
7.16
X9250TS24IT1
Active
Ind
24 Ld SOIC T+R
5
6.51
X9250TS24IZ-2.7
Active
Ind
24 Ld SOIC
5
7.16
X9250TS24IZ-2.7T1
Active
Ind
24 Ld SOIC T+R
5
7.16
X9250TS24IZ-2.7T2
Active
Ind
24 Ld SOIC T+R
5
7.16
X9250TS24T1
Active
Comm 24 Ld SOIC T+R
5
5.20
X9250TS24Z
Active
Comm
24 Ld SOIC
5
5.20
X9250TS24Z-2.7
Active
Comm
24 Ld SOIC
5
5.73
X9250TS24Z-2.7T1
Active
Comm 24 Ld SOIC T+R
5
5.73
X9250TS24ZT1
Active
Comm 24 Ld SOIC T+R
5
5.20
X9250TV24
Active
Comm
24 Ld TSSOP
1
5.46
X9250TV24-2.7
Active
Comm
24 Ld TSSOP
1
6.01
X9250TV24I
Active
Ind
24 Ld TSSOP
1
6.83
X9250TV24I-2.7
Active
Ind
24 Ld TSSOP
1
7.52
X9250US24
Active
Comm
24 Ld SOIC
5
5.20
X9250US24-2.7
Active
Comm
24 Ld SOIC
5
5.73
X9250US24-2.7T1
Active
Comm 24 Ld SOIC T+R
5
5.73
X9250US24I
Active
Ind
24 Ld SOIC
5
6.51
X9250US24I-2.7
Active
Ind
24 Ld SOIC
5
7.16
X9250US24I-2.7T1
Active
Ind
24 Ld SOIC T+R
5
7.16
X9250US24I-2.7T2
Active
Ind
24 Ld SOIC T+R
5
7.16
X9250US24IT1
Active
Ind
24 Ld SOIC T+R
5
6.51
X9250US24IZ-2.7
Active
Ind
24 Ld SOIC
5
7.16
X9250US24IZ-2.7T1
Active
Ind
24 Ld SOIC T+R
5
7.16
X9250US24IZ-2.7T2
Active
Ind
24 Ld SOIC T+R
5
7.16
X9250US24T1
Active
Comm 24 Ld SOIC T+R
5
5.20
X9250US24Z
Active
Comm
5
5.20
Part No.
24 Ld SOIC
Price
MSL US $
Related
Devices
X9250US24Z-2.7
Active
Comm
X9250US24Z-2.7T1
Active
X9250US24ZT1
24 Ld SOIC
5
5.73
Comm 24 Ld SOIC T+R
5
5.73
Active
Comm 24 Ld SOIC T+R
5
5.20
X9250UV24
Active
Comm
24 Ld TSSOP
1
5.46
X9250UV24-2.7
Active
Comm
24 Ld TSSOP
1
6.01
X9250UV24-2.7A
Active
Comm
24 Ld TSSOP
1
6.01
X9250UV24I
Active
Ind
24 Ld TSSOP
1
6.83
X9250UV24I-2.7
Active
Ind
24 Ld TSSOP
1
7.52
X9250UV24IZ
Active
Ind
24 Ld TSSOP
5
6.83
X9250UV24IZ-2.7
Active
Ind
24 Ld TSSOP
5
7.52
X9250UV24IZ-2.7T2
Active
Ind
24 Ld TSSOP T+R
5
7.52
XLABVIEW01
Active
XLABVIEW01Z
Active
X9250TS24IZ
Coming Soon
Ind
24 Ld SOIC
3
X9250TV24IZ
Coming Soon
Ind
24 Ld TSSOP
3
X9250TV24IZ-2.7
Coming Soon
Ind
24 Ld TSSOP
3
X9250US24IZ
Coming Soon
Ind
24 Ld SOIC
3
X9250UV24Z-2.7
Coming Soon Comm
24 Ld TSSOP
3
N/A 91.77
Eval Board
N/A 91.77
X9250TS24IZT1
InActive
Ind
24 Ld SOIC T+R
3
X9250TV24Z
InActive
Comm
24 Ld TSSOP
3
X9250TV24Z-2.7
InActive
Comm
24 Ld TSSOP
3
X9250TZ24I-2.7
InActive
Ind
24 Ld TSSOP
N/A
X9250TZ24I-2.7T2
InActive
Ind
24 Ld TSSOP
3
X9250US24IZT1
InActive
Ind
24 Ld SOIC T+R
3
X9250UV24Z
InActive
Comm
24 Ld TSSOP
3
X9250UZ24I-2.7
InActive
Ind
24 Ld TSSOP
N/A
X9250UZ24I-2.7T1
InActive
Ind
6.49
6.49
6.49
6.49
24 Ld TSSOP T+R N/A
The price listed is the manufacturer's suggested retail price for quantities between 100 and
999 units. However, prices in today's market are fluid and may change without notice.
MSL = Moisture Sensitivity Level - per IPC/JEDEC J-STD-020
SMD = Standard Microcircuit Drawing
Description
The X9250 integrates 4 digitally controlled potentiometers (XDCP) on a monolithic CMOS
integrated circuit.
The digitally controlled potentiometer is implemented using 255 resistive elements in a series
array. Between each element are tap points connected to the wiper terminal through switches. The
position of the wiper on the array is controlled by the user through the SPI bus interface. Each
potentiometer has associated with it a volatile Wiper Counter Register (WCR) and 4 nonvolatile
Data Registers (DR0:DR3) that can be directly written to and read by the user. The contents of the
WCR controls the position of the wiper on the resistor array though the switches. Power up recalls
the contents of DR0 to the WCR.
The XDCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a
wide variety of applications including control, parameter adjustments, and signal processing.
Key Features
Four potentiometers in one package
256 resistor taps/pot - 0.4% resolution
SPI serial interface
Wiper resistance, 40Ω typical @ VCC = 5V
Four nonvolatile data registers for each pot
Nonvolatile storage of wiper position
Standby current < 5μA max (total package)
Power supplies
VCC = 2.7V to 5.5V
V+ = 2.7V to 5.5V
V– = -2.7V to -5.5V
100kΩ, 50kΩ total pot resistance
High reliability
Endurance – 100,000 data changes per bit per register
Register data retention - 100 years
24 Ld SOIC, 24 Ld TSSOP
Dual supply version of X9251
Pb-free plus anneal available (RoHS compliant)
Related Documentation
Application Note(s):
A Compendium of Application Circuits for Intersil’s Digitally-Controlled (XDCP)
Potentiometers
A Primer on Digitally-Controlled Potentiometers
Application of Intersil Digitally Controlled Potentiometers (XDCP™) as Hybrid Analog/Digital
Feedback System Control Elements
DC/DC Module Trim with Digital Potentiometers
Designing Power Supplies Using Intersil’s XDCP Mixed Signal Products
Power Supply and DC to DC Converter Control using Intersil Digitally Controlled
Potentiontiometers (XDCPs)
Putting Analog On The Bus
Shaft Encoder Drives Multiple Intersil Digitally Controlled Potentiontiometers (XDCPs)
Tone, Balance, and Volume Control using a Quad XDCP
Using Intersil Digitally Controlled Potentiometers in Commercial RF Power Amplifier
Applications
Datasheet(s):
Low Noise/Low Power/SPI Bus/256 Taps
Technical Brief(s):
Converting a Fixed PWM to an Adjustable PWM
Evaluation Board(s):
Intersil_XDCP_Test_Utility_Manual_rev_3.2.3.pdf
LabView_XDCP_Software.zip
LabView_XDCP_Upgrade_3.2.3.zip
Readme_XicorLabVIEW_V3.2.3.txt
XDCP_Vref Evaluation Board Kit Documentation and Software
accessHW.zip
Technical Homepage:
Digitally Controlled Potentiometers (DCPs) and Capacitors (DCCs)
Precision Analog Homepage
Parametric Data
Number of DCPs
Number of Taps
Memory Type
Bus Interface Type
Resistance Options (kΩ)
VCC Range (V)
DCP Bias Range (V)
DCP Differential Terminal Voltage (V)
V+, V- Supply Range (V)
Terminal Voltage Range VL to VH (V)
Resistance Taper
Wiper Current (mA)
Wiper Resistance (Ω)
Standby Current ISB (μA)
Quad
256
Non-Volatile
SPI
50, 100
2.7 to 5.5
-10, +10
10
2.7 to 5.5 and -5.5 to -2.7
V- to V+
Linear
±3
150
5
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