X9251
®
Single Supply/Low Power/256-Tap/SPI Bus
Data Sheet
April 13, 2007
FN8166.5
Quad Digitally-Controlled (XDCP™)
Potentiometer
Features
The X9251 integrates four digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated circuit.
• 256 resistor taps–0.4% resolution
• Four potentiometers in one package
• SPI Serial Interface for write, read, and transfer operations
of the potentiometer
The digitally controlled potentiometers are imple-mented
with a combination of resistor elements and CMOS switches.
The position of the wipers are controlled by the user through
the SPI bus interface. Each potentiometer has associated
with it a volatile Wiper Counter Register (WCR) and four
non-volatile Data Registers that can be directly written to and
read by the user. The content of the WCR controls the
position of the wiper. At power-up, the device recalls the
content of the default Data Registers of each DCP (DR00,
DR10, DR20, and DR30) to the corresponding WCR.
• Wiper resistance: 100Ω typical @ VCC = 5V
• 4 Non-volatile data registers for each
potentiometer
• Non-volatile storage of multiple wiper positions
• Standby current VH, VL, and VW.
5. n = 0, 1, 2, …,255; m = 0, 1, 2, …, 254.
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X9251
DC Operating Characteristics (Over the recommended operating conditions unless otherwise specified.)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP
MAX
UNITS
400
μA
5
mA
ICC1
VCC supply current
(active)
fSCK = 2.5 MHz, SO = Open, VCC = 6V
Other Inputs = VSS
ICC2
VCC supply current
(non-volatile write)
fSCK = 2.5MHz, SO = Open, VCC = 6V
Other Inputs = VSS
ISB
VCC current (standby)
SCK = SI = VSS, Addr. = VSS,
CS = VCC = 6V
3
μA
1
ILI
Input leakage current
VIN = VSS to VCC
10
μA
ILO
Output leakage current
VOUT = VSS to VCC
10
μA
VIH
Input HIGH voltage
VCC x 0.7
V
VIL
Input LOW voltage
VOL
Output LOW voltage
IOL = 3mA
VOH
Output HIGH voltage
IOH = -1mA, VCC ≥ +3V
VCC - 0.8
V
VOH
Output HIGH voltage
IOH = -0.4mA, VCC ≤ +3V
VCC - 0.4
V
VCC x 0.3
V
0.4
V
Endurance and Data Retention
PARAMETER
Minimum endurance
Data retention
MIN
UNITS
100,000
Data changes per bit per register
100
years
Capacitance
SYMBOL
TEST
TYP
UNITS
VOUT = 0V
8
pF
Output capacitance (SO)
VOUT = 0V
8
pF
Input capacitance (A0, A1, CS, WP, HOLD, and SCK)
VIN = 0V
6
pF
CIN/OUT (Note 6) Input/Output capacitance (SI)
COUT (Note 6)
CIN (Note 6)
TEST CONDITIONS
Power-Up Timing
SYMBOL
PARAMETER
MIN
MAX
UNITS
tr VCC (Note 6)
VCC Power-up rate
tPUR (Note 7)
Power-up to initiation of read operation
1
ms
tPUW (Note 7)
Power-up to initiation of write operation
50
ms
0.2
V/ms
A.C. Test Conditions
Input Pulse Levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
10ns
Input and output timing level
VCC x 0.5
NOTES:
6. This parameter is not 100% tested
7. tPUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued. These
parameters are periodically sampled and not 100% tested.
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April 13, 2007
X9251
Equivalent A.C. Load Circuit
VCC
SPICE Macromodel
2kΩ
RTOTAL
RL
RH
SO pin
CW
CL
2kΩ
10pF
CL
10pF
25pF
10pF
RW
AC TIMING
SYMBOL
PARAMETER
MIN
MAX
UNITS
2
MHz
fSCK
SPI clock frequency
tCYC
SPI clock cycle rime
500
ns
tWH
SPI clock high rime
200
ns
tWL
SPI clock low time
200
ns
tLEAD
Lead time
250
ns
tLAG
Lag time
250
ns
tSU
SI, SCK, HOLD and CS input setup time
50
ns
tH
SI, SCK, HOLD and CS input hold time
50
ns
tRI
SI, SCK, HOLD and CS input rise time
2
μs
tFI
SI, SCK, HOLD and CS input fall time
2
μs
250
ns
200
ns
tDIS
SO output disable time
tV
SO output valid time
0
tHO
SO output hold time
tRO (Note 6)
SO output rise time
100
ns
tFO (Note 6)
SO output fall time
100
ns
tHOLD
0
HOLD time
ns
400
ns
tHSU
HOLD setup time
100
ns
tHH
HOLD hold time
100
ns
tHZ
HOLD low to output in high Z
100
ns
tLZ
HOLD high to output in low Z
100
ns
TI
Noise suppression time constant at SI, SCK, HOLD and CS inputs
10
ns
tCS
CS deselect time
2
μs
tWPASU
WP, A0 setup time
0
ns
tWPAH
WP, A0 hold time
0
ns
High-Voltage Write Cycle Timing
SYMBOL
tWR
PARAMETER
High-voltage write cycle time (store instructions)
TYP
MAX
UNITS
5
10
ms
XDCP Timing
SYMBOL
tWRPO (Note 6)
tWRL (Note 6)
MIN
MAX
UNITS
Wiper response time after the third (last) power supply is stable
PARAMETER
5
10
μs
Wiper response time after instruction issued (all load instructions)
5
10
μs
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April 13, 2007
X9251
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
Timing Diagrams
Input Timing
tCS
CS
SCK
tSU
tH
tLAG
tCYC
tLEAD
...
tWH
tWL
...
SI
MSB
SO
HIGH IMPEDANCE
tRI
tFI
LSB
Output Timing
CS
SCK
...
tV
MSB
SO
SI
tHO
tDIS
...
LSB
ADDR
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April 13, 2007
X9251
Hold Timing
CS
tHSU
tHH
SCK
...
tRO
tFO
SO
tHZ
tLZ
SI
tHOLD
HOLD
XDCP Timing (for All Load Instructions)
CS
SCK
...
tWRL
SI
...
MSB
LSB
VWx
SO
HIGH IMPEDANCE
Write Protect and Device Address Pins Timing
(ANY INSTRUCTION)
CS
tWPASU
tWPAH
WP
A0
A1
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X9251
Applications information
Basic Configurations of Electronic Potentiometers
+VR
VR
RW
I
Three terminal
Potentiometer;
Variable voltage divider
Two terminal Variable
Resistor;
Variable current
Application Circuits
NON INVERTING AMPLIFIER
VS
VOLTAGE REGULATOR
+
VO
–
VIN
VO (REG)
317
R1
R2
Iadj
R1
R2
VO = (1+R2/R1)VS
VO (REG) = 1.25V (1+R2/R1)+Iadj R2
OFFSET VOLTAGE ADJUSTMENT
R1
COMPARATOR WITH HYSTERESIS
R2
VS
VS
–
+
100kΩ
–
VO
+
+12V
10kΩ
}
10kΩ
}
TL072
10kΩ
VO
R1
R2
VUL = {R1/(R1+R2)} VO(max)
RLL = {R1/(R1+R2)} VO(min)
-12V
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X9251
Application Circuits (continued)
ATTENUATOR
FILTER
C
VS
R2
R1
VO
–
–
VS
+
R
VO
+
R3
R4
R2
R1 = R2 = R3 = R4 = 10kΩ
R1
GO = 1 + R2/R1
fc = 1/(2πRC)
VO = G VS
-1/2 ≤ G ≤ +1/2
R1
R2
}
VS
}
INVERTING AMPLIFIER
EQUIVALENT L-R CIRCUIT
R2
C1
–
VS
VO
+
+
–
R1
ZIN
VO = G VS
G = - R2/R1
R3
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R1 + R3) >> R2
FUNCTION GENERATOR
C
R2
–
+
R1
–
} RA
+
} RB
frequency ∝ R1, R2, C
amplitude ∝ RA, RB
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April 13, 2007
X9251
Small Outline Plastic Packages (SOIC)
M24.3 (JEDEC MS-013-AD ISSUE C)
N
24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
H
0.25(0.010) M
B M
INCHES
E
SYMBOL
-B1
2
3
L
SEATING PLANE
-A-
A
D
h x 45°
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
MIN
MAX
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
A1
0.0040
0.0118
0.10
0.30
-
B
0.013
0.020
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.5985
0.6141
15.20
15.60
3
E
0.2914
0.2992
7.40
7.60
4
e
α
B S
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
0.05 BSC
1.27 BSC
-
H
0.394
0.419
10.00
10.65
-
h
0.010
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
N
α
NOTES:
MILLIMETERS
24
0°
24
8°
0°
7
8°
Rev. 1 4/06
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
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April 13, 2007
X9251
Thin Shrink Small Outline Package Family (TSSOP)
MDP0044
0.25 M C A B
D
THIN SHRINK SMALL OUTLINE PACKAGE FAMILY
A
(N/2)+1
N
MILLIMETERS
SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE
PIN #1 I.D.
E
E1
1
(N/2)
B
0.20 C B A
2X
N/2 LEAD TIPS
TOP VIEW
0.05
e
C
SEATING
PLANE
H
A
1.20
1.20
1.20
1.20
1.20
Max
A1
0.10
0.10
0.10
0.10
0.10
±0.05
A2
0.90
0.90
0.90
0.90
0.90
±0.05
b
0.25
0.25
0.25
0.25
0.25
+0.05/-0.06
c
0.15
0.15
0.15
0.15
0.15
+0.05/-0.06
D
5.00
5.00
6.50
7.80
9.70
±0.10
E
6.40
6.40
6.40
6.40
6.40
Basic
E1
4.40
4.40
4.40
4.40
4.40
±0.10
e
0.65
0.65
0.65
0.65
0.65
Basic
L
0.60
0.60
0.60
0.60
0.60
±0.15
L1
1.00
1.00
1.00
1.00
1.00
Reference
Rev. F 2/07
0.10 M C A B
b
0.10 C
N LEADS
SIDE VIEW
NOTES:
1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.
SEE DETAIL “X”
3. Dimensions “D” and “E1” are measured at dAtum Plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
c
END VIEW
L1
A
A2
GAUGE
PLANE
0.25
L
A1
0° - 8°
DETAIL X
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FN8166.5
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