X9251US24-2.7

DATASHEET X9251 FN8166 Rev 7.00 January 14, 2021 Single Supply/Low Power/256-Tap/SPI Bus, Quad Digitally-Controlled (XDCP™) Potentiometer Features The X9251 integrates four digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated circuit. • Four potentiometers in one package The digitally controlled potentiometers are implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the SPI bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and four nonvolatile Data Registers that can be directly written to and read by the user. The content of the WCR controls the position of the wiper. At power-up, the device recalls the content of the default Data Registers of each DCP (DR00, DR10, DR20, and DR30) to the corresponding WCR. • 256 resistor taps–0.4% resolution • SPI serial interface for write, read, and transfer operations of the potentiometer • Wiper resistance: 100Ω typical at VCC = 5V • 4 Nonvolatile data registers for each potentiometer • Nonvolatile storage of multiple wiper positions • Standby current VH, VL, and VW. 13. n = 0, 1, 2, …,255; m = 0, 1, 2, …, 254. 14. This parameter is not 100% tested 15. tPUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued. These parameters are periodically sampled and not 100% tested. Equivalent AC Load Circuit VCC SPICE MACROMODEL RTOTAL 2kΩ RH RL CW CL SO PIN 2kΩ CL 10pF 25pF 10pF 10pF RW FN8166 Rev 7.00 January 14, 2021 Page 13 of 20 X9251 AC TIMING SYMBOL PARAMETER MIN TYP MAX UNITS 2 MHz fSCK SPI clock frequency tCYC SPI Clock Cycle Time 500 ns tWH SPI Clock High Time 200 ns tWL SPI Clock Low Time 200 ns tLEAD Lead Time 250 ns tLAG Lag Time 250 ns tSU SI, SCK, HOLD and CS Input Setup Time 50 ns tH SI, SCK, HOLD and CS Input Hold Time 50 ns tRI SI, SCK, HOLD and CS Input Rise Time 2 µs tFI SI, SCK, HOLD and CS Input Fall Time 2 µs 250 ns 200 ns tDIS SO Output Disable Time tV SO Output Valid Time tHO SO Output Hold Time 0 0 ns tRO (Note 14) SO Output Rise Time 100 ns tFO (Note 14) SO Output Fall Time 100 ns tHOLD HOLD Time 400 ns tHSU HOLD Setup Time 100 ns tHH HOLD Hold Time 100 ns tHZ HOLD Low to Output in High Z 100 ns tLZ HOLD High to Output in Low Z 100 ns TI Noise Suppression Time Constant at SI, SCK, HOLD and CS Inputs 10 ns CS Deselect Time 2 µs tWPASU WP, A0 Setup Time 0 ns tWPAH WP, A0 Hold Time 0 ns tCS High-Voltage Write Cycle Timing SYMBOL tWR PARAMETER TYP MAX UNITS 5 10 ms MIN MAX UNITS Wiper response time after the third (last) power supply is stable 5 10 µs Wiper response time after instruction issued (all load instructions) 5 10 µs High-voltage write cycle time (store instructions) XDCP Timing SYMBOL tWRPO (Note 14) tWRL (Note 14) PARAMETER FN8166 Rev 7.00 January 14, 2021 Page 14 of 20 X9251 Symbol Table WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from Low to High Will change from Low to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance Timing Diagrams Input Timing tCS CS tCYC tLEAD SCK tSU tH tLAG ... tWH tWL ... SI MSB SO HIGH IMPEDANCE tRI tFI LSB Output Timing CS SCK ... tV MSB SO SI tHO tDIS ... LSB ADDR FN8166 Rev 7.00 January 14, 2021 Page 15 of 20 X9251 Hold Timing CS tHSU tHH SCK ... tRO tFO SO tHZ tLZ SI tHOLD HOLD XDCP Timing (for All Load Instructions) CS SCK ... tWRL ... MSB SI LSB VWx SO HIGH IMPEDANCE Write Protect and Device Address Pins Timing (ANY INSTRUCTION) CS tWPASU tWPAH WP A0 A1 FN8166 Rev 7.00 January 14, 2021 Page 16 of 20 X9251 Applications information Basic Configurations of Electronic Potentiometers +VR VR RW I Three terminal Potentiometer; Variable voltage divider Two terminal Variable Resistor; Variable current Application Circuits NON INVERTING AMPLIFIER VS VOLTAGE REGULATOR + VO – VIN VO (REG) 317 R1 R2 Iadj R1 R2 VO = (1 + R2/R1)VS VO (REG) = 1.25V (1 + R2/R1) + Iadj R2 OFFSET VOLTAGE ADJUSTMENT R1 COMPARATOR WITH HYSTERESIS R2 VS VS – + 100kΩ VO – VO + +12V FN8166 Rev 7.00 January 14, 2021 10kΩ } 10kΩ } TL072 10kΩ R1 R2 VUL = {R1/(R1 + R2)} VO(max) RLL = {R1/(R1 + R2)} VO(min) -12V Page 17 of 20 X9251 Application Circuits (continued) ATTENUATOR FILTER C VS + R2 R1 VS VO – – R VO + R3 R4 R2 R1 = R2 = R3 = R4 = 10kΩ R1 GO = 1 + R2/R1 fc = 1/(2πRC) VO = G V S -1/2 ≤ G ≤ +1/2 R2 } VS R1 } INVERTING AMPLIFIER EQUIVALENT L-R CIRCUIT R2 C1 – VS VO + + – R1 ZIN VO = G V S G = - R2/R1 R3 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2 FUNCTION GENERATOR C R2 – R1 – + } RA + } RB FREQUENCY ∝ R1, R2, C AMPLITUDE ∝ RA, RB FN8166 Rev 7.00 January 14, 2021 Page 18 of 20 X9251 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION January 14, 2021 FN8166.7 Updated AC Timing table: the value of TI changed from 10ns (MAX) to 10ns (TYP). Updated Ordering Information. Removed about Intersil section. December 3, 2014 FN8166.6 Updated to Intersil new standards. Updated Ordering Information Table on page 3, by removing obsoleted parts and 100kΩ referenced parts, adding Note 3 and changed TSSOP POD references from “MDP0044” to “M24.173”. Added Revision History and About Intersil verbiage. Updated M24.3 POD to the latest revision. -“Updated to new POD standard by removing table listing dimensions and putting dimensions on drawing. Added Land Pattern.” Replaced MDP0044 POD with M24.173 POD to update to new format and only show 24 Ld version. FN8166 Rev 7.00 January 14, 2021 CHANGE Page 19 of 20 X9251 Package Outline Drawing For the most recent package outline drawing, see M24.173. M24.173 24 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) Rev 1, 5/10 A 1 3 7.80 ±0.10 SEE DETAIL "X" 13 24 6.40 PIN #1 I.D. MARK 4.40 ±0.10 2 3 0.20 C B A 1 12 0.15 +0.05 -0.06 B 0.65 TOP VIEW END VIEW 1.00 REF H - 0.05 C 0.90 +0.15 -0.10 1.20 MAX GAUGE PLANE SEATING PLANE 0.25 +0.05 -0.06 0.10 M C B A 0.10 C 5 0°-8° 0.05 MIN 0.15 MAX SIDE VIEW 0.25 0.60± 0.15 DETAIL "X" (1.45) NOTES: 1. Dimension does not include mold flash, protrusions or gate burrs. (5.65) Mold flash, protrusions or gate burrs shall not exceed 0.15 per side. 2. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25 per side. 3. Dimensions are measured at datum plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Dimension does not include dambar protrusion. Allowable protrusion shall be 0.08mm total in excess of dimension at maximum material condition. Minimum space between protrusion and adjacent lead (0.65 TYP) (0.35 TYP) TYPICAL RECOMMENDED LAND PATTERN is 0.07mm. 6. Dimension in ( ) are for reference only. 7. Conforms to JEDEC MO-153. FN8166 Rev 7.00 January 14, 2021 Page 20 of 20 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. 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