DATASHEET
Single Supply/Low Power/256-Tap/SPI Bus, Quad
Digitally-Controlled (XDCP™) Potentiometer
X9251
Features
The X9251 integrates four digitally controlled potentiometers
(XDCP) on a monolithic CMOS integrated circuit.
• Four potentiometers in one package
The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
SPI bus interface. Each potentiometer has associated with it a
volatile Wiper Counter Register (WCR) and four nonvolatile
Data Registers that can be directly written to and read by the
user. The content of the WCR controls the position of the wiper.
At power-up, the device recalls the content of the default Data
Registers of each DCP (DR00, DR10, DR20, and DR30) to the
corresponding WCR.
• SPI serial interface for write, read, and transfer operations of
the potentiometer
• 256 resistor taps–0.4% resolution
• Wiper resistance: 100Ω typical at VCC = 5V
• 4 Nonvolatile data registers for each potentiometer
• Nonvolatile storage of multiple wiper positions
• Standby current VH, VL, and VW.
13. n = 0, 1, 2, …,255; m = 0, 1, 2, …, 254.
14. This parameter is not 100% tested
15. tPUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued. These
parameters are periodically sampled and not 100% tested.
Equivalent AC Load Circuit
VCC
SPICE MACROMODEL
RTOTAL
2kΩ
RH
RL
CW
CL
SO PIN
2kΩ
CL
10pF
25pF
10pF
10pF
RW
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X9251
AC TIMING
SYMBOL
PARAMETER
MIN
MAX
UNITS
2
MHz
fSCK
SPI clock frequency
tCYC
SPI Clock Cycle Time
500
ns
tWH
SPI Clock High Time
200
ns
tWL
SPI Clock Low Time
200
ns
tLEAD
Lead Time
250
ns
tLAG
Lag Time
250
ns
tSU
SI, SCK, HOLD and CS Input Setup Time
50
ns
tH
SI, SCK, HOLD and CS Input Hold Time
50
ns
tRI
SI, SCK, HOLD and CS Input Rise Time
tFI
SI, SCK, HOLD and CS Input Fall Time
tDIS
SO Output Disable Time
tV
SO Output Valid Time
tHO
SO Output Hold Time
0
2
µs
2
µs
250
ns
200
ns
0
ns
tRO (Note 14)
SO Output Rise Time
100
ns
tFO (Note 14)
SO Output Fall Time
100
ns
tHOLD
HOLD Time
400
ns
tHSU
HOLD Setup Time
100
ns
tHH
HOLD Hold Time
100
tHZ
HOLD Low to Output in High Z
100
ns
tLZ
HOLD High to Output in Low Z
100
ns
TI
Noise Suppression Time Constant at SI, SCK, HOLD and CS Inputs
10
ns
ns
CS Deselect Time
2
µs
tWPASU
WP, A0 Setup Time
0
ns
tWPAH
WP, A0 Hold Time
0
ns
tCS
High-Voltage Write Cycle Timing
SYMBOL
tWR
PARAMETER
TYP
MAX
UNITS
5
10
ms
MIN
MAX
UNITS
Wiper response time after the third (last) power supply is stable
5
10
µs
Wiper response time after instruction issued (all load instructions)
5
10
µs
High-voltage write cycle time (store instructions)
XDCP Timing
SYMBOL
tWRPO (Note 14)
tWRL (Note 14)
PARAMETER
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X9251
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
Timing Diagrams
Input Timing
tCS
CS
tCYC
tLEAD
SCK
tSU
tH
tLAG
...
tWH
tWL
...
SI
MSB
SO
HIGH IMPEDANCE
tRI
tFI
LSB
Output Timing
CS
SCK
...
tV
MSB
SO
SI
tHO
tDIS
...
LSB
ADDR
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X9251
Hold Timing
CS
tHSU
tHH
SCK
...
tRO
tFO
SO
tHZ
tLZ
SI
tHOLD
HOLD
XDCP Timing (for All Load Instructions)
CS
SCK
...
tWRL
...
MSB
SI
LSB
VWx
SO
HIGH IMPEDANCE
Write Protect and Device Address Pins Timing
(ANY INSTRUCTION)
CS
tWPASU
tWPAH
WP
A0
A1
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X9251
Applications information
Basic Configurations of Electronic Potentiometers
+VR
VR
RW
I
Three terminal Potentiometer;
Variable voltage divider
Two terminal Variable Resistor;
Variable current
Application Circuits
NON INVERTING AMPLIFIER
VS
VOLTAGE REGULATOR
+
VO
–
VIN
VO (REG)
317
R1
R2
Iadj
R1
R2
VO = (1 + R2/R1)VS
VO (REG) = 1.25V (1 + R2/R1) + Iadj R2
OFFSET VOLTAGE ADJUSTMENT
R1
COMPARATOR WITH HYSTERESIS
R2
VS
VS
–
+
100kΩ
VO
–
VO
+
+12V
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10kΩ
}
10kΩ
}
TL072
10kΩ
R1
R2
VUL = {R1/(R1 + R2)} VO(max)
RLL = {R1/(R1 + R2)} VO(min)
-12V
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X9251
Application Circuits (continued)
ATTENUATOR
FILTER
C
VS
+
R2
R1
VS
VO
–
–
R
VO
+
R3
R4
R2
R1 = R2 = R3 = R4 = 10kΩ
R1
GO = 1 + R2/R1
fc = 1/(2RC)
VO = G VS
-1/2 G +1/2
R2
}
VS
R1
}
INVERTING AMPLIFIER
EQUIVALENT L-R CIRCUIT
R2
C1
–
VS
VO
+
+
–
R1
ZIN
VO = G VS
G = - R2/R1
R3
ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq
(R1 + R3) >> R2
FUNCTION GENERATOR
C
R2
–
R1
–
+
} RA
+
} RB
FREQUENCY R1, R2, C
AMPLITUDE RA, RB
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X9251
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
CHANGE
December 3, 2014
FN8166.6
Updated to Intersil new standards.
Updated Ordering Information Table on page 3, by removing obsoleted parts and 100kΩ referenced parts, adding
Note 3 and changed TSSOP POD references from “MDP0044” to “M24.173”.
Added Revision History and About Intersil verbiage.
Updated M24.3 POD to the latest revision.
-“Updated to new POD standard by removing table listing dimensions and putting dimensions on drawing.
Added Land Pattern.”
Replaced MDP0044 POD with M24.173 POD to update to new format and only show 24 Ld version.
About Intersil
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address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
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Reliability reports are also available from our website at www.intersil.com/support
For additional products, see www.intersil.com/en/products.html
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in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
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X9251
Package Outline Drawing
M24.3
24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE (SOIC)
Rev 2, 3/11
24
INDEX
AREA
7.60 (0.299)
7.40 (0.291) 10.65 (0.419)
10.00 (0.394)
DETAIL "A"
1
2
3
TOP VIEW
1.27 (0.050)
0.40 (0.016)
SEATING PLANE
2.65 (0.104)
2.35 (0.093)
15.60 (0.614)
15.20 (0.598)
0.75 (0.029)
x 45°
0.25 (0.010)
0.30 (0.012)
0.10 (0.004)
1.27 (0.050)
0.51 (0.020)
0.33 (0.013)
8°
0°
0.32 (0.012)
0.23 (0.009)
SIDE VIEW “B”
SIDE VIEW “A”
1.981 (0.078)
9.373 (0.369)
1.27 (0.050)
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1982.
2. Package length does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
3. Package width does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm
(0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch).
7. Controlling dimension: MILLIMETER. Converted inch dimensions in
( ) are not necessarily exact.
8. This outline conforms to JEDEC publication MS-013-AD ISSUE C.
0.533 (0.021)
TYPICAL RECOMMENDED LAND PATTERN
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X9251
Package Outline Drawing
M24.173
24 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 1, 5/10
A
1
3
7.80 ±0.10
SEE DETAIL "X"
13
24
6.40
PIN #1
I.D. MARK
4.40 ±0.10
2
3
0.20 C B A
1
12
0.15 +0.05
-0.06
B
0.65
TOP VIEW
END VIEW
1.00 REF
H
- 0.05
C
0.90 +0.15
-0.10
1.20 MAX
GAUGE
PLANE
SEATING PLANE
0.25 +0.05
-0.06
0.10 M C B A
0.10 C
5
0°-8°
0.05 MIN
0.15 MAX
SIDE VIEW
0.25
0.60± 0.15
DETAIL "X"
(1.45)
NOTES:
1. Dimension does not include mold flash, protrusions or gate burrs.
(5.65)
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
3. Dimensions are measured at datum plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.08mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead
(0.65 TYP)
(0.35 TYP)
TYPICAL RECOMMENDED LAND PATTERN
is 0.07mm.
6. Dimension in ( ) are for reference only.
7. Conforms to JEDEC MO-153.
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