X9252UV24I-2.7

DATASHEET X9252 FN8167 Rev 3.1 Jul 1, 2021 Low Power + Quad 256-tap + 2-Wire Bus + Up/Down Interface Quad Digitally-Controlled (XDCP™) Potentiometer Features The X9252 integrates 4 digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated circuit. • Quad Solid State Potentiometer The digitally controlled potentiometers are implemented using 255 resistive elements in a series array. Between each pair of elements are tap points connected to wiper terminals through switches. The position of each wiper on the array is controlled by the user through the Up/Down (U/D) or 2-wire bus interface. The wiper of each potentiometer has an associated volatile Wiper Counter Register (WCR) and four nonvolatile Data Registers (DRs) that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array through the switches. At power-up, the device recalls the contents of the default data registers DR00, DR10, DR20, DR30, to the corresponding WCR. • 256 Wiper Tap Points-0.4% Resolution • 2-Wire Serial Interface for Write, Read, and Transfer Operations of the Potentiometer • Up/Down Interface for Individual Potentiometers • Wiper Resistance: 40 Typical • NonVolatile Storage of Wiper Positions • Power On Recall. Loads Saved Wiper Position on Power-Up. • Standby Current < 100µA Max • Maximum Wiper Current: 3mA Each DCP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including the programming of bias voltages, the implementation of ladder networks, and three resistor programmable networks. • VCC: 2.7V to 5.5V Operation • 2.8k and 10k Version of Total Pot Resistance • Endurance: 100,000 Data Changes per Bit per Register • 100 yr. Data Retention • 24 Ld TSSOP • Pb-Free (RoHS Compliant) RH1 RH0 VCC RH3 RH2 A2 A1 2-Wire Interface WCR0 DR00 DR01 DR02 DR03 A0 SDA SCL DS0 Up-Down Interface POWER-UP, INTERFACE CONTROL AND STATUS DCP0 WCR1 DR10 DR11 DR12 DR13 DCP1 WCR2 DR20 DR21 DR22 DR23 DCP2 WCR3 DR30 DR31 DR32 DR33 DCP3 DS1 CS U/D VSS WP RW0 RL0 RW1 RL1 RW2 RL2 RW3 RL3 FIGURE 1. Functional Diagram FN8167 Rev 3.1 Jul 1, 2021 Page 1 of 19 © 2005 Renesas Electronics X9252 Ordering Information PART NUMBER (Notes 1, 2) PART MARKING RTOTAL (k) PACKAGE DESCRIPTION (RoHS Compliant) 24 Ld TSSOP (4.4mm) X9252YV24IZ-2.7 X9252YV ZG 2.8 X9252WV24IZ-2.7 X9252WV ZG 10 PKG. DWG. # CARRIER TYPE M24.173 Tube TEMP RANGE -40 to +85°C NOTES: 1. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. For Moisture Sensitivity Level (MSL), see X9252 device information page. For more information about MSL, see TB363 Pinout (24 LD TSSOP) TOP VIEW 1 24 DS1 A0 2 23 SCL RW3 3 22 RL2 RH3 4 21 RH2 RL3 DS0 5 20 RW2 U/D 6 19 CS VCC 7 18 VSS RL0 8 17 RW1 RH0 9 16 RH1 RW0 10 15 RL1 A2 11 14 A1 WP 12 13 SDA Pin Descriptions PIN # SYMBOL DESCRIPTION 1, 24 DS0, DS1 DCP select for Up/Down interface. 2, 14, 11 A0, A1, A2 Device address for 2-wire bus. 3 RW3 Wiper terminal of DCP3. 4 RH3 High terminal of DCP3. 5 RL3 Low terminal of DCP3. 6 U/D Increment/decrement for up/down interface. 7 VCC System supply voltage 8 RL0 Low terminal of DCP0. 9 RH0 High terminal of DCP0. 10 RW0 Wiper terminal of DCP0. 12 WP Hardware write protect 13 SDA Serial data input/output for 2-wire bus. 15 RL1 Low terminal of DCP1. 16 RH1 High terminal of DCP1. 17 RW1 Wiper terminal DCP1. 18 VSS System ground 19 CS Chip select for Up/Down interface. 20 RW2 FN8167 Rev 3.1 Jul 1, 2021 Wiper terminal of DCP2. Page 2 of 19 X9252 Pin Descriptions (Continued) PIN # SYMBOL DESCRIPTION 21 RH2 High terminal of DCP2. 22 RL2 Low terminal of DCP2. 23 SCL Serial clock for 2-wire bus. Pin Descriptions DCP Select (DS1 and DS0) Bus Interface Pins The DS1 and DS0 select one of the four DCPs for an Up/Down interface operation. Serial Data Input/Output (SDA) The SDA is a bidirectional serial data input/output pin for the 2wire interface. It receives device address, operation code, wiper register address and data from a 2-wire external master device at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock SCL. SDA requires an external pull-up resistor, since it’s an open drain output. Serial Clock (SCL) This input is the serial clock of the 2-wire and Up/Down interface. Device Address (A0, A1, A2) The Address inputs are used to set the least significant 3 bits of the 8-bit 2-wire interface slave address. A match in the slave address serial data stream must be made with the Address input pins in order to initiate communication with the X9252. A maximum of 8 devices may occupy the 2-wire serial bus. Hardware Write Protect Input (WP) When the WP pin is set low, “write” operations to nonvolatile DCP Data Registers are disabled. This includes both 2-wire interface nonvolatile “Write”, and Up/Down interface “Store” operations. DCP Pins RH0, RL0, RH1, RL1, RH2, RL2, RH3, and RL3 These pins are equivalent to the terminal connections on mechanical potentiometers. Since there are 4 DCPs, there is one set of RH and RL for each DCP. RW0, RW1, RW2, and RW3 The wiper pins are equivalent to the wiper terminal of mechanical potentiometers. Since there are four DCPs, there are 4 RW pins. Chip Select (CS) When the CS pin is low, increment or decrement operations are possible using the SCL and U/D pins. The 2-wire interface is disabled at this time. When CS is high, the 2-wire interface is enabled. Up or Down Control (U/D) The U/D input pin is held HIGH during increment operations and held LOW during decrement operations. FN8167 Rev 3.1 Jul 1, 2021 Page 3 of 19 X9252 Absolute Maximum Ratings Recommended Operating Conditions Junction Temperature Under Bias . . . . . . . . . . . . . .-65C to +135C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Voltage at any Digital Interface Pin with Respect to VSS, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V Voltage at any DCP Pin with Respect to VSS . . . . . . . . . -1V to VCC Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . . 300C IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA Latch-Up Robustness All pins except SDA (Pin 13) . . . . . . . . . . . . . . . ±100mA @ 85°C SDA (Pin 13): . . . . . . . . . . . . . . . . . . . . . +100mA, -40mA @ 85°C Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C Supply Voltage (VCC) (Note 6) Limits . . . . . . . . . . . . . . 2.7V to 5.5V Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. Analog Specifications Across recommended operating conditions unless otherwise stated. Boldface limits apply across the operating temperature range, -40°C to +85°C. SYMBOL RTOTAL PARAMETER End-to-End Resistance TEST CONDITIONS MIN (Note 12) Y, W versions respectively Power Rating Wiper Current (Note 7) RW Wiper Resistance VTERM +25°C, each DCP DCP to DCP Resistance Matching IW 0.75 See “Test Circuit” on page 8 Wiper current = Noise (Note 7) -3.0 50 VCC RTOTAL VSS Voltage on any DCP Pin Ref: 1kHz Resolution Absolute Linearity (Note 3) V(RH0) = V(RH1) = V(RH2) = V(RH3) = VCC V(RL0) = V(RL1) = V(RL2) = V(RL3) = VSS Relative linearity (Note 4) IOL k +20 % 50 mW 2.0 % +3.0 mA 150  VCC V -120 dBV 0.4 % +1 MI (Note 5) -0.3 +0.3 MI (Note 5) 300 -20 Ratiometric Temperature (Note 7) Coefficient Potentiometer Capacitance (Note 7) See “Equivalent Circuit” on page 8 Leakage on DCP Pins Voltage at pin from VSS to VCC UNIT -1 Temperature coefficient of resistance (Note 7) CH/CL/CW MAX (Note 12) 2.8, 10 -20 End-to-End Resistance Tolerance RTOTAL Matching TYP (Note 6) ppm/C +20 ppm/°C 10 µA 10/10/25 0.1 pF DC Electrical Specifications Across the recommended operating conditions unless otherwise specified. Boldface limits apply across the operating temperature range, -40°C to +85°C. SYMBOL PARAMETER TEST CONDITIONS MIN MAX (Note 12) (Note 12) UNITS ICC1 VCC Supply Current (Volatile Write/Read) fSCL = 400kHz; SDA = open; (for 2-wire, active, read and volatile write states only) 3 mA ICC2 VCC Supply Current (Active) fSCL = 200kHz; (for U/D interface, increment, decrement) 3 mA ICC3 VCC Supply Current (Nonvolatile Write) fSCL = 400kHz; SDA = Open; (for 2-wire, active, nonvolatile write state only) 5 mA VCC Current (Standby) VCC = +5.5V; VIN = VSS or VCC; SDA = VCC; (for 2-Wire, standby state only) 100 µA Leakage Current, Bus Interface Pins Voltage at pin from VSS to VCC -10 10 µA VCC x 0.7 VCC + 1 V ISB IL VIH Input HIGH Voltage FN8167 Rev 3.1 Jul 1, 2021 Page 4 of 19 X9252 DC Electrical Specifications Across the recommended operating conditions unless otherwise specified. Boldface limits apply across the operating temperature range, -40°C to +85°C. SYMBOL PARAMETER VIL Input LOW Voltage VOL SDA Pin Output LOW Voltage MIN MAX (Note 12) (Note 12) TEST CONDITIONS -1 UNITS VCC x 0.3 V 0.4 V IOL = 3mA Endurance and Data Retention PARAMETER MIN UNITS Minimum Endurance 100,000 Data changes per bit Data Retention 100 Years Capacitance Symbol Test CIN/OUT (Note 7) Input/Output Capacitance (SDA) CIN (Note 7) Input Capacitance (SCL, WP, DS0, DS1, CS, U/D, A2, A1 and A0) Test Conditions Max UNITS VOUT = 0V 8 pF VIN = 0V 6 pF Power-Up Timing SYMBOL PARAMETER MAX UNITS tD (Notes 7, 11) Power-Up Delay from VCC Power-Up (VCC above 2.7V) to Wiper Position Recall Completed, and Communication Interfaces Ready for Operation. 2 ms A.C. Test Conditions Input Pulse Levels VCC x 0.1 to VCC x 0.9 Input Rise and Fall Times 10ns Input and Output Timing Threshold Level VCC x 0.5 External Load at Pin SDA 2.3k to VCC and 100pF to VSS 2-Wire Interface Timing (s) SYMBOL PARAMETER MIN MAX UNITS 400 kHz fSCL Clock Frequency tHIGH Clock High Time 600 ns tLOW Clock Low Time 1300 ns tSU:STA Start Condition Setup Time 600 ns tHD:STA Start Condition Hold Time 600 ns tSU:STO Stop Condition Setup Time 600 ns tSU:DAT SDA Data Input Setup Time 100 ns tHD:DAT SDA Data Input Hold Time 30 ns tR (Note 7) SCL and SDA Rise Time 300 ns tF (Note 7) SCL and SDA Fall Time 300 ns tAA (Note 7) SCL Low to SDA Data Output Valid Time 0.9 µs tDH SDA Data Output Hold Time tIN (Note 7) Pulse Width Suppression Time at SCL and SDA inputs tBUF (Note 7) Bus Free Time (Prior to Any Transmission) FN8167 Rev 3.1 Jul 1, 2021 0 ns 50 1200 ns ns Page 5 of 19 X9252 2-Wire Interface Timing (s) (Continued) SYMBOL PARAMETER MIN MAX UNITS tSU:WPA (Note 7) A0, A1, A2 and WP Setup Time 600 ns tHD:WPA (Note 7) A0, A1, A2 and WP Hold Time 600 ns SDA vs SCL Timing tHIGH tF SCL tLOW tR tSU:DAT tSU:STA tHD:DAT tHD:STA SDA (INPUT TIMING) tSU:STO tAA tDH tBUF SDA (OUTPUT TIMING) WP, A0, A1, and A2 Pin Timing STOP START SCL Clk 1 SDA IN tSU:WP tHD:WP WP, A0, A1, or A2 Increment/Decrement Timing SYMBOL tCI PARAMETER MIN TYP (Note 6) MAX UNITS CS to SCL Setup 600 ns tID (Note 7) SCL HIGH to U/D, DS0 or DS1 Change 600 ns tDI (Note 7) U/D, DS0 or DS1 to SCL Setup 600 ns tIL SCL LOW Period 2.5 µs tIH SCL HIGH Period 2.5 µs tIC SCL Inactive to CS Inactive (Nonvolatile Store Setup Time) 1 µs CS Deselect Time (Store) 10 ms CS Deselect Time (No Store) 1 µs tCPHS tCPHNS (Note 7) tIW (Note 7) tCYC SCL to RW Change SCL Cycle Time tR, tF (Note 7) SCL Input Rise and Fall Time FN8167 Rev 3.1 Jul 1, 2021 100 500 5 µs µs 500 µs Page 6 of 19 X9252 Increment/Decrement Timing CS tCYC tCI tIL tIH tCPHNS tCPHS tIC 90% 90% 10% SCL tID tDI tF tR U/D DS0, DS1 tIW MI RW (3) High-Voltage Write Cycle Timing SYMBOL tWC (Notes 7, 10) PARAMETER Non-Volatile Write Cycle Time TYP MAX UNITS 5 10 ms XDCP Timing SYMBOL PARAMETER MIN MAX UNITS tWRL (Note 7) SCL Rising Edge To Wiper Code Changed, Wiper Response Time After Instruction Issued (All Load Instructions) 5 20 µs NOTES: 3. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = [V(RW(n)(actual))-V(RW(n)(expected))]/MI V(RW(n)(expected)) = n(V(RH)-V(RL))/255 + V(RL), with n from 0 to 255. 4. Relative linearity is a measure of the error in step size between taps = [V(RW(n+1))-(V(RW(n)) + MI)]/MI, with n from 0 to 254 5. 1 Ml = Minimum Increment = [V(RH)-V(RL)]/255. 6. Typical values are for TA = +25°C and nominal supply voltage. 7. This parameter is not 100% tested. 8. Ratiometric temperature coefficient = (V(RW)T1(n)-V(RW)T2(n))/[V(RW)T1(n)(T1-T2)] x 106, with T1 and T2 being 2 temperatures, and n from 0 to 255. 9. Measured with wiper at tap position 255, RL grounded, using test circuit. 10. tWC is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. It is the time from a valid STOP condition at the end of a write sequence of a 2-wire interface write operation, or from the rising edge of CS of a valid “Store” operation of the Up/Down interface, to the end of the self-timed internal nonvolatile write cycle. 11. The recommended power up sequence is to apply VCC/VSS first, then the potentiometer voltages. During power-up, the data sheet parameters for the DCP do not fully apply until tD after VCC reaches its final value. In order to prevent unwanted tap position changes, or an inadvertant store, bring the CS pin high before or concurrently with the VCC pin on power-up. 12. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. FN8167 Rev 3.1 Jul 1, 2021 Page 7 of 19 X9252 Test Circuit Equivalent Circuit RTOTAL TEST POINT RL RH CW CH RW CL FORCE CURRENT RW Principles of Operation The X9252 is an integrated circuit incorporating four resistor arrays, their associated registers and counters, and the serial interface logic providing direct communication between the host and the digitally controlled potentiometers. This section provides detail description of the following: - Resistor Array - Up/Down Interface - 2-wire Interface Resistor Array Description The X9252 is comprised of four resistor arrays. Each array contains 255 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (RHi and RLi inputs) (see Figure 1). At both ends of each array and between each resistor segment is a switch connected to the wiper (RWi) pin. Within each individual array only one switch may be turned on at a time. These switches are controlled by a Wiper Counter Register (WCR). The 8 bits of the WCR (WCR[7:0]) are decoded to select and enable one of 256 switches (see Table 1). Note that each wiper has a dedicated WCR. When all bits of a WCR are zeroes, the switch closest to the corresponding RL pin is selected. When all bits of a WCR are ones, the switch closest to the corresponding RH pin is selected. The WCR is volatile and may be written directly. There are four non-volatile Data Registers (DR) associated with each WCR. Each DR can be loaded into WCR. All DRs and WCRs can be read or written. Power-Up and Down Requirements During power-up, CS must be high, to avoid inadvertant “store” operations. At power-up, the contents of Data Registers DR00, DR10, DR20, and DR30, are loaded into the corresponding wiper counter register. i = 0, 1, 2, AND 3 FOUR NON-VOLATILE DATA REGISTERS DRi0, DRi1, DRi2, and DRi3 VOLATILE 8-BIT WIPER COUNTER REGISTER WCRi WCR[7:0] = FF hex 255 RHi 254 253 252 ONE OF 256 DECODER WP SCL SDA A2, A1, A0 CS INTERFACE CONTROL AND VOLATILE STATUS REGISTER (SR) 2 (SHARED BY THE FOUR DCPs) 1 U/D DS1, DS0 WCR[7:0] = 00 hex 0 RLi RWi FIGURE 2. DETAILED BLOCK DIAGRAM OF ONE DCP FN8167 Rev 3.1 Jul 1, 2021 Page 8 of 19 X9252 Up/Down Interface Operation Mode Selection for Up/Down Control The SCL, U/D, CS, DS0 and DS1 inputs control the movement of the wiper along the resistor array. With CS set LOW the device is selected and enabled to respond to the U/D and SCL inputs. HIGH-to-LOW transitions on SCL will increment or decrement (depending on the state of the U/D input) a wiper counter register selected by DS0 and DS1. The output of this counter is decoded to select one of 256 wiper positions along the resistor array. The value of the counter is stored in nonvolatile Data Registers DRi0 whenever CS transitions HIGH while the SCL and WP inputs are HIGH. “i” indicates the DCP number selected with pins DS1 and DS0. During a “Store” operation bits DRSel1 and DRSel0 in the Status Register must be both “0”, which is their power up default value. Other combinations are reserved and must not be used. The system may select the X9252, move the wiper, and deselect the device without having to store the latest wiper position in nonvolatile memory. After the wiper movement is performed as described above and once the new position is reached, the system must keep SCL LOW while taking CS HIGH. The new wiper position will be maintained until changed by the system or until a power-down/up cycle recalled the previously stored data. This procedure allows the system to always power-up to a preset value stored in nonvolatile memory; then during system operation minor adjustments could be made. The adjustments might be based on user preference, system parameter changes due to temperature drift, etc. The state of U/D may be changed while CS remains LOW. This allows the host system to enable the device and then move the wiper up and down until the proper trim is attained. The 2-wire interface is disabled while CS remains LOW. CS SCL U/D MODE L H Wiper Up L L Wiper Down H X Store Wiper Position to nonvolatile memory if WP pin is high. No store, return to standby, if WP pin is low. X X Standby L X No Store, Return to Standby L H Wiper Up (not recommended) L L Wiper Down (not recommended) H 2-Wire Serial Interface Protocol Overview The device supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is called the master and the device being controlled is called the slave. The master always initiates data transfers, and provides the clock for both transmit and receive operations. The X9252 operates as a slave in all applications. All 2-wire interface operations must begin with a START, followed by a Slave Address byte. The Slave Address selects the X9252, and specifies if a Read or Write operation is to be performed. All Communication over the 2-wire interface is conducted by sending the MSB of each byte of data first. Serial Clock and Data DS1 DS0 SELECTED DCP 0 0 DCP0 0 1 DCP1 Data states on the SDA line can change only while SCL is LOW. The SDA state changes while SCL is HIGH are reserved for indicating START and STOP conditions (see Figure 3). On power-up of the X9252, the SDA pin is in the input mode. 1 0 DCP2 Serial Start Condition 1 1 DCP3 All commands are preceded by the START condition, which is a HIGH-to-LOW transition of SDA while SCL is HIGH. The device continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition has been met (see Figure 3). TABLE 1. DCP SELECTION FOR UP/DOWN CONTROL Serial Stop Condition All communications must be terminated by a STOP condition, which is a LOW-to-HIGH transition of SDA while SCL is HIGH. The STOP condition is also used to place the device into the Standby power mode after a read sequence. A STOP condition can only be issued after the transmitting device has released the bus (see Figure 3). FN8167 Rev 3.1 Jul 1, 2021 Page 9 of 19 X9252 SCL SDA START DATA STABLE DATA CHANGE DATA STABLE STOP FIGURE 3. VALID DATA CHANGES, START, AND STOP CONDITIONS SCL FROM MASTER 1 8 9 SDA OUTPUT FROM TRANSMITTER SDA OUTPUT FROM RECEIVER START ACK FIGURE 4. ACKNOWLEDGE RESPONSE FROM RECEIVER Serial Acknowledge Slave Address Byte An ACK (Acknowledge), is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data (see Figure 4). Following a START condition, the master must output a Slave Address Byte (Figure 5). This byte includes three parts: The device responds with an ACK after recognition of a START condition followed by a valid Slave Address byte. A valid Slave Address byte must contain the Device Type Identifier 0101, and the Device Address bits matching the logic state of pins A2, A1, and A0 (see Figure 5). If a write operation is selected, the device responds with an ACK after the receipt of each subsequent eight-bit word. In the read mode, the device transmits eight bits of data, releases the SDA line, and then monitors the line for an ACK. The device continues transmitting data if an ACK is detected. The device terminates further data transmissions if an ACK is not detected. The master must then issue a STOP condition to place the device into a known state. - The four MSBs (SA7-SA4) are the Device Type Identifier, which must always be set to 0101 in order to select the X9252. - The next three bits (SA3-SA1) are the Device Address bits (AS2-AS0). To access any part of the X9252’s memory, the value of bits AS2, AS1, and AS0 must correspond to the logic levels at pins A2, A1, and A0 respectively. - The LSB (SA0) is the R/W bit. This bit defines the operation to be performed on the device being addressed. When the R/W bit is “1”, then a Read operation is selected. A “0” selects a Write operation. SA7 0 SA6 SA5 SA4 SA3 SA2 SA1 1 0 1 AS2 AS1 AS0 Device Type Identifier SLAVE ADDRESS BIT(S) Device Address R/W Read or Write DESCRIPTION SA7-SA4 Device Type Identifier SA3-SA1 Device Address SA0 SA0 Read or Write Operation Select FIGURE 5. SLAVE ADDRESS (SA) FORMAT FN8167 Rev 3.1 Jul 1, 2021 Page 10 of 19 X9252 Nonvolatile Write Acknowledge Polling After a nonvolatile write command sequence is correctly issued (including the final STOP condition), the X9252 initiates an internal high voltage write cycle. This cycle typically requires 5ms. During this time, any Read or Write command is ignored by the X9252. Write Acknowledge Polling is used to determine whether a high voltage write cycle is completed. During acknowledge polling, the master first issues a START condition followed by a Slave Address Byte. The Slave Address Byte contains the X9252’s Device Type Identifier and Device Address. The LSB of the Slave Address (R/W) can be set to either 1 or 0 in this case. If the device is busy within the high voltage cycle, then no ACK is returned. If the high voltage cycle is completed, an ACK is returned and the master can then proceed with a new Read or Write operation (see Figure 6). BYTE LOAD COMPLETED BY ISSUING STOP. ENTER ACK POLLING ISSUE START ISSUE SLAVE ADDRESS BYTE (READ OR WRITE) ACK RETURNED? ISSUE STOP HIGH VOLTAGE NO NO SEQUENCE. YES X9252 Digital Potentiometer Register Organization Refer to the “Functional Diagram” on page 1. There are four Digitally Controlled Potentiometers, referred to as DCPi, i = 0, 1, 2, 3. Each potentiometer has one volatile Wiper Control Register (WCR) with the corresponding number, WCRi, i = 0, 1, 2, 3. Each potentiometer also has four nonvolatile registers to store wiper position or general data, these are numbered DRi0, DRi1, DRi2 and DRi3, i = 0, 1, 2, 3. The registers are organized in five pages of four, with one page consisting of the WCRi (i = 0 to 3), a second page containing the DRi0 (i = 0 to 3), a third page containing the DRi1, and so forth. These pages can be written to four bytes at time. In this manner all four potentiometer WCRs can be updated in a single serial write (see “Page Write Operation” on page 14), as well as all four registers of a given page in the DR array. The unique feature of the X9252 device is that writing or reading to a Data Register of a given DCP automatically updates/moves the WCR of that DCP with the content of the DR. In this manner data can be moved from a particular DCP register to that DCP’s WCR just by performing a 2-wire read operation. Simultaneously, that data byte can be utilized by the host. Status Register Organization The Status Register (SR) is used in read and write operations to select the appropriate DCP register. Before any DCP register can be accessed, the SR must be set to the correct value. It is accessed by setting the Address Byte to 07h (see Table 3). Do this by Writing the Slave Address followed by a Byte Address of 07h. The SR is volatile and defaults to 00h on power-up. It is an 8-bit register containing three control bits in the 3 LSBs as follows: YES COMPLETE. CONTINUE COMMAND 2-Wire Serial Interface Operation 7 6 5 Reserved ISSUE STOP CONTINUE NORMAL READ OR WRITE COMMAND SEQUENCE PROCEED 4 3 2 1 0 DRSel1 DRSel0 NVEnable Bits DRSel1 and DRSel0 determine which Data Register of a DCP is selected for a given operation. NVEnable is used to select the volatile WCR if “0”, and one of the nonvolatile DCP registers if “1”. Table 2 shows this register organization. “Store” operations using the Up/Down interface require that bits DRSel1 and DRSel0 are set to “0”. FIGURE 6. ACKNOWLEDGE POLLING SEQUENCE FN8167 Rev 3.1 Jul 1, 2021 Page 11 of 19 X9252 TABLE 2. REGISTER NUMBERING STATUS REG (Note 13) (Addr: 07H) REGISTERED SELECTED (Note 14) RESERVED BITS 7-3 DRSel1 BIT-2 DRSel0 BIT-1 NVEnable BIT-0 DCP0 DCP1 DCP2 DCP3 (ADDR: 00h) (ADDR: 01h) (ADDR: 02h) (ADDR: 03h) Reserved X X 0 WCR0 WCR1 WCR2 WCR3 0 0 1 DR00 DR10 DR20 DR30 0 1 1 DR01 DR11 DR21 DR31 1 0 1 DR02 DR12 DR22 DR32 1 1 1 DR03 DR13 DR23 DR33 To read or write the contents of a single Data Register or Wiper Register: 13. Load the status register (using a write command) to select the row (see Figure 7) Writing a 1, 3, 5, or 7 to the Status Register specifies that the subsequent read or write command will access a Data Register. This status register operation also initiates a transfer of the contents of the selected data register to its associated WCR for all DCPs. So, for example, writing ‘03h’ to the status register causes the value in DR01 to move to WCR0, DR11 to move to WCR1, DR21 to move to WCR2, and DR31 to move to WCR3. Writing a 0 to bit ‘0’ of the status register specifies that the subsequent read or write command will access a wiper counter register. Each WCR can be written to individually, without affecting the contents of any other. 14. Access the desired DR or WCR using a new write or read command (see Figure 8 for write and Figure 10 for read.) Specify the desired column (DCP number) by sending the DCP address as part of this read or write command. If Bit-0 of data byte = 1, DR contents move to WCR during this ACK period SIGNALS FROM THE MASTER S T A R T SIGNAL AT SDA 0 1 0 1 SIGNALS FROM THE SLAVE STATUS REGISTER ADDRESS SLAVE ADDRESS 0 0 0 0 0 0 1 1 1 A C K S T O P DR SELECT DATA 0 0 0 0 0 x x 1 A C K A C K FIGURE 7. STATUS REGISTER WRITE (USES STANDARD BYTE WRITE SEQUENCE TO SET UP ACCESS TO A DATA REGISTER) FN8167 Rev 3.1 Jul 1, 2021 Page 12 of 19 X9252 DCP Addressing for 2-Wire Interface The SR bits and WP pin determine the register being accessed through the 2-wire interface (see Table 2). Once the register number has been selected by a 2-wire instruction, then the DCP number is determined by the Address Byte of the following instruction. Note again that this enables a complete page write of the DRs of all four potentiometers at once. The register addresses accessible in the X9252 include: As noted before, any write operation to a Data Register (DR), also transfers the contents of all the data registers in that row to their corresponding WCR. For example, to write 3Ahex to the Data Register 1 of DCP2 the following sequence is required: TABLE 3. 2-WIRE INTERFACE ADDRESS BYTE ADDRESS (HEX) CONTENTS 0 DCP 0 1 DCP 1 2 DCP 2 3 DCP 3 4 Not Used 5 Not Used 6 Not Used 7 Status Register START Slave Address ACK Address Byte ACK Data Byte ACK 0101 0000 (Hardware Address = 000, and a Write Command) 0000 0111 (Indicates Status Register Address) 0000 0011 (Data Register 1 and NVEnable Selected) Note: at this ACK, the WCRs are all updated with their respective DR. STOP START Slave Address ACK Address Byte ACK Data Byte ACK STOP All other address bits in the Address Byte must be set to “0” during 2-wire write operations and their value should be ignored when read. Byte Write Operation For any Byte Write operation, the X9252 requires the Slave Address byte, an Address Byte, and a Data Byte (see Figure 8). After each of them, the X9252 responds with an ACK. The master then terminates the transfer by generating a STOP condition. At this time, if the write operation is to a volatile register (WCR, or SR), the X9252 is ready for the next read or write operation. If the write operation is to a nonvolatile register (DR), and the WP pin is high, the X9252 begins the internal write cycle to the nonvolatile memory. During the internal nonvolatile write cycle, the X9252 does not respond to any requests from the master. The SDA output is at high impedance. 0101 0000 (Hardware Address = 000, Write Command) 0000 0010 (Access DCP2) 0011 1010 (Write Data Byte 3Ah) During the sequence of this example, WP pin must be high, and A0, A1, and A2 pins must be low. When completed, the DR21 register and the WCR2 will be set to 3Ah and the other Data Register in Row 1 will transfer their other contents to the respective WCR’s WRITE SIGNALS FROM THE MASTER SIGNAL AT SDA SIGNALS FROM THE SLAVE S T A R T 0 1 0 1 S T O P DATA BYTE ADDRESS BYTE SLAVE ADDRESS 0 A C K A C K A C K FIGURE 8. BYTE WRITE SEQUENCE FN8167 Rev 3.1 Jul 1, 2021 Page 13 of 19 X9252 Page Write Operation As stated previously, the memory is organized as a single Status Register (SR), and four pages of four registers each. Each page contains one Data Register for each DCP. The order of the bytes within a page is DR0i, followed by DR1i, followed by DR2i, and then DR3i, with i being the Data Register number (0, 1, 2, or 3). Normally a page write operation will be used to efficiently update all four data registers and WCR in a single write command, starting at DCP0 and finishing with DCP3. In order to perform a Page Write operation to the memory array, the NVEnable bit in the SR must first be set to “1”. A Page Write operation is initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the first data byte is transferred, the master can transmit up to 4 bytes (see Figure 9). After the receipt of each byte, the X9252 responds with an ACK, and the internal DCP address counter is incremented by one. The page address remains constant. When the counter reaches the end of the page (DR3i, 03hex), it “rolls over” and goes back to the first byte of the same page (DR0i, 00hex). For example, if the master writes 3 bytes to a page starting at location DR22, the first 2 bytes are written to locations DR22 and DR32, while the last byte is written to locations DR02. Afterwards, the DCP counter would point to location DR12. If the master supplies more than 4 bytes of data, then new data overwrites the previous data, one byte at a time. The master terminates the loading of Data Bytes by issuing a STOP condition, which initiates the nonvolatile write cycle. As with the Byte Write operation, all inputs are disabled until completion of the internal write cycle. If the WP pin is low, the nonvolatile write cycle doesn’t start and the bytes are discarded. Notice that the Data Bytes are also written to the WCR of the corresponding DCPs, therefore in the above example, WCR2, WCR3, and WCR0 are also written and WCR1 is updated with the contents of DR12. WRITE SIGNALS FROM THE MASTER S T A R T 2 R2 FIGURE 19. INVERTING AMPLIFIER FIGURE 20. EQUIVALENT L-R CIRCUIT C R2 - R1 - + } RA + } RB FREQUENCY R1, R2, C AMPLITUDE  RA, RB FIGURE 21. FUNCTION GENERATOR FN8167 Rev 3.1 Jul 1, 2021 Page 17 of 19 X9252 Application Circuits (Continued) mR nR pR } } VUL } V+ VS + VO VS VR V+ + VO + + - VLL FIGURE 23. SHUNT LIMITER FIGURE 22. WINDOW COMPARATOR pR } } mR nR } C VO + + FIGURE 24. FUNCTION GENERATOR REVISION DATE 3.1 Jul 1, 2021 FN8167 Rev 3.1 Jul 1, 2021 DESCRIPTION Updated external links throughout. Updated the ordering information table format. Added Latch-Up Robustness in the Abs Max section. Added Revision History section. Page 18 of 19 X9252 Package Outline Drawing For the most recent package outline drawing, see M24.173. M24.173 24 Lead Thin Shrink Small Outline Package (TSSOP) Rev 1, 5/10 A 1 3 7.80 ±0.10 SEE DETAIL "X" 13 24 6.40 PIN #1 I.D. MARK 4.40 ±0.10 2 3 0.20 C B A 1 12 0.15 +0.05 -0.06 B 0.65 TOP VIEW END VIEW 1.00 REF H - 0.05 C 0.90 +0.15 -0.10 1.20 MAX GAUGE PLANE SEATING PLANE 0.25 +0.05 -0.06 0.10 M C B A 0.10 C 5 0°-8° 0.05 MIN 0.15 MAX SIDE VIEW 0.25 0.60± 0.15 DETAIL "X" (1.45) NOTES: 1. Dimension does not include mold flash, protrusions or gate burrs. (5.65) Mold flash, protrusions or gate burrs shall not exceed 0.15 per side. 2. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25 per side. 3. Dimensions are measured at datum plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Dimension does not include dambar protrusion. Allowable protrusion shall be 0.08mm total in excess of dimension at maximum material condition. Minimum space between protrusion and adjacent lead (0.65 TYP) (0.35 TYP) TYPICAL RECOMMENDED LAND PATTERN is 0.07mm. 6. Dimension in ( ) are for reference only. 7. Conforms to JEDEC MO-153. FN8167 Rev 3.1 Jul 1, 2021 Page 19 of 19 IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. 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