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X9258UV24IZ

X9258UV24IZ

  • 厂商:

    RENESAS(瑞萨)

  • 封装:

    TSSOP24

  • 描述:

    IC DGT POT 50KOHM 256TAP 24TSSOP

  • 数据手册
  • 价格&库存
X9258UV24IZ 数据手册
DATASHEET X9258 FN8168 Rev 6.00 December 15, 2011 Low Noise/Low Power/2-Wire Bus/256 Taps Quad Digital Controlled Potentiometers (XDCP™) The X9258 integrates 4 digitally controlled potentiometers (XDCP™) on a monolithic CMOS integrated circuit. Features • Four potentiometers in one package The digitally controlled potentiometer is implemented using 255 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the 2-wire bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and 4 non-volatile Data Registers (DR0:DR3) that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array though the switches. Power-up recalls the contents of DR0 to the WCR. • 256 resistor taps/potentiometer................. 0.4% resolution • 2-wire serial interface • Wiper resistance, 40Ωtypical @ V+ = 5V, V- = -5V • Four nonvolatile data registers for each potentiometer • Nonvolatile storage of wiper position • Standby current > R2 FIGURE 18. EQUIVALENT L-R CIRCUIT FIGURE 17. INVERTING AMPLIFIER C R2 – R1 – + + } RA } RB FREQUENCY  R1, R2, C AMPLITUDE  RA, RB FIGURE 19. FUNCTION GENERATOR FN8168 Rev 6.00 December 15, 2011 Page 17 of 19 X9258 X9258 Thin Shrink Small Outline Package Family (TSSOP) MDP0044 0.25 M C A B D THIN SHRINK SMALL OUTLINE PACKAGE FAMILY A MILLIMETERS (N/2)+1 N SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE PIN #1 I.D. E E1 1 (N/2) B 0.20 C B A 2X N/2 LEAD TIPS TOP VIEW 0.05 e C SEATING PLANE H A 1.20 1.20 1.20 1.20 1.20 Max A1 0.10 0.10 0.10 0.10 0.10 ±0.05 A2 0.90 0.90 0.90 0.90 0.90 ±0.05 b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06 c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06 D 5.00 5.00 6.50 7.80 9.70 ±0.10 E 6.40 6.40 6.40 6.40 6.40 Basic E1 4.40 4.40 4.40 4.40 4.40 ±0.10 e 0.65 0.65 0.65 0.65 0.65 Basic L 0.60 0.60 0.60 0.60 0.60 ±0.15 L1 1.00 1.00 1.00 1.00 1.00 Reference Rev. F 2/07 0.10 M C A B b 0.10 C N LEADS SIDE VIEW NOTES: 1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm per side. SEE DETAIL “X” 3. Dimensions “D” and “E1” are measured at dAtum Plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. c END VIEW L1 A A2 GAUGE PLANE 0.25 L A1 0° - 8° DETAIL X © Copyright Intersil Americas LLC 2005-2011. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8168 Rev 6.00 December 15, 2011 Page 18 of 19 X9258 X9258 Package Outline Drawing M24.3 24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE (SOIC) Rev 2, 3/11 24 INDEX AREA 7.60 (0.299) 7.40 (0.291) 10.65 (0.419) 10.00 (0.394) DETAIL "A" 1 2 3 TOP VIEW 1.27 (0.050) 0.40 (0.016) SEATING PLANE 2.65 (0.104) 2.35 (0.093) 15.60 (0.614) 15.20 (0.598) 0.75 (0.029) x 45° 0.25 (0.010) 0.30 (0.012) 0.10 (0.004) 1.27 (0.050) 0.51 (0.020) 0.33 (0.013) 8° 0° 0.32 (0.012) 0.23 (0.009) SIDE VIEW “B” SIDE VIEW “A” 1.981 (0.078) 9.373 (0.369) 1.27 (0.050) NOTES: 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. Package length does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 3. Package width does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 5. Terminal numbers are shown for reference only. 6. The lead width as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 7. Controlling dimension: MILLIMETER. Converted inch dimensions in ( ) are not necessarily exact. 8. This outline conforms to JEDEC publication MS-013-AD ISSUE C. 0.533 (0.021) TYPICAL RECOMMENDED LAND PATTERN FN8168 Rev 6.00 December 15, 2011 Page 19 of 19
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