X9259TS24I-2.7

APPLICATION NOTES AND DEVELOPMENT SYSTEM A V A I L A B L E AN99 • AN115 • AN124 •AN133 • AN134 • AN135 Single Supply / Low Power / 256-tap / 2-Wire bus X9259 Quad Digitally-Controlled (XDCPTM) Potentiometers FEATURES DESCRIPTION • Four separate potentiometers in one package • 256 resistor taps–0.4% resolution • 2-Wire Serial Interface for write, read, and transfer operations of the potentiometer • Wiper Resistance: 100Ω typical @ VCC = 5V • 4 Non-volatile Data Registers for Each Potentiometer • Non-volatile Storage of Multiple Wiper Positions • Standby Current < 5µA Max • VCC: 2.7V to 5.5V Operation • 50KΩ, 100KΩ versions of Total Resistance • Endurance: 100,000 Data Changes per Bit per Register • 100 yr. Data Retention • Single Supply Version of X9258 • 24-Lead SOIC, 24-Lead TSSOP, 24-Lead CSP (Chip Scale Package) • Low Power CMOS The X9259 integrates four digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated circuit. The digitally controlled potentiometers are implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the 2-wire bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and four non-volatile Data Registers that can be directly written to and read by the user. The content of the WCR controls the position of the wiper. At power-up, the device recalls the content of the default Data Registers of each DCP (DR00, DR10, DR20, and DR30) to the corresponding WCR. The XDCP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. FUNCTIONAL DIAGRAM A3 A2 2-Wire Interface A1 A0 RH1 RH0 VCC WCR0 DR00 DR01 DR02 DR03 POWER UP, INTERFACE CONTROL AND STATUS DCP0 WCR1 DR10 DR11 DR12 DR13 DCP1 RH3 RH2 WCR2 DR20 DR21 DR22 DR23 DCP2 WCR3 DR30 DR31 DR32 DR33 DCP3 SDA SCL VSS REV 1.5 4/13/04 WP RW0 RL0 www.xicor.com RW1 RL1 RW2 RL2 RW3 Characteristics subject to change without notice. RL3 1 of 25 X9259 ORDERING INFO Package Operating Temperature Range VCC Limits 50kΩ 24-lead SOIC 0°C to 70°C 5V±10% X9259US24-2.7 50kΩ 24-lead SOIC 0°C to 70°C 2.7 to 5.5V Ordering Number Potentiomenter Organization X9259US24 X9259US24I 50kΩ 24-lead SOIC -40°C to +85°C 5V±10% X9259US24I-2.7 50kΩ 24-lead SOIC -40°C to +85°C 2.7 to 5.5V X9259UV24 50kΩ 24-lead TSSOP 0°C to 70°C 5V±10% X9259UV24-2.7 50kΩ 24-lead TSSOP 0°C to 70°C 2.7 to 5.5V X9259UV24I 50kΩ 24-lead TSSOP -40°C to +85°C 5V±10% X9259UV24I-2.7 50kΩ 24-lead TSSOP -40°C to +85°C 2.7 to 5.5V X9259UB24 50kΩ 24-lead CSP 0°C to 70°C 5V±10% X9259UB24-2.7 50kΩ 24-lead CSP 0°C to 70°C 2.7 to 5.5V X9259UB24I 50kΩ 24-lead CSP -40°C to +85°C 5V±10% X9259UB24I-2.7 50kΩ 24-lead CSP -40°C to +85°C 2.7 to 5.5V X9259TS24 100kΩ 24-lead SOIC 0°C to 70°C 5V±10% X9259TS24-2.7 100kΩ 24-lead SOIC 0°C to 70°C 2.7 to 5.5V X9259TS24I 100kΩ 24-lead SOIC -40°C to +85°C 5V±10% X9259TS24I-2.7 100kΩ 24-lead SOIC -40°C to +85°C 2.7 to 5.5V X9259TV24 100kΩ 24-lead TSSOP 0°C to 70°C 5V±10% X9259TV24-2.7 100kΩ 24-lead TSSOP 0°C to 70°C 2.7 to 5.5V X9259TV24I 100kΩ 24-lead TSSOP -40°C to +85°C 5V±10% X9259TV24I-2.7 100kΩ 24-lead TSSOP -40°C to +85°C 2.7 to 5.5V X9259TB24 100kΩ 24-lead CSP 0°C to 70°C 5V±10% X9259TB24-2.7 100kΩ 24-lead CSP 0°C to 70°C 2.7 to 5.5V X9259TB24I 100kΩ 24-lead CSP -40°C to +85°C 5V±10% X9259TB24I-2.7 100kΩ 24-lead CSP -40°C to +85°C 2.7 to 5.5V REV 1.5 4/13/04 www.xicor.com Characteristics subject to change without notice. 2 of 25 X9259 CIRCUIT LEVEL APPLICATIONS SYSTEM LEVEL APPLICATIONS • Vary the gain of a voltage amplifier • Adjust the contrast in LCD displays • Provide programmable dc reference voltages for comparators and detectors • Control the power level of LED transmitters in communication systems • Control the volume in audio circuits • Set and regulate the DC biasing point in an RF power amplifier in wireless systems • Trim out the offset voltage error in a voltage amplifier circuit • Set the output voltage of a voltage regulator • Trim the resistance in Wheatstone bridge circuits • Control the gain, characteristic frequency and Q-factor in filter circuits • Set the scale factor and zero point in sensor signal conditioning circuits • Vary the frequency and duty cycle of timer ICs • Vary the dc biasing of a pin diode attenuator in RF circuits • Control the gain in audio and home entertainment systems • Provide the variable DC bias for tuners in RF wireless systems • Set the operating points in temperature control systems • Control the operating point for sensors in industrial systems • Trim offset and gain errors in artificial intelligent systems • Provide a control variable (I, V, or R) in feedback circuits REV 1.5 4/13/04 www.xicor.com Characteristics subject to change without notice. 3 of 25 X9259 PIN CONFIGURATION SOIC/TSSOP CSP 1 DNC 1 24 A3 A0 RW3 2 23 SCL 3 22 RL2 RH3 4 21 RH2 RL3 5 20 RW2 NC 6 19 NC 18 VSS VCC 7 X9259 RL0 8 17 RW1 RH0 9 16 RH1 RW0 10 15 RL1 A2 11 14 A1 WP 12 13 SDA A 2 3 4 RW0 A2 A1 RL1 RL0 WP SDA RW1 VCC RH0 RH1 VSS NC RH3 RH2 NC RL3 DNC A3 RW2 RW3 A0 SCL RL2 B C D E F Top View–Bumps Down PIN ASSIGNMENTS Pin Pin (SOIC/TSSOP) (CSP) Symbol Function 2 F2 A0 3 F1 RW3 Device Address for 2-Wire bus. (See Note 1) Wiper Terminal of DCP3 4 D2 RH3 High Terminal of DCP3 5 E1 RL3 Low Terminal of DCP3 6 E2 NC1 Must be left unconnected 7 C1 VCC System Supply Voltage 8 B1 RL0 Low Terminal of DCP0 9 C2 RH0 High Terminal of DCP0 10 A1 RW0 Wiper Terminal of DCP0 11 A2 A2 Device Address for 2-Wire bus. (See Note 1) 12 B2 WP Hardware Write Protect – Active Low 13 B3 SDA Serial Data Input/Output for 2-Wire bus. 14 A3 A1 Device Address for 2-Wire bus. (See Note 1) 15 A4 RL1 Low Terminal of DCP1 16 C3 RH1 High Terminal of DCP1 17 B4 RW1 Wiper Terminal of DCP1 18 C4 VSS System Ground 20 E4 RW2 WiperTerminal of DCP2 21 D3 RH2 High Terminal of DCP2 22 F4 RL2 Low Terminal of DCP2 23 F3 SCL Serial Clock for 2-Wire bus. 24 E3 A3 Device Address for 2-Wire bus. (See Note 1) 6, 19 D1, D4 NC No Connect 1 E2 DNC Do Not Connect Note 1: A0-A3 Device address pins must be tied to a logic level. REV 1.5 4/13/04 www.xicor.com Characteristics subject to change without notice. 4 of 25 X9259 PIN DESCRIPTIONS Potentiometer Pins Bus Interface Pins RH, RL SERIAL DATA INPUT/OUTPUT (SDA) The SDA is a bidirectional serial data input/output pin for a 2-Wire slave device and is used to transfer data into and out of the device. It receives device address, opcode, wiper register address and data sent from a 2-Wire master at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock SCL. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. The RH and RL pins are equivalent to the terminal connections on a mechanical potentiometer. Since there are 4 potentiometers, there are 4 sets of RH and RL such that RH0 and RL0 are the terminals of DCP0 and so on. RW The wiper pin are equivalent to the wiper terminal of a mechanical potentiometer. Since there are 4 potentiometers, there are 4 sets of RW such that RW0 is the terminal of DCP0 and so on. Bias Supply Pins SERIAL CLOCK (SCL) This input is used by 2-Wire master to supply 2-Wire serial clock to the X9259. SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY GROUND (VSS) The VCC pin is the system supply voltage. The VSS pin is the system ground. DEVICE ADDRESS (A3–A0) The Address inputs are used to set the least significant 4 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the Address input in order to initiate communication with the X9259. A maximum of 16 devices may occupy the 2-Wire serial bus. Device pins A3-A0 must be tie to a logic level which specify the external address of the device, see Figures 3, 4, and 5. REV 1.5 4/13/04 Other Pins NO CONNECT No connect pins should be left open. This pins are used for Xicor manufacturing and testing purposes. HARDWARE WRITE PROTECT INPUT (WP) The WP pin when LOW prevents non-volatile writes to the Data Registers. www.xicor.com Characteristics subject to change without notice. 5 of 25 X9259 PRINCIPLES OF OPERATION The X9259 is an integrated circuit incorporating four DCPs and their associated registers and counters, and the serial interface providing direct communication between a host and the potentiometers. DCP Description Each DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of each DCP are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL pins). The RW pin is an intermediate node, equivalent to the wiper terminal of a mechanical potentiometer. Power Up and Down Recommendations. There are no restrictions on the power-up or powerdown conditions of VCC and the voltages applied to the potentiometer pins provided that VCC is always more positive than or equal to VH, VL, and VW, i.e., VCC ≥ VH, VL, VW. The VCC ramp rate specification is always in effect. The position of the wiper terminal within the DCP is controlled by an 8-bit volatile Wiper Counter Register (WCR). Figure 1. Detailed Potentiometer Block Diagram One of Four Potentiometers RH #: 0, 1, 2, or 3 SERIAL BUS INPUT SERIAL DATA PATH FROM INTERFACE CIRCUITRY DR#0 DR#1 8 DR#2 IF WCR = 00[H] then RW is closest to RL IF WCR = FF[H] then RW is closest to RH 8 WIPER COUNTER REGISTER (WCR#) DR#3 COUNTER --DECODE DCP CORE RW INC/DEC LOGIC UP/DN MODIFIED SCK REV 1.5 4/13/04 PARALLEL BUS INPUT www.xicor.com UP/DN CLK RL Characteristics subject to change without notice. 6 of 25 X9259 Wiper Counter Register (WCR) The X9259 contains four Wiper Counter Registers, one for each potentiometer. The Wiper Counter Register can be envisioned as a 8-bit parallel and serial load counter with its outputs decoded to select one of 256 wiper positions along its resistor array. The contents of the WCR can be altered in four ways: it may be written directly by the host via the Write Wiper Counter Register instruction (serial load); it may be written indirectly by transferring the contents of one of four associated data registers via the XFR Data Register instruction (parallel load); it can be modified one step at a time by the Increment/Decrement instruction (see Instruction section for more details). Finally, it is loaded with the contents of its data register zero (DR#0) upon power-up. (See Figure 1.) Data Registers (DR) Each of the four DCPs has four 8-bit non-volatile Data Registers. These can be read or written directly by the host. Data can also be transferred between any of the four data registers and the associated Wiper Counter Register. All operations changing data in one of the data registers is a non-volatile operation and takes a maximum of 10ms. If the application does not require storage of multiple settings for the potentiometer, the Data Registers can be used as regular memory locations for system parameters or user preference data. Bit [7:0] are used to store one of the 256 wiper positions (0~255). The Wiper Counter Register is a volatile register; that is, its contents are lost when the X9259 is powereddown. Although the register is automatically loaded with the value in DR#0 upon power-up, this may be different from the value present at power-down. Powerup guidelines are recommended to ensure proper loadings of the DR#0 value into the WCR# (See Design Considerations Section). Table 1. Wiper counter Register, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile). WCR7 WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 (MSB) WCR0 (LSB) Table 2. Data Register, DR (8-bit), Bit [7:0]: Used to store wiper positions or data (Non-volatile). Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 (MSB) REV 1.5 4/13/04 Bit 2 Bit 1 Bit 0 (LSB) www.xicor.com Characteristics subject to change without notice. 7 of 25 X9259 SERIAL INTERFACE The X9259 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master always initiates data transfers and provide the clock for both transmit and receive operations. Therefore, the X9259 operates as a slave device in all applications. All 2-wire interface operations must begin with a START, followed by an Identification Byte, that selects the X9259. All communication over the 2-wire interface is conducted by sending the MSB of each byte of data first. Clock and Data Conventions Data states on the SDA line can change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions. See Figure 2. On power up of the X9259 the SDA pin is in the input mode. START Condition All commands to the X9259 are preceded by the start condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The X9259 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met. See Figure 2. STOP Condition All communications must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH. See Figure 2. The STOP condition REV 1.5 4/13/04 is also used to place the device into the Standby Power mode after a Read sequence. A STOP condition can only be issued after the transmitting device has released the bus. Acknowledge An ACK, Acknowledge, is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data. See Figure 3. The X9259 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again after successful receipt of an Instruction Byte. The X9259 also responds with an ACK after receiving a Data Byte after a Write Instruction. A valid Identification Byte contains the Device Type Identifier 0101, as the four MSBs, and the Device Address bits matching the logic states of pins A3, A2, A1, and A0, as the four LSBs. See Figure 4. In the Read mode, the device transmits eight bits of data, releases the SDA line, and then monitors the line for an ACK. The device continues transmitting data if an ACK is detected. The device terminates further data transmissions if an ACK is not detected. The master must then issue a STOP condition to place the device into a known state. During the internal non-volatile Write operation, the X9259 ignores the inputs at SDA and SCL, and does not issue an ACK after Identification bytes. www.xicor.com Characteristics subject to change without notice. 8 of 25 X9259 Figure 2. Valid Data Changes, Start, and Stop Conditions SCL SDA START DATA DATA DATA STABLE CHANGE STABLE STOP Figure 3. Acknowledge Response from Receiver SCL from Master 1 8 9 SDA Output from Transmitter SDA Output from Receiver START ACK Identification Byte The first byte sent to the X9259 from the host is called the Identification Byte. The most significant four bits are a Device Type Identifier, ID[3:0] bits, which must be 0101. Refer to Table 3. Data Register Selection Only the device which Slave Address matches the incoming device address sent by the master executes the instruction. The A3-A0 inputs can be actively driven by CMOS input signals or tied to VCC or VSS. INSTRUCTION BYTE (I) The next byte sent to the X9259 contains the instruction and register pointer information. The four most significant bits are used provide the instruction opcode I [3:0]. The RB and RA bits point to one of the four data registers of each associated XDCP. The least two significant bits point to one of four Wiper Counter Registers or DCPs. The format is shown in Table 4. REV 1.5 4/13/04 Register RB RA DR#0 0 0 DR#1 0 1 DR#2 1 0 DR#3 1 1 #: 0, 1, 2, or 3 The least significant four bits of the Identification Byte are the Slave Address bits, AD[3:0]. To access the X9259, these four bits must match the logic values of pins A3, A2, A1, and A0. www.xicor.com Characteristics subject to change without notice. 9 of 25 X9259 Table 3. Identification Byte Format Device Type Identifier Slave Address ID3 ID2 ID1 ID0 0 1 0 1 A3 A2 A1 A0 Logic value of pins A3, A2, A1, and A0 (MSB) (LSB) Table 4. Instruction Byte Format Instruction Opcode I3 I2 DCP Selection (WCR Selection) Register Selection I1 I0 RB RA P1 (MSB) P0 (LSB) Table 5. Instruction Set Instruction I3 I2 Instruction Set I1 I0 RB RA P1 P0 Operation Read Wiper Counter Register Write Wiper Counter Register 1 0 0 1 0 0 1/0 1/0 1 0 1 0 0 0 1/0 1/0 Read Data Register 1 0 1 1 1/0 1/0 1/0 1/0 Write Data Register 1 1 0 0 1/0 1/0 1/0 1/0 XFR Data Register to Wiper Counter Register 1 1 0 1 1/0 1/0 1/0 1/0 XFR Wiper Counter Register to Data Register 1 1 1 0 1/0 1/0 1/0 1/0 Global XFR Data Registers to Wiper Counter Registers 0 0 0 1 1/0 1/0 0 0 Global XFR Wiper Counter Registers to Data Register 1 0 0 0 1/0 1/0 0 0 Increment/Decrement Wiper Counter Register 0 0 1 0 0 0 1/0 1/0 Read the contents of the Wiper Counter Register pointed to by P1-P0 Write new value to the Wiper Counter Register pointed to by P1-P0 Read the contents of the Data Register pointed to by P1-P0 and RB-RA Write new value to the Data Register pointed to by P1-P0 and RB-RA Transfer the contents of the Data Register pointed to by P1-P0 and RB-RA to its associated Wiper Counter Register Transfer the contents of the Wiper Counter Register pointed to by P1-P0 to the Data Register pointed to by RB-RA Transfer the contents of the Data Registers pointed to by RB-RA of all four pots to their respective Wiper Counter Registers Transfer the contents of both Wiper Counter Registers to their respective data Registers pointed to by RB-RA of all four DCPs Enable Increment/decrement of the Control Latch pointed to by P1-P0 Note: 1/0 = data is one or zero REV 1.5 4/13/04 www.xicor.com Characteristics subject to change without notice. 10 of 25 X9259 Instructions Four of the nine instructions are three bytes in length. These instructions are: – Read Wiper Counter Register – read the current wiper position of the selected potentiometer, – Write Wiper Counter Register – change current wiper position of the selected potentiometer, – Read Data Register – read the contents of the selected Data Register; – Write Data Register – write a new value to the selected Data Register. The basic sequence of the three byte instructions is illustrated in Figure 5. These three-byte instructions exchange data between the WCR and one of the Data Registers. A transfer from a Data Register to a WCR is essentially a write to a static RAM, with the static RAM controlling the wiper position. The response of the wiper to this action is delayed by tWRL. A transfer from the WCR (current wiper position), to a Data Register is a write to non-volatile memory and takes a minimum of tWR to complete. The transfer can occur between one of the four potentiometer’s WCR, and one of its associated registers, DRs; or it may occur globally, where the transfer occurs between all potentiometers and one associated register. Four instructions require a two-byte sequence to complete. These instructions transfer data between the host and the X9259; either between the host and one of the data registers or directly between the host and the Wiper Counter Register. These instructions are: – XFR Data Register to Wiper Counter Register – This transfers the contents of one specified Data Register to the associated Wiper Counter Register. – XFR Wiper Counter Register to Data Register – This transfers the contents of the specified Wiper Counter Register to the specified associated Data Register. – Global XFR Data Register to Wiper Counter Register – This transfers the contents of all specified Data Registers to the associated Wiper Counter Registers. – Global XFR Wiper Counter Register to Data Register – This transfers the contents of all Wiper Counter Registers to the specified associated Data Registers. INCREMENT/DECREMENT COMMAND The final command is Increment/Decrement (Figure 6 and 7). The Increment/Decrement command is different from the other commands. Once the command is issued and the X9259 has responded with an Acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby, providing a fine tuning capability to the host. For each SCL clock pulse (tHIGH) while SDA is HIGH, the selected wiper moves one wiper position towards the RH terminal. Similarly, for each SCL clock pulse while SDA is LOW, the selected wiper moves one resistor wiper position towards the RL terminal. See Instruction format for more details. REV 1.5 4/13/04 www.xicor.com Characteristics subject to change without notice. 11 of 25 X9259 Figure 4. Two-Byte Instruction Sequence SCL SDA 0 1 0 1 S ID3 ID2 ID1 ID0 A3 A2 A1 A0 T A External R Device ID Address T A I3 C K I2 I1 I0 Instruction Opcode RB RA P1 P0 A C K Register DCP/WCR Address Address S T O P Figure 5. Three-Byte Instruction Sequence 2-Wire Interface SCL SDA 0 1 0 1 S ID3 ID2 ID1 ID0 A3 T A Device ID R T A2 A0 A I3 C K External Address I2 A1 I1 I0 Instruction Opcode RB RA P1 P0 A C K Register Pot/WCR Address Address D7 D6 D5 D4 D3 D2 D1 D0 Data for WCR[7:0] or DR[7:0] A C K S T O P Figure 6. Increment/Decrement Instruction Sequence 2-Wire Interface SCL 0 SDA S T A R T 1 0 1 ID3 ID2 ID1 ID0 A3 Device ID A2 A1 A0 External Address A C K I3 I2 I1 Instruction Opcode I0 RB RA P1 P0 A C Register Pot/WCR K Address Address I N C 1 I N C 2 I N C n D E C 1 D E C n S T O P Figure 7. Increment/Decrement Timing Spec INC/DEC CMD Issued tWRID SCL SDA RW REV 1.5 4/13/04 Voltage Out www.xicor.com Characteristics subject to change without notice. 12 of 25 X9259 INSTRUCTION FORMAT Read Wiper Counter Register (WCR) Device Type Device S Identifier Addresses T A R 0 1 0 1 A3 A2 A1 A0 T Instruction DR/WCR S Opcode Addresses A C K 1 0 0 1 0 0 P1 P0 S A C K Wiper Position (Sent by X9259 on SDA) M W W W W W W W W A C C C C C C C C C R R R R R R R R K 7 6 5 4 3 2 1 0 S T O P S A C K Wiper Position (Sent by Master on SDA) S W W W W W W W W A C C C C C C C C C R R R R R R R R K 7 6 5 4 3 2 1 0 S T O P Write Wiper Counter Register (WCR) Device Type Device S Identifier Addresses T A R 0 1 0 1 A3 A2 A1 A0 T Instruction DR/WCR S Opcode Addresses A C K 1 0 1 0 0 0 P1 P0 Read Data Register (DR) Device Type Device S Identifier Addresses T A R 0 1 0 1 A3 A2 A1 A0 T Instruction DR/WCR S Opcode Addresses A C K 1 0 1 1 RB RA P1 P0 S A C K Wiper Position (Sent by X9259 on SDA) M W W W W W W W W A C C C C C C C C C R R R R R R R R K 7 6 5 4 3 2 1 0 S T O P Device Type Device S Identifier Addresses T A R 0 1 0 1 A3 A2 A1 A0 T Instruction DR/WCR S Opcode Addresses A C 1 1 0 0 RB RA P1 P0 K S A C K Wiper Position (Sent by Master on SDA) S W W W W W W W W A C C C C C C C C C R R R R R R R R K 7 6 5 4 3 2 1 0 S T O P HIGH-VOLTAGE WRITE CYCLE Write Data Register (DR) Global XFR Data Register (DR) to Wiper Counter Register (WCR) S T A R T Instruction DR/WCR S Opcode Addresses A C 1 A3 A2 A1 A0 K 0 0 0 1 RB RA 0 0 Device Type Identifier 0 1 Notes: (1) (2) (3) (4) (5) 0 Device Addresses S A C K S T O P “MACK”/”SACK”: stands for the acknowledge sent by the Master/Slave. “A3 ~ A0”: stands for the device addresses sent by the master. “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition. “I”: stands for the increment operation, SDA held high during active SCL phase (high). “D”: stands for the decrement operation, SDA held low during active SCL phase (high). REV 1.5 4/13/04 www.xicor.com Characteristics subject to change without notice. 13 of 25 X9259 Global XFR Wiper Counter Register (WCR) to Data Register (DR) S Device Type Device T Identifier Addresses A R 0 1 0 1 A3 A2 A1 A0 T Instruction DR/WCR S Opcode Addresses A C 1 0 0 0 RB RA 0 0 K S A C K S T O P HIGH-VOLTAGE WRITE CYCLE Transfer Wiper Counter Register (WCR) to Data Register (DR) Device S Device Type Identifier Addresses T A R 0 1 0 1 A3 A2 A1 A0 T Instruction DR/WCR S Opcode Addresses A C K 1 1 1 0 RB RA P1 P0 S A C K S T O P S A C K S T O P HIGH-VOLTAGE WRITE CYCLE Transfer Data Register (DR) to Wiper Counter Register (WCR) S Device Type Device T Identifier Addresses A R 0 1 0 1 A3 A2 A1 A0 T Instruction DR/WCR S Opcode Addresses A C 1 1 0 1 RB RA P1 P0 K Increment/Decrement Wiper Counter Register (WCR) Device S Device Type Identifier Addresses T A R 0 1 0 1 A3 A2 A1 A0 T Notes: (1) (2) (3) (4) (5) Instruction DR/WCR S Opcode Addresses A C 0 0 1 0 0 0 P1 P0 K Increment/Decrement S (Sent by Master on SDA) A C I/D I/D . . . . I/D I/D K S T O P “MACK”/”SACK”: stands for the acknowledge sent by the Master/Slave. “A3 ~ A0”: stands for the device addresses sent by the master. “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition. “I”: stands for the increment operation, SDA held high during active SCL phase (high). “D”: stands for the decrement operation, SDA held low during active SCL phase (high). REV 1.5 4/13/04 www.xicor.com Characteristics subject to change without notice. 14 of 25 X9259 ABSOLUTE MAXIMUM RATINGS COMMENT Temperature under bias ....................–65°C to +135°C Storage temperature .........................–65°C to +150°C Voltage on SCL, SDA, any address input, VCC with respect to VSS.................................. –1V to +7V ∆V = | (VH–VL) |.................................................... 5.5V Lead temperature (soldering, 10 seconds).........300°C IW (10 seconds) ................................................. ±6mA Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temp Min. Supply Voltage (VCC)(4) Limits Device 0°C +70°C X9259 5V ±10% –40°C +85°C X9259-2.7 2.7V to 5.5V Commercial Industrial Max. ANALOG CHARACTERISTICS (Over recommended industrial (2.7V) operating conditions unless otherwise stated.) Limits Symbol Parameter Min. Typ. Max. Units Test Conditions RTOTAL End to End Resistance 100 kΩ T version RTOTAL End to End Resistance 50 kΩ U version End to End Resistance Tolerance ±20 % Power Rating 50 mW IW Wiper Current ±3 mA RW Wiper Resistance 300 Ω 150 Ω VCC V VTERM Voltage on any RH or RL Pin VSS Noise 0.4 Resolution V(VCC) @ VCC = 3V RTOTAL IW = V(VCC) @ VCC = 5V RTOTAL Ref: 1V % Absolute Linearity (1) -1 +1 MI(3) Rw(n)(actual) – Rw(n)(expected)(5) Relative Linearity (2) -0.6 +0.6 MI(3) Rw(n + 1) – [Rw(n) + MI](5) ±300 Temperature Coefficient of RTOTAL Ratiometric Temp. Coefficient CH/CL/CW IW = VSS = 0V dB/ Hz -120 25°C, each pot Potentiometer Capacitances -20 ppm/°C +20 10/10/25 ppm/°C pF See Macro model Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. (3) MI = RTOT / 255 or (RH – RL) / 255, single pot (4) During power up VCC > VH, VL, and VW. (5) n = 0, 1, 2, …,255; m =0, 1, 2, …, 254. REV 1.5 4/13/04 www.xicor.com Characteristics subject to change without notice. 15 of 25 X9259 D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Limits Symbol Parameter Min. Typ. Max. Units Test Conditions ICC1 VCC supply current (active) 3 mA fSCL = 400KHz; VCC = +6V; SDA = Open; (for 2-Wire, Active, Read and ICC2 VCC supply current (non-volatile write) 5 mA fSCL = 400KHz; VCC = +6V; SDA = Open; (for 2-Wire, Active, Non-volatile Write State only) ISB VCC current (standby) 5 µA VCC = +6V; VIN = VSS or VCC; SDA = VCC; (for 2-Wire, Standby State only) ILI Input leakage current 10 µA VIN = VSS to VCC ILO Output leakage current 10 µA VOUT = VSS to VCC VIH Input HIGH voltage VCC x 0.7 VCC + 1 V –1 VCC x 0.3 V 0.4 V IOL = 3mA VIL Input LOW voltage VOL Output LOW voltage VOH Output HIGH voltage VCC - 0.8 V IOH = -1mA, VCC ≥ +3V VOH Output HIGH voltage VCC - 0.4 V IOH = -0.4mA, VCC ≤ +3V ENDURANCE AND DATA RETENTION Parameter Min. Units Minimum endurance 100,000 Data changes per bit per register Data retention 100 years CAPACITANCE Symbol (6) CIN/OUT (6) CIN Test Max. Units Test Conditions Input / Output capacitance (SDA) 8 pF VOUT = 0V Input capacitance (SCL, WP, A2, A1 and A0) 6 pF VIN = 0V POWER-UP TIMING Symbol Parameter Min. Max. Units 0.2 50 V/ms tr VCC(6) VCC Power-up rate tPUR(7) Power-up to initiation of read operation 1 ms (7) Power-up to initiation of write operation 50 ms tPUW A.C. TEST CONDITIONS Input Pulse Levels Input rise and fall times Input and output timing level VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5 Notes: (6) This parameter is not 100% tested (7) tPUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued. These parameters are periodically sampled and not 100% tested. REV 1.5 4/13/04 www.xicor.com Characteristics subject to change without notice. 16 of 25 X9259 EQUIVALENT A.C. LOAD CIRCUIT 5V SPICE Macromodel 1533Ω RTOTAL RH SDA pin RL CW CL 100pF CL 10pF 25pF 10pF RW AC TIMING Symbol Parameter Min. Max. Units 400 kHz fSCL Clock Frequency tCYC Clock Cycle Time tHIGH Clock High Time 600 ns tLOW Clock Low Time 1300 ns tSU:STA Start Setup Time 600 ns tHD:STA Start Hold Time 600 ns tSU:STO Stop Setup Time 600 ns tSU:DAT SDA Data Input Setup Time 100 ns tHD:DAT SDA Data Input Hold Time 30 ns tR SCL and SDA Rise Time 300 tF SCL and SDA Fall Time 300 ns tAA SCL Low to SDA Data Output Valid Time 0.9 µs tDH SDA Data Output Hold Time 0 ns TI Noise Suppression Time Constant at SCL and SDA inputs 50 ns tBUF Bus Free Time (Prior to Any Transmission) 1200 ns tSU:WPA A0, A1 Setup Time 0 ns tHD:WPA A0, A1 Hold Time 0 ns REV 1.5 4/13/04 2500 www.xicor.com ns Characteristics subject to change without notice. ns 17 of 25 X9259 HIGH-VOLTAGE WRITE CYCLE TIMING Symbol Parameter tWR High-voltage write cycle time (store instructions) Typ. Max. Units 5 10 ms XDCP TIMING Symbol Parameter Min. Max. Units tWRPO Wiper response time after the third (last) power supply is stable 5 10 µs tWRL Wiper response time after instruction issued (all load instructions) 5 10 µs SYMBOL TABLE WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from Low to High Will change from Low to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed N/A Changing: State Not Known Center Line is High Impedance . REV 1.5 4/13/04 www.xicor.com Characteristics subject to change without notice. 18 of 25 X9259 TIMING DIAGRAMS Start and Stop Timing (START) (STOP) tR tF SCL tSU:STA tHD:STA tSU:STO tR tF SDA Input Timing tCYC tHIGH SCL tLOW SDA tSU:DAT tHD:DAT tBUF Output Timing SCL SDA tAA REV 1.5 4/13/04 www.xicor.com tDH Characteristics subject to change without notice. 19 of 25 X9259 XDCP Timing (for All Load Instructions) (STOP) SCL LSB SDA tWRL VWx Write Protect and Device Address Pins Timing (START) (STOP) SCL ... (Any Instruction) ... SDA ... tSU:WPA tHD:WPA WP A0, A1 REV 1.5 4/13/04 www.xicor.com Characteristics subject to change without notice. 20 of 25 X9259 APPLICATIONS INFORMATION Basic Configurations of Electronic Potentiometers +VR VR RW I Three terminal Potentiometer; Variable voltage divider Two terminal Variable Resistor; Variable current Application Circuits Noninverting Amplifier VS Voltage Regulator + VO – VIN VO (REG) 317 R1 R2 Iadj R1 R2 VO = (1+R2/R1)VS VO (REG) = 1.25V (1+R2/R1)+Iadj R2 Offset Voltage Adjustment R1 Comparator with Hysterisis R2 VS VS – + VO 100KΩ – VO + } } TL072 R1 R2 10KΩ 10KΩ +12V REV 1.5 4/13/04 VUL = {R1/(R1+R2)} VO(max) RLL = {R1/(R1+R2)} VO(min) 10KΩ -12V www.xicor.com Characteristics subject to change without notice. 21 of 25 X9259 Application Circuits (continued) Attenuator Filter C VS + R2 R1 VS VO – – R VO + R3 R4 R2 R1 = R2 = R3 = R4 = 10kΩ R1 GO = 1 + R2/R1 fc = 1/(2πRC) VO = G VS -1/2 ≤ G ≤ +1/2 R1 R2 } } Inverting Amplifier Equivalent L-R Circuit VS R2 C1 – VS VO + + – R1 ZIN VO = G VS G = - R2/R1 R3 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2 Function Generator C R2 – + R1 – } RA + } RB frequency ∝ R1, R2, C amplitude ∝ RA, RB REV 1.5 4/13/04 www.xicor.com Characteristics subject to change without notice. 22 of 25 X9259 PACKAGING INFORMATION 24-Bump Chip Scale Package (CSP B24) Package Outline Drawing 9259TRR YWW I LOT # a k f d A4 A3 A2 A1 A4 A3 A2 A1 A4 A3 A2 A1 A4 A3 A2 A1 A4 A3 A2 A1 A4 A3 A2 A1 b m l e j Bottom View (Bumped Side) Top View (Marking Side) Side View e e Side View Ball Matrix 4 3 2 1 A RL1 A1 A2 RW0 B RW1 SDA WP RL0 C VSS RH1 RH0 VCC D NC RH2 RH3 NC E RW2 A3 NC1 RL3 F RL2 SCL A0 RW3 NC - must be left unconnected Millimeters Inches Symbol Min Nom. Max Package Width A 2.755 2.785 2.815 Package Length B 4.507 4.537 4.567 Package Height C 0.644 0.677 0.710 Body Thickness D 0.444 0.457 0.470 Ball Height E 0.220 0.240 0.260 Ball Diameter F 0.310 0.330 0.350 Ball Pitch – Width J 0.5 Ball Pitch – Length K 0.5 Ball to Edge Spacing – Width L 0.618 0.643 0.668 Ball to Edge Spacing – Length M 1.056 1.081 1.106 REV 1.5 4/13/04 www.xicor.com Min Nom. Characteristics subject to change without notice. Max 23 of 25 X9259 PACKAGING INFORMATION 24-Lead Plastic, TSSOP, Package Code V24 .026 (.65) BSC .169 (4.3) .252 (6.4) BSC .177 (4.5) .303 (7.70) .311 (7.90) .047 (1.20) .0075 (.19) .0118 (.30) .002 (.06) .005 (.15) .010 (.25) Gage Plane 0°–8° (4.16) (7.72) Seating Plane .020 (.50) .030 (.75) (1.78) Detail A (20X) (0.42) (0.65) .031 (.80) .041 (1.05) ALL MEASUREMENTS ARE TYPICAL See Detail “A” NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) REV 1.5 4/13/04 www.xicor.com Characteristics subject to change without notice. 24 of 25 X9259 PACKAGING INFORMATION 24-Lead Plastic, SOIC, Package Code S24 0.290 (7.37) 0.393 (10.00) 0.299 (7.60) 0.420 (10.65) Pin 1 Index Pin 1 0.014 (0.35) 0.020 (0.50) 0.598 (15.20) 0.610 (15.49) (4X) 7° 0.092 (2.35) 0.105 (2.65) 0.003 (0.10) 0.012 (0.30) 0.050 (1.27) 0.050" Typical 0.010 (0.25) X 45° 0.020 (0.50) 0.050" Typical 0° – 8° 0.009 (0.22) 0.013 (0.33) 0.420" 0.015 (0.40) 0.050 (1.27) FOOTPRINT 0.030" Typical 24 Places NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) LIMITED WARRANTY ©Xicor, Inc. 2004 Patents Pending Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. TRADEMARK DISCLAIMER: Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All others belong to their respective owners. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor’s products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. REV 1.5 4/13/04 www.xicor.com Characteristics subject to change without notice. 25 of 25