X9268TS24I

APPLICATION NOTES AND DEVELOPMENT SYSTEM A V A I L A B L E AN99 • AN115 • AN124 •AN133 • AN134 • AN135 Dual Supply / Low Power / 256-tap / 2-Wire bus X9268 Dual Digitally-Controlled (XDCPTM) Potentiometers FEATURES DESCRIPTION • Dual–Two separate potentiometers • 256 resistor taps/pot–0.4% resolution • 2-Wire Serial Interface for write, read, and transfer operations of the potentiometer • Wiper Resistance, 100Ω typical @ V+ = 5V, V- = -5V • 16 Nonvolatile Data Registers for Each Potentiometer • Nonvolatile Storage of Multiple Wiper Positions • Power On Recall. Loads Saved Wiper Position on Power Up. • Standby Current < 5µA Max • VCC: ±2.7V to ±5.5V Operation • 50KΩ, 100KΩ versions of End to End Pot Resistance • Endurance: 100,000 Data Changes per Bit per Register • 100 yr. Data Retention • 24-Lead SOIC, 24-Lead XBGA • Low Power CMOS • Power Supply VCC = ±2.7V to ±5.5V V+ = 2.7V to 5.5V V- = -2.7V to -5.5V The X9268 integrates 2 digitally controlled potentiometer (XDCP) on a monolithic CMOS integrated circuit. The digital controlled potentiometer is implemented using 255 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the 2-Wire bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and a four nonvolatile Data Registers that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array though the switches. Powerup recalls the contents of the default Data Register (DR0) to the WCR. The XDCP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. FUNCTIONAL DIAGRAM VCC 2-Wire Bus Interface Address Data Status Write Read Transfer Inc/Dec Bus Interface and Control RH1 Power On Recall Wiper Counter Registers (WCR) Control VSS RH0 V+ Data Registers (DR0–DR3) V- RW0 RL0 RW1 RL1 50KΩ or 100KΩ versions REV 1.1.4 5/4/02 www.xicor.com Characteristics subject to change without notice. 1 of 24 X9268 DETAILED FUNCTIONAL DIAGRAM RH0 RL0 RW0 VCC V+ Power On Recall R0 R1 R2 R3 SCL SDA A3 A2 INTERFACE AND CONTROL CIRCUITRY Wiper Counter Register (WCR) 50KΩ and 100KΩ 256-taps 8 A1 A0 Pot 0 Data WP Power On Recall R0 R1 R2 R3 VSS Wiper Counter Register (WCR) Resistor Array Pot 1 RL1 RH1 RW1 V- CIRCUIT LEVEL APPLICATIONS SYSTEM LEVEL APPLICATIONS • Vary the gain of a voltage amplifier • Adjust the contrast in LCD displays • Provide programmable dc reference voltages for comparators and detectors • Control the power level of LED transmitters in communication systems • Control the volume in audio circuits • Set and regulate the DC biasing point in an RF power amplifier in wireless systems • Trim out the offset voltage error in a voltage amplifier circuit • Set the output voltage of a voltage regulator • Trim the resistance in Wheatstone bridge circuits • Control the gain, characteristic frequency and Q-factor in filter circuits • Set the scale factor and zero point in sensor signal conditioning circuits • Vary the frequency and duty cycle of timer ICs • Vary the dc biasing of a pin diode attenuator in RF circuits • Control the gain in audio and home entertainment systems • Provide the variable DC bias for tuners in RF wireless systems • Set the operating points in temperature control systems • Control the operating point for sensors in industrial systems • Trim offset and gain errors in artificial intelligent systems • Provide a control variable (I, V, or R) in feedback circuits REV 1.1.4 5/4/02 www.xicor.com Characteristics subject to change without notice. 2 of 24 X9268 PIN CONFIGURATION SOIC XBGA NC 1 24 A3 A0 NC 2 23 SCL 3 22 NC NC 4 21 NC NC 5 20 NC V+ 6 19 V- 18 VSS VCC 7 X9268 2 1 3 4 A Not Available B C RL0 8 17 RW1 RH0 9 16 RH1 RW0 D 10 15 RL1 A2 11 14 A1 WP 12 13 SDA E F Top View–Bumps Down PIN ASSIGNMENTS Pin (SOIC) Pin (XBGA) Symbol Function 1 NC No Connect 2 A0 Device Address for 2-Wire bus. 3 NC No Connect 4 NC No Connect 5 NC No Connect 6 V+ 7 VCC System Supply Voltage Analog Suppy Pin (Positive) 8 RL0 Low Terminal for Potentiometer 0. 9 RH0 High Terminal for Potentiometer 0. 10 RW0 Wiper Terminal for Potentiometer 0. 11 A2 Device Address for 2-Wire bus. 12 WP Hardware Write Protect 13 SDA Serial Data Input/Output for 2-Wire bus. 14 A1 Device Address for 2-Wire bus. 15 RL1 Low Terminal for Potentiometer 1. 16 RH1 High Terminal for Potentiometer 1. 17 RW1 Wiper Terminal for Potentiometer 1. 18 VSS System Ground 19 V- Analog Supply Pin (Negative) 20 NC No Connect 21 NC No Connect 22 NC No Connect 23 SCL Serial Clock for 2-Wire bus. 24 A3 REV 1.1.4 5/4/02 Device Address for 2-Wire bus. www.xicor.com Characteristics subject to change without notice. 3 of 24 X9268 PIN DESCRIPTIONS RW The wiper pin are equivalent to the wiper terminal of a mechanical potentiometer. Since there are 4 potentiometers, there are 2 sets of RW such that RW0 is the terminal of POT 0 and so on. Bus Interface Pins SERIAL DATA INPUT/OUTPUT (SDA) The SDA is a bidirectional serial data input/output pin for a 2-Wire slave device and is used to transfer data into and out of the device. It receives device address, opcode, wiper register address and data sent from an 2-Wire master at the rising edge of the serial clock SCL, and it shifts out data after each falling edge of the serial clock SCL. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. SERIAL CLOCK (SCL) This input is used by 2-Wire master to supply 2-Wire serial clock to the X9268. DEVICE ADDRESS (A3–A0) The address inputs are used to set the least significant 3 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the Address input in order to initiate communication with the X9268. A maximum of 8 devices may occupy the 2Wire serial bus. Bias Supply Pins SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY GROUND (VSS) The VCC pin is the system supply voltage. The VSS pin is the system ground. Analog Supply Voltages (V+ and V-) These supplies are the analog voltage supplies for the potentiometer. The V+ supply is tied to the wiper switches while the V- supply is used to bias the switches and the internal P+ substrate of the integrated circuit. Both of these supplies set the voltage limits of the potentiometer. Other Pins NO CONNECT No connect pins should be left open. This pins are used for Xicor manufacturing and testing purposes. HARDWARE WRITE PROTECT INPUT (WP) The WP pin when LOW prevents nonvolatile writes to the Data Registers. Potentiometer Pins RH, RL The RH and RL pins are equivalent to the terminal connections on a mechanical potentiometer. Since there are 2 potentiometers, there are 2 sets of RH and RL such that RH0 and RL0 are the terminals of POT 0 and so on. REV 1.1.4 5/4/02 www.xicor.com Characteristics subject to change without notice. 4 of 24 X9268 These switches are controlled by a Wiper Counter Register (WCR). The 8-bits of the WCR (WCR[7:0]) are decoded to select, and enable, one of 256 switches (see Table 1). PRINCIPLES OF OPERATION The X9268 is a integrated microcircuit incorporating four resistor arrays and their associated registers and counters and the serial interface logic providing direct communication between the host and the digitally controlled potentiometers. This section provides detail description of the following: The WCR may be written directly. These Data Registers can the WCR can be read and written by the host system. – Resistor Array Description Power Up and Down Requirements. At all times, the voltages on the potentiometer pins must be less than V+ and more than V-. During power up and power down, VCC, V+, and V- must reach their final values within 1msecs of each other. The VCC ramp rate spec is always in effect. – Serial Interface Description – Instruction and Register Description. Array Description The X9268 is comprised of a resistor array (see Figure 1). Each array contains 255 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL inputs). At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (RW) output. Within each individual array only one switch may be turned on at a time. Figure 1. Detailed Potentiometer Block Diagram One of Two Potentiometers SERIAL DATA PATH SERIAL BUS INPUT FROM INTERFACE CIRCUITRY REGISTER 0 (DR0) REGISTER 1 (DR1) 8 REGISTER 2 (DR2) IF WCR = 00[H] THEN RW = RL IF WCR = FF[H] THEN RW = RH 8 PARALLEL BUS INPUT REGISTER 3 (DR3) WIPER COUNTER REGISTER (WCR) RH C O U N T E R D E C O D E INC/DEC LOGIC UP/DN MODIFIED SCL UP/DN CLK RL RW REV 1.1.4 5/4/02 www.xicor.com Characteristics subject to change without notice. 5 of 24 X9268 SERIAL INTERFACE DESCRIPTION Serial Interface The X9268 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X9268 will be considered a slave device in all applications. Clock and Data Conventions Data states on the SDA line can change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. See Figure 2. Start Condition All commands to the X9268 are preceded by the start condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The X9268 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition is met. See Figure 2. Stop Condition All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA while SCL is HIGH. See Figure 2. Acknowledge Acknowledge is a software convention used to provide a positive handshake between the master and slave devices on the bus to indicate the successful receipt of data. The transmitting device, either the master or the slave, will release the SDA bus after transmitting eight bits. The master generates a ninth clock cycle and during this period the receiver pulls the SDA line LOW to acknowledge that it successfully received the eight bits of data. The X9268 will respond with an acknowledge after recognition of a start condition and its slave address and once again after successful receipt of the command byte. If the command is followed by a data byte the X9268 will respond with a final acknowledge. See Figure 2. Figure 2. Acknowledge Response from Receiver SCL FROM MASTER 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START REV 1.1.4 5/4/02 ACKNOWLEDGE www.xicor.com Characteristics subject to change without notice. 6 of 24 X9268 Acknowledge Polling The disabling of the inputs, during the internal nonvolatile write operation, can be used to take advantage of the typical 5ms nonvolatile write cycle time. Once the stop condition is issued to indicate the end of the nonvolatile write command the X9268 initiates the internal write cycle. ACK polling, Flow 1, can be initiated immediately. This involves issuing the start condition followed by the device slave address. If the X9268 is still busy with the write operation no ACK will be returned. If the X9268 has completed the write operation an ACK will be returned and the master can then proceed with the next operation. FLOW 1: ACK Polling Sequence Nonvolatile Write Command Completed EnterACK Polling Issue START Issue STOP No Yes Further Operation? Instructions DEVICE ADDRESSING: IDENTIFICATION BYTE (ID AND A) The first byte sent to the X9268 from the host is called the Identification Byte. The most significant four bits of the slave address are a device type identifier. The ID[3:0] bits is the device id for the X9268; this is fixed as 0101[B] (refer to Table 1). The A[3:0] bits in the ID byte is the internal slave address. The physical device address is defined by the state of the A3-A0 input pins. The slave address is externally specified by the user. The X9268 compares the serial data stream with the address input state; a successful compare of both address bits is required for the X9268 to successfully continue the command sequence. Only the device which slave address matches the incoming device address sent by the master executes the instruction. The A3-A0 inputs can be actively driven by CMOS input signals or tied to VCC or VSS. INSTRUCTION BYTE (I) Issue Slave Address ACK Returned? INSTRUCTION AND REGISTER DESCRIPTION The next byte sent to the X9268 contains the instruction and register pointer information. The three most significant bits are used provide the instruction opcode I [3:0]. The RB and RA bits point to one of the four Data Registers of each associated XDCP. The least significant bit points to one of two Wiper Counter Registers or Pots. The format is shown in Table 2. No Register Selection Yes Issue Instruction Proceed REV 1.1.4 5/4/02 Register Selected RB RA DR0 0 0 DR1 0 1 DR2 1 0 DR3 1 1 Issue STOP Proceed www.xicor.com Characteristics subject to change without notice. 7 of 24 X9268 Table 1. Identification Byte Format Device Type Identifier Slave Address ID3 ID2 ID1 ID0 0 1 0 1 A3 A2 A1 (MSB) A0 (LSB) Table 2. Instruction Byte Format Data Register Selection Instruction Opcode I3 I2 I1 I0 RB Pot Selection (WCR Selection) RA 0 (MSB) P0 (LSB) Table 3. Instruction Set Instruction I3 I2 Instruction Set I1 I0 RB RA 0 P0 Operation Read Wiper Counter Register Write Wiper Counter Register 1 0 0 1 0 0 0 1/0 1 0 1 0 0 0 0 1/0 Read Data Register 1 0 1 1 1/0 1/0 0 1/0 Write Data Register 1 1 0 0 1/0 1/0 0 1/0 XFR Data Register to Wiper Counter Register 1 1 0 1 1/0 1/0 0 1/0 XFR Wiper Counter Register to Data Register 1 1 1 0 1/0 1/0 0 1/0 Global XFR Data Registers to Wiper Counter Registers 0 0 0 1 1/0 1/0 0 0 Global XFR Wiper Counter Registers to Data Register 1 0 0 0 1/0 1/0 0 0 Increment/Decrement Wiper Counter Register 0 0 1 0 0 0 0 1/0 Read the contents of the Wiper Counter Register pointed to by P0 Write new value to the Wiper Counter Register pointed to by P0 Read the contents of the Data Register pointed to by P0 and RB-RA Write new value to the Data Register pointed to by P0 and RB-RA Transfer the contents of the Data Register pointed to by P0 and RB-RA to its associated Wiper Counter Register Transfer the contents of the Wiper Counter Register pointed to by P0 to the Data Register pointed to by RB-RA Transfer the contents of the Data Registers pointed to by RB-RA of all four pots to their respective Wiper Counter Registers Transfer the contents of both Wiper Counter Registers to their respective data Registers pointed to by RB-RA of all four pots Enable Increment/decrement of the Control Latch pointed to by P0 Note: 1/0 = data is one or zero REV 1.1.4 5/4/02 www.xicor.com Characteristics subject to change without notice. 8 of 24 X9268 DEVICE DESCRIPTION Wiper Counter Register (WCR) The X9268 contains two Wiper Counter Registers, one for each DCP potentiometer. The Wiper Counter Register can be envisioned as a 8-bit parallel and serial load counter with its outputs decoded to select one of 256 switches along its resistor array. The contents of the WCR can be altered in four ways: it may be written directly by the host via the Write Wiper Counter Register instruction (serial load); it may be written indirectly by transferring the contents of one of four associated data registers via the XFR Data Register instruction (parallel load); it can be modified one step at a time by the Increment/Decrement instruction (see Instruction section for more details). Finally, it is loaded with the contents of its Data Register zero (DR0) upon power-up. The Wiper Counter Register is a volatile register; that is, its contents are lost when the X9268 is powereddown. Although the register is automatically loaded with the value in DR0 upon power-up, this may be different from the value present at power-down. Powerup guidelines are recommended to ensure proper loadings of the DR0 value into the WCR (See Design Considerations Section). Data Registers (DR) Each potentiometer has four 8-bit nonvolatile Data Registers. These can be read or written directly by the host. Data can also be transferred between any of the four Data Registers and the associated Wiper Counter Register. All operations changing data in one of the data registers is a nonvolatile operation and will take a maximum of 10ms. If the application does not require storage of multiple settings for the potentiometer, the Data Registers can be used as regular memory locations for system parameters or user preference data. Bit [7:0] are used to store one of the 256 wiper positions (0~255). Table 1. Wiper counter Register, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile, V). WCR7 WCR6 WCR5 WCR4 WCR3 WCR2 WCR1 WCR0 V V V V V V V V (MSB) (LSB) Table 2. Data Register, DR (8-bit), Bit [7:0]: Used to store wiper positions or data (Nonvolatile, NV). Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 NV NV NV NV NV NV NV NV MSB REV 1.1.4 5/4/02 LSB www.xicor.com Characteristics subject to change without notice. 9 of 24 X9268 DEVICE DESCRIPTION Instructions Four of the nine instructions are three bytes in length. These instructions are: – Read Wiper Counter Register – read the current wiper position of the selected potentiometer, – Write Wiper Counter Register – change current wiper position of the selected potentiometer, – Read Data Register – read the contents of the selected Data Register; – Write Data Register – write a new value to the selected Data Register. The basic sequence of the three byte instructions is illustrated in Figure 4. These three-byte instructions exchange data between the WCR and one of the Data Registers. A transfer from a Data Register to a WCR is essentially a write to a static RAM, with the static RAM controlling the wiper position. The response of the wiper to this action will be delayed by tWRL. A transfer from the WCR (current wiper position), to a Data Register is a write to nonvolatile memory and takes a minimum of tWR to complete. The transfer can occur between one of the four potentiometers and one of its associated registers; or it may occur globally, where the transfer occurs between all potentiometers and one associated register Four instructions require a two-byte sequence to complete. These instructions transfer data between the host and the X9268; either between the host and one of the data registers or directly between the host and the Wiper Counter Register. These instructions are: REV 1.1.4 5/4/02 – XFR Data Register to Wiper Counter Register – This transfers the contents of one specified Data Register to the associated Wiper Counter Register. – XFR Wiper Counter Register to Data Register – This transfers the contents of the specified Wiper Counter Register to the specified associated Data Register. – Global XFR Data Register to Wiper Counter Register – This transfers the contents of all specified Data Registers to the associated Wiper Counter Registers. – Global XFR Wiper Counter Register to Data Register – This transfers the contents of all Wiper Counter Registers to the specified associated Data Registers. INCREMENT/DECREMENT COMMAND The final command is Increment/Decrement (Figure 5 and 6). The Increment/Decrement command is different from the other commands. Once the command is issued and the X9268 has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby, providing a fine tuning capability to the host. For each SCL clock pulse (tHIGH) while SDA is HIGH, the selected wiper will move one resistor segment towards the RH terminal. Similarly, for each SCL clock pulse while SDA is LOW, the selected wiper will move one resistor segment towards the RL terminal. See Instruction format for more details. www.xicor.com Characteristics subject to change without notice. 10 of 24 X9268 Figure 3. Two-Byte Instruction Sequence SCL SDA 0 1 0 1 S ID3 ID2 ID1 ID0 A3 A2 A1 A0 T A Internal R Device ID Address T A I3 C K I2 I1 I0 Instruction Opcode RB RA 0 Register Address P0 A C K Pot/WCR Address S T O P Figure 4. Three-Byte Instruction Sequence SCL SDA 0 1 0 1 0 S ID3 ID2 ID1 ID0 A3 T A Device ID R T A2 A0 A I3 C K Internal Address I2 A1 I1 I0 Instruction Opcode RB RA 0 P0 A C K Register Pot/WCR Address Address D7 D6 D5 D4 D3 D2 D1 D0 WCR[7:0] or Data Register D[7:0] A C K S T O P Figure 5. Increment/Decrement Instruction Sequence SCL 0 SDA S T A R T 1 0 1 ID3 ID2 ID1 ID0 A3 Device ID 0 A2 A1 A0 Internal Address A C K I3 I2 I1 Instruction Opcode I0 RB RA 0 P0 A C Register Pot/WCR K Address Address I N C 1 I N C 2 I N C n D E C 1 D E C n S T O P Figure 6. Increment/Decrement Timing Limits INC/DEC CMD Issued tWRID SCL SDA RW REV 1.1.4 5/4/02 Voltage Out www.xicor.com Characteristics subject to change without notice. 11 of 24 X9268 INSTRUCTION FORMAT Read Wiper Counter Register (WCR) Device Type Device S Identifier Addresses T A R 0 1 0 1 A3 A2 A1 A0 T Instruction DR/WCR S Opcode Addresses A C K 1 0 0 1 0 0 0 P0 S A C K Wiper Position (Sent by X9268 on SDA) M W W W W W W W W A C C C C C C C C C R R R R R R R R K 7 6 5 4 3 2 1 0 S T O P S A C K Wiper Position (Sent by Master on SDA) S W W W W W W W W A C C C C C C C C C R R R R R R R R K 7 6 5 4 3 2 1 0 S T O P Write Wiper Counter Register (WCR) Device Type Device S Identifier Addresses T A R 0 1 0 1 A3 A2 A1 A0 T Instruction DR/WCR S Opcode Addresses A C K 1 0 1 0 0 0 0 P0 Read Data Register (DR) Device Type Device S Identifier Addresses T A R 0 1 0 1 A3 A2 A1 A0 T Instruction DR/WCR S Opcode Addresses A C K 1 0 1 1 RB RA 0 P0 S A C K Wiper Position (Sent by X9268 on SDA) M W W W W W W W W A C C C C C C C C C R R R R R R R R K 7 6 5 4 3 2 1 0 S T O P Device Type Device S Identifier Addresses T A R 0 1 0 1 A3 A2 A1 A0 T Instruction DR/WCR S Opcode Addresses A C 1 1 0 0 RB RA 0 P0 K S A C K Wiper Position (Sent by Master on SDA) S W W W W W W W W A C C C C C C C C C R R R R R R R R K 7 6 5 4 3 2 1 0 S T O P HIGH-VOLTAGE WRITE CYCLE Write Data Register (DR) Global XFR Data Register (DR) to Wiper Counter Register (WCR) S T A R T Instruction DR/WCR S Opcode Addresses A C 1 A3 A2 A1 A0 K 0 0 0 1 RB RA 0 0 Device Type Identifier 0 1 0 REV 1.1.4 5/4/02 Device Addresses www.xicor.com S A C K S T O P Characteristics subject to change without notice. 12 of 24 X9268 Global XFR Wiper Counter Register (WCR) to Data Register (DR) S Device Type Device T Identifier Addresses A R 0 1 0 1 A3 A2 A1 A0 T Instruction DR/WCR S Opcode Addresses A C 1 0 0 0 RB RA 0 0 K S A C K S T O P HIGH-VOLTAGE WRITE CYCLE Transfer Wiper Counter Register (WCR) to Data Register (DR) Device S Device Type Identifier Addresses T A R 0 1 0 1 A3 A2 A1 A0 T Instruction DR/WCR S Opcode Addresses A C K 1 1 1 0 RB RA 0 P0 S A C K S T O P S A C K S T O P HIGH-VOLTAGE WRITE CYCLE Transfer Data Register (DR) to Wiper Counter Register (WCR) S Device Type Device T Identifier Addresses A R 0 1 0 1 A3 A2 A1 A0 T Instruction DR/WCR S Opcode Addresses A C 1 1 0 1 RB RA 0 P0 K Increment/Decrement Wiper Counter Register (WCR) Device S Device Type Identifier Addresses T A R 0 1 0 1 A3 A2 A1 A0 T Notes: (1) (2) (3) (4) (5) Instruction DR/WCR S Opcode Addresses A C 0 0 1 0 0 0 0 P0 K Increment/Decrement S (Sent by Master on SDA) A C I/D I/D . . . . I/D I/D K S T O P “MACK”/”SACK”: stands for the acknowledge sent by the master/slave. “A3 ~ A0”: stands for the device addresses sent by the master. “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition. “I”: stands for the increment operation, SDA held high during active SCL phase (high). “D”: stands for the decrement operation, SDA held low during active SCL phase (high). REV 1.1.4 5/4/02 www.xicor.com Characteristics subject to change without notice. 13 of 24 X9268 ABSOLUTE MAXIMUM RATINGS COMMENT Temperature under bias ....................–65°C to +135°C Storage temperature .........................–65°C to +150°C Voltage on SDA, SCL or any address input with respect to VSS.................................. –1V to +7V Voltage on V+ (referenced to VSS) ........................ 10V Voltage on V- (referenced to VSS)......................... -10V (V+) – (V-).............................................................. 12V Any VH/RH ............................................................... V+ Any VL/RL ................................................................. VLead temperature (soldering, 10 seconds).........300°C IW (10 seconds) ................................................. ±6mA Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temp Min. Max. Device Supply Voltage (VCC)(4) Limits Commercial 0°C +70°C X9268 5V ±10% –40°C +85°C X9268-2.7 2.7V to 5.5V V+ 2.7V to 5.5V V- -2.7V to -5.5V Industrial REV 1.1.4 5/4/02 www.xicor.com Characteristics subject to change without notice. 14 of 24 X9268 POTENTIOMETER CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.) Limits Symbol Parameter Min. Typ. Max. Unit Test Conditions RTOTAL End to End Resistance 100 kΩ T version RTOTAL End to EndResistance 50 kΩ U version End to end resistance tolerance ±20 % Power rating 50 mW IW Wiper current ±3 mA RW Wiper resistance 250 Ω IW = ± 1mA, V+ = 3V; V- = -3V IW = ± 1mA, V+ = 5V; V- = -5V RW Wiper resistance V+ Voltage on V+ Pin VVTERM Voltage on V- Pin 150 Ω X9268 +4.5 +5.5 V X9268-2.7 +2.7 +5.5 X9268 -5.5 -4.5 X9268 -2.7 -5.5 -2.7 V- V+ Voltage on any VH/RH or VL/RL pin Noise Resolution (4) Absolute linearity 0.4 % MI(3) Vw(n)(actual)–Vw(n)(expected) ±0.6 MI(3) Vw(n + 1)–[Vw(n) + MI] ppm/°C ±20 10/10/25 Ref: 1kHz ±1 ±300 Ratiometric Temperature Coefficient CH/CL/CW Potentiometer Capacitance V dBV Relative linearity (2) Temperature coefficient of resistance V -120 (1) 25°C, each pot ppm/°C pF See Circuit #3 Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. (3) MI = RTOT / 255 or (RH – RL) / 255, single pot (4) During power up VCC > VH, VL, and VW. (5) n = 0, 1, 2, …,255; m =0, 1, 2, …, 254. REV 1.1.4 5/4/02 www.xicor.com Characteristics subject to change without notice. 15 of 24 X9268 D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Symbol Parameter Limits Typ. Max. Units Test Conditions ICC1 VCC supply current (active) Min. 3 mA fSCL = 400KHz; VCC = +6V; SDA = Open; (for 2-Wire, Active, Read and ICC2 VCC supply current (nonvolatile write) 5 mA fSCL = 400KHz; VCC = +6V; SDA = Open; (for 2-Wire, Active, Nonvolatile Write State only) ISB VCC current (standby) 5 µA VCC = +6V; VIN = VSS or VCC; SDA = VCC; (for 2-Wire, Standby State only) ILI Input leakage current 10 µA VIN = VSS to VCC ILO Output leakage current 10 µA VOUT = VSS to VCC VIH Input HIGH voltage VCC x 0.7 VCC + 1 V VIL Input LOW voltage –1 VCC x 0.3 V VOL Output LOW voltage 0.4 V VOH Output HIGH voltage IOL = 3mA ENDURANCE AND DATA RETENTION Parameter Min. Units Minimum endurance 100,000 Data changes per bit per register Data retention 100 years CAPACITANCE Symbol (6) Test Max. Units Test Conditions CIN/OUT Input / Output capacitance (SDA) 8 pF VOUT = 0V CIN(6) Input capacitance (SCL, WP, A3, A2, A1 and A0) 6 pF VIN = 0V POWER-UP TIMING Symbol (6) tr VCC (7) tPUR Parameter VCC Power-up rate Power-up to initiation of read operation Min. Max. Units 0.2 50 V/ms 1 ms POWER UP AND DOWN REQUIREMENTS The are no restrictions on the sequencing of the bias supplies VCC, V+, and V- provided that all three supplies reach their final values within 1msec of each other. At all times, the voltages on the potentiometer pins must be less than V+ and more than V-. The recall of the wiper position from nonvolatile memory is not in effect until all supplies reach their final value. The VCC ramp rate spec is always in effect. A.C. TEST CONDITIONS Input Pulse Levels Input rise and fall times Input and output timing level VCC x 0.1 to VCC x 0.9 10ns VCC x 0.5 Notes: (6) This parameter is not 100% tested (7) tPUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued. These parameters are periodically sampled and not 100% tested. Characteristics subject to change without notice. 16 of 24 REV 1.1.4 5/4/02 www.xicor.com X9268 EQUIVALENT A.C. LOAD CIRCUIT 5V 3V 1533Ω SPICE Macromodel 867Ω RTOTAL RH SDA pin RL SDA pin CW CL 100pF 100pF CL 10pF 25pF 10pF RW AC TIMING Symbol Parameter Min. Max. Units 400 kHz fSCL Clock Frequency tCYC Clock Cycle Time 2500 ns tHIGH Clock High Time 600 ns tLOW Clock Low Time 1300 ns tSU:STA Start Setup Time 600 ns tHD:STA Start Hold Time 600 ns tSU:STO Stop Setup Time 600 ns tSU:DAT SDA Data Input Setup Time 100 ns tHD:DAT SDA Data Input Hold Time 30 ns tR SCL and SDA Rise Time 300 ns tF SCL and SDA Fall Time 300 ns tAA SCL Low to SDA Data Output Valid Time 0.9 µs tDH SDA Data Output Hold Time 0 ns TI Noise Suppression Time Constant at SCL and SDA inputs 50 ns tBUF Bus Free Time (Prior to Any Transmission) 1200 ns tSU:WPA A0, A1 Setup Time 0 ns tHD:WPA A0, A1 Hold Time 0 ns HIGH-VOLTAGE WRITE CYCLE TIMING Symbol Parameter tWR High-voltage write cycle time (store instructions) Typ. Max. Units 5 10 ms XDCP TIMING Symbol Parameter Min. Max. Units tWRPO Wiper response time after the third (last) power supply is stable 5 10 µs tWRL Wiper response time after instruction issued (all load instructions) 5 10 µs .REV 1.1.4 5/4/02 www.xicor.com Characteristics subject to change without notice. 17 of 24 X9268 TIMING DIAGRAMS Start and Stop Timing (START) (STOP) tR tF SCL tSU:STA tHD:STA tSU:STO tR tF SDA Input Timing tCYC tHIGH SCL tLOW SDA tSU:DAT tHD:DAT tBUF Output Timing SCL SDA tAA REV 1.1.4 5/4/02 www.xicor.com tDH Characteristics subject to change without notice. 18 of 24 X9268 XDCP Timing (for All Load Instructions) (STOP) SCL LSB SDA tWRL VWx Write Protect and Device Address Pins Timing (START) (STOP) SCL ... (Any Instruction) ... SDA ... tSU:WPA tHD:WPA WP A0, A1 REV 1.1.4 5/4/02 www.xicor.com Characteristics subject to change without notice. 19 of 24 X9268 APPLICATIONS INFORMATION Basic Configurations of Electronic Potentiometers +VR VR RW I Three terminal Potentiometer; Variable voltage divider Two terminal Variable Resistor; Variable current Application Circuits Noninverting Amplifier VS Voltage Regulator + VO – VIN VO (REG) 317 R1 R2 Iadj R1 R2 VO = (1+R2/R1)VS VO (REG) = 1.25V (1+R2/R1)+Iadj R2 Offset Voltage Adjustment R1 Comparator with Hysterisis R2 VS VS – + VO 100KΩ – VO + } } TL072 R1 R2 10KΩ 10KΩ +12V REV 1.1.4 5/4/02 VUL = {R1/(R1+R2)} VO(max) VLL = {R1/(R1+R2)} VO(min) 10KΩ -12V www.xicor.com Characteristics subject to change without notice. 20 of 24 X9268 Application Circuits (continued) Attenuator Filter C VS + R2 R1 VS VO – – R VO + R3 R4 R2 R1 = R2 = R3 = R4 = 10kΩ R1 GO = 1 + R2/R1 fc = 1/(2πRC) VO = G VS -1/2 ≤ G ≤ +1/2 R1 R2 } } Inverting Amplifier Equivalent L-R Circuit VS R2 C1 – VS VO + + – R1 ZIN VO = G VS G = - R2/R1 R3 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2 Function Generator C R2 – + R1 – } RA + } RB frequency ∝ R1, R2, C amplitude ∝ RA, RB REV 1.1.4 5/4/02 www.xicor.com Characteristics subject to change without notice. 21 of 24 X9268 PACKAGING INFORMATION 24-Ball BGA (X9268TA/X9268UA) a a 1 2 l 3 m 4 j 4 3 2 1 A A B B k C C D D E E b b f F Top View (Bump Side Down) F Bottom View (Bump Side Up) Note: Drawing not to scale d = Die Orientation mark c e Side View (Bump Side Down) Millimeters Inches Symbol Min Nom. Max Nom Min Max Package Body Dimension X a 2.810 2.775 2.845 0.11063 0.10925 0.11201 Package Body Dimension Y b 4.588 4.553 4.623 0.18063 0.17925 0.18201 Package Height c 0.635 0.505 0.765 0.02500 0.01988 0.03012 Package Body Thickness d 0.433 0.395 0.471 0.01705 0.01555 0.01854 Ball Height e 0.202 0.110 0.294 0.00795 0.00433 0.01157 Ball Diameter f 0.284 0.180 0.388 0.01118 0.00709 0.01528 Total Ball Count g 24 Ball Count X Axis h 4 Ball Count Y Axis i 6 Pins Pitch X Axis j 0.5 Pins Pitch Y Axis k 0.5 Edge to Ball Center (Corner) Distance Along X l 0.655 0.620 0.690 0.02579 0.02441 0.02717 Edge to Ball Center (Corner) Distance Along Y m 1.044 1.009 1.079 0.04110 0.03972 0.04248 REV 1.1.4 5/4/02 www.xicor.com Characteristics subject to change without notice. 22 of 24 X9268 PACKAGING INFORMATION 24-Lead Plastic Small Outline Gull Wing Package Type S 0.290 (7.37) 0.393 (10.00) 0.299 (7.60) 0.420 (10.65) Pin 1 Index Pin 1 0.014 (0.35) 0.020 (0.50) 0.598 (15.20) 0.610 (15.49) (4X) 7° 0.092 (2.35) 0.105 (2.65) 0.003 (0.10) 0.012 (0.30) 0.050 (1.27) 0.050" Typical 0.010 (0.25) X 45° 0.020 (0.50) 0.050" Typical 0° – 8° 0.009 (0.22) 0.013 (0.33) 0.420" 0.015 (0.40) 0.050 (1.27) FOOTPRINT 0.030" Typical 24 Places NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) REV 1.1.4 5/4/02 www.xicor.com Characteristics subject to change without notice. 23 of 24 X9268 ORDERING INFORMATION X9268 Y P T V VCC Limits Blank = 5V ±10% –2.7 = 2.7 to 5.5V Device Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = –40°C to +85°C Package S24 = 24-Lead SOIC xxx = xxx-Lead XBGA Potentiometer Organization Pot U= 50KΩ T= 100KΩ PART MARK CONVENTION xx Lead XBGA Top Mark X9268xxxx-2.7 X9268xxxx xx X9268 xxxx X9268xxxxx I-2.7 X9268xxxx-2.7 X9268xxxx xx X9268 xxxx X9268xxxxx I-2.7 LIMITED WARRANTY ©Xicor, Inc. 2000 Patents Pending Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. TRADEMARK DISCLAIMER: Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All others belong to their respective owners. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor’s products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. REV 1.1.4 5/4/02 www.xicor.com Characteristics subject to change without notice. 24 of 24