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NOT RECOMMENDED FOR NEW DESIGNS
NO RECOMMENDED REPLACEMENT
contact our Technical Support Center at
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X93155
FN8181
Rev 2.00
February 19, 2008
Digitally Controlled Potentiometer (XDCP™)
The Intersil X93155 is a digitally controlled potentiometer
(XDCP). The device consists of a resistor array, wiper
switches, a control section, and nonvolatile memory. The
wiper position is controlled by a 3-wire interface.
Features
The potentiometer is implemented by a resistor array
composed of 31 resistive elements and a wiper switching
network. The position of the wiper element is controlled by
the CS, U/D, and INC inputs. The position of the wiper can
be stored in nonvolatile memory and then be recalled upon
during a subsequent power-up operation.
• 32 wiper tap points per potentiometer
- Wiper position stored in nonvolatile memory and
recalled on power-up
• Solid-state potentiometer
• Up/Down interface
• 31 resistive elements per potentiometer
- Temperature compensated
- Maximum resistance tolerance ±25%
- Terminal voltage, 0 to VCC
The device is connected as a two-terminal variable resistor
and can be used in a wide variety of applications including:
• Low power CMOS
- VCC = 5V ±10%
- Active current, 200µA typ.
- Standby current, 2.0µA max
- Bias and Gain Control
- LCD Contrast Adjustment
Pinout
• High reliability
- Endurance 200,000 data changes per bit
- Register data retention, 100 years
X93155
(8 LD MSOP)
TOP VIEW
INC
1
8
VCC
U/D
2
7
CS
RH
3
6
RL
VSS
4
5
NC*
• RTOTAL value = 50k
• Packages
- 8 Ld MSOP
• Pb-free available (RoHS compliant)
*NC can be left unconnected, or connected to any voltage between VSS
and VCC.
Ordering Information
PART NUMBER
PART MARKING VCC LIMITS (V)
X93155UM8I*
AGM
X93155UM8IZ* (Note)
DCH
5 ±10%
RTOTAL (k)
TEMP
RANGE (°C)
50
-40 to +85
8 Ld MSOP
M8.118
-40 to +85
8 Ld MSOP
(Pb-free)
M8.118
PACKAGE
PKG DWG. #
*Add "T1" suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
FN8181 Rev 2.00
February 19, 2008
Page 1 of 8
X93155
Block Diagram
VCC (SUPPLY VOLTAGE)
U/D
INC
CS
30k
5-BIT
UP/DOWN
COUNTER
30
29
RH
UP/DOWN
(U/D)
5-BIT
NONVOLATILE
MEMORY
CONTROL
AND
MEMORY
INCREMENT
(INC)
RH
31
DEVICE SELECT
STORE AND
CONTROL
RECALL
CIRCUITRY
(CS)
RL
28
ONE
OF
THIRTY
TWO
DECODER
TRANSFER
GATES
RESISTOR
ARRAY
2
1
VCC
0
VSS (Ground)
VSS
RL
GENERAL
DETAILED
Pin Descriptions
MSOP
SYMBOL
1
INC
Increment (INC). The INC input is negative-edge triggered. Toggling INC will move the wiper and either increment or
decrement the counter in the direction indicated by the logic level on the U/D input.
2
U/D
Up/Down (U/D). The U/D input controls the direction of the wiper movement and whether the counter is incremented or
decremented.
3
RH
RH. The RH and RL pins of the X93155 are equivalent to the end terminals of a variable resistor.
4
VSS
Ground.
5
NC
No Connection (or can be connected to any voltage between VSS and VCC.)
6
RL
RL. The RH and RL pins of the X93155 are equivalent to the end terminals of a variable resistor.
7
CS
Chip Select (CS). The device is selected when the CS input is LOW. The current counter value is stored in nonvolatile
memory when CS is returned HIGH while the INC input is also HIGH. After the store operation is complete, the X93155
will be placed in the low power standby mode until the device is selected once again.
8
VCC
Supply Voltage.
FN8181 Rev 2.00
February 19, 2008
BRIEF DESCRIPTION
Page 2 of 8
X93155
Absolute Maximum Ratings
Thermal Information
Voltage on CS, INC, U/D, RH, RL and VCC
with respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +6.5V
Maximum resistor current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2mA
Temperature under bias. . . . . . . . . . . . . . . . . . . . . .-65C to +135C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Maximum reflow temperature (40s) . . . . . . . . . . . . . . . . . . . . +240°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature Range
Industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V ±10% (Note 6)
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. Absolute linearity is utilized to determine actual wiper resistance versus expected resistance = (RH(n)(actual)-RH(n)(expected)) = ±1 Ml Maximum.
n = 1 .. 29 only
2. Relative linearity is a measure of the error in step size between taps = RH(n+1)—[RH(n) + Ml] = ±0.5 Ml, n = 1 .. 29 only.
3. 1 Ml = Minimum Increment = RTOT/31.
4. Typical values are for TA = +25°C and nominal supply voltage.
5. Limits established by characterization and are not production tested.
6. When performing multiple write operations, VCC must not decrease by more than 150mV from its initial value.
7. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested.
Potentiometer Specifications
SYMBOL
RTOT
VR
IR
Over recommended operating conditions, unless otherwise stated.
PARAMETER
TEST CONDITIONS/NOTES
End-to-end Resistance
RH, RL Terminal Voltages
MIN
(Note 7)
TYP
(Note 4)
MAX
(Note 7)
UNIT
37.5
50
62.5
k
VCC
V
1
mW
(Note 5)
0
Power Rating
RTOTAL 50k
Noise
Ref: 1kHz
Potentiometer Current
(Note 5)
-120
0.6
Resolution
CH/CL/CW
3
Absolute linearity (Note 1)
RH(n)(actual)-RH(n)(expected)
Relative linearity (Note 2)
RH(n+1)-[RH(n)+MI]
RTOTAL Temperature Coefficient
(Note 5)
Potentiometer Capacitances
See “Circuit #2 SPICE Macro
Model” on page 4
DC Electrical Specifications
SYMBOL
dBV
(Note 5)
mA
%
±1
MI
(Note 3)
±0.5
MI
(Note 3)
±35
ppm/°C
10/10/25
pF
(Note 5)
Over recommended operating conditions unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
(Note 7)
TYP
(Note 4)
MAX
(Note 7)
UNIT
200
300
µA
1400
µA
ICC1
VCC Active Current (Increment)
CS = VIL, U/D = VIL or VIH and
INC = 0.4V @ max. tCYC
ICC2
VCC Active Current (Store)
(EEPROM Store)
CS = VIH, U/D = VIL or VIH and
INC = VIH @ max. tWR
ISB
Standby Supply Current
CS = VCC - 0.3V, U/D and INC = VSS
or VCC - 0.3V
2.0
µA
ILI
CS
VCS = VCC
±1
µA
FN8181 Rev 2.00
February 19, 2008
Page 3 of 8
X93155
DC Electrical Specifications
SYMBOL
Over recommended operating conditions unless otherwise specified. (Continued)
PARAMETER
TEST CONDITIONS
MIN
(Note 7)
TYP
(Note 4)
MAX
(Note 7)
UNIT
120
200
250
µA
±1
µA
ILI
CS
VCC = 5V, CS = 0
ILI
INC, U/D Input Leakage Current
VIN = VSS to VCC
VIH
CS, INC, U/D Input HIGH Voltage
VCC x 0.7
VCC + 0.5
V
VIL
CS, INC, U/D Input LOW Voltage
-0.5
VCC x 0.1
V
CIN
(Note 5)
CS, INC, U/D Input Capacitance
10
pF
VCC = 5V, VIN = VSS, TA = +25°C,
f = 1MHz
Circuit #2 SPICE Macro Model
Endurance and Data Retention
PARAMETER
MIN
UNIT
Minimum endurance
200,000
Data changes per bit
Data retention
100
RTOTAL
RH
Years
CL
CW
CH
RL
10pF
Test Circuit #1
25pF
TEST POINT
10pF
VH/RH
AC Conditions of Test
VL
AC Electrical Specifications
SYMBOL
Input pulse levels
0V to 5V
Input rise and fall times
10ns
Input reference levels
1.5V
Over recommended operating conditions, unless otherwise specified.
PARAMETER
MIN
(Note 7)
TYP
(Note 4)
MAX
(Note 7)
UNIT
tCl
CS to INC Setup
100
ns
tlD
INC HIGH to U/D Change
100
ns
tDI
U/D to INC Setup
100
ns
tlL
INC LOW Period
1
µs
tlH
INC HIGH Period
1
µs
tlC
INC Inactive to CS Inactive
1
µs
tCPH
CS Deselect Time (No Store)
250
ns
tCPH
CS Deselect Time (Store)
10
ms
tCYC
INC Cycle Time
2
µs
tR , tF
(Note 5)
INC Input Rise and Fall time
tR VCC
(Note 5)
VCC Power-up Rate
tWR
Store Cycle
FN8181 Rev 2.00
February 19, 2008
1
5
500
µs
50
V/ms
10
ms
Page 4 of 8
X93155
AC Timing
CS
tCYC
tCI
tIL
tIH
tIC
(STORE)
tCPH
90%
INC
90%
10%
tID
tDI
tF
tR
U/D
Power-up and Power-down Requirements
There are no restrictions on the power-up or power-down
conditions of VCC and the voltages applied to the
potentiometer pins provided that VCC is always more positive
than or equal to VH and VL, i.e., VCC VH,VL. The VCC ramp
rate specification is always in effect.
Pin Descriptions
RH and RL
The RH and RL pins of the X93155 are equivalent to the end
terminals of a variable resistor. The minimum voltage is VSS
and the maximum is VCC. The terminology of RH and RL
references the relative position of the terminal in relation to
wiper movement direction selected by the U/D input.
Up/Down (U/D)
The U/D input controls the direction of the wiper movement
and whether the counter is incremented or decremented.
and retained for future use. The resistor array is comprised of
31 individual resistors connected in series. At either end of the
array and between each resistor is an electronic switch that
transfers the connection at that point to the wiper. The wiper is
connected to the RL terminal, forming a variable resistor from
RH to RL.
The wiper, when at either fixed terminal, acts like its
mechanical equivalent and does not move beyond the last
position. That is, the counter does not wrap around when
clocked to either extreme.
If the wiper is moved several positions, multiple taps are
connected to the wiper for up to 10µs. The 2-terminal
resistance value for the device can temporarily change by a
significant amount if the wiper is moved several positions.
When the device is powered-down, the last wiper position
stored will be maintained in the nonvolatile memory. When
power is restored, the contents of the memory are recalled and
the wiper is set to the value last stored.
Increment (INC)
The INC input is negative-edge triggered. Toggling INC will
move the wiper and either increment or decrement the counter
in the direction indicated by the logic level on the U/D input.
Chip Select (CS)
The device is selected when the CS input is LOW. The current
counter value is stored in nonvolatile memory when CS is
returned HIGH while the INC input is also HIGH. After the store
operation is complete, the X93155 will be placed in the low
power standby mode until the device is selected once again.
Principles of Operation
There are three sections of the X93155: the input control,
counter and decode section; the nonvolatile memory; and the
resistor array. The input control section operates just like an
up/down counter. The output of this counter is decoded to turn
on a single electronic switch connecting a point on the resistor
array to the wiper output. Under the proper conditions the
contents of the counter can be stored in nonvolatile memory
FN8181 Rev 2.00
February 19, 2008
Instructions and Programming
The INC, U/D and CS inputs control the movement of the wiper
along the resistor array. With CS set LOW, the device is
selected and enabled to respond to the U/D and INC inputs.
HIGH to LOW transitions on INC will increment or decrement
(depending on the state of the U/D input) a five bit counter. The
output of this counter is decoded to select one of thirty two
wiper positions along the resistive array.
The value of the counter is stored in nonvolatile memory
whenever CS transitions HIGH while the INC input is also
HIGH. In order to avoid an accidental store during power-up,
CS must go HIGH with VCC during initial power-up. When left
open, the CS pin is internally pulled up to VCC by an internal
30k resistor.
The system may select the X93155, move the wiper and
deselect the device without having to store the latest wiper
position in nonvolatile memory. After the wiper movement is
performed as previously described and once the new position
Page 5 of 8
X93155
is reached, the system must keep INC LOW while taking CS
HIGH. The new wiper position will be maintained until changed
by the system or until a power-up/down cycle recalled the
previously stored data. In order to recall the stored position of
the wiper on power-up, the CS pin must be held HIGH.
Symbol Table
WAVEFORM
This procedure allows the system to always power-up to a
preset value stored in nonvolatile memory; then during system
operation, minor adjustments could be made. The adjustments
might be based on user preference, system parameter
changes due to temperature drift, or other system trim
requirements.
The state of U/D may be changed while CS remains LOW. This
allows the host system to enable the device and then move the
wiper up and down until the proper trim is attained.
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
Mode Selection
CS
INC
U/D
MODE
L
H
Wiper Up
Applications Information
L
L
Wiper Down
H
X
Store Wiper Position
Electronic digitally controlled (XDCP) potentiometers provide
three powerful application advantages:
X
X
Standby Current
L
X
No Store, Return to Standby
L
H
Wiper Up (not recommended)
L
L
Wiper Down (not recommended)
H
I
1. The variability and reliability of a solid-state potentiometer
2. The flexibility of computer-based digital controls
3. The retentivity of nonvolatile memory used for the storage
of multiple potentiometer settings or data
VR
Two terminal variable resistor.
© Copyright Intersil Americas LLC 2005-2008. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8181 Rev 2.00
February 19, 2008
Page 6 of 8
X93155
Low Voltage High Impedance Instrumentation Amplifier
5V
10k
+
+
10k
50k
U1A
50k
VIN
VOUT
U1C
X93155 (RTOTAL)
+
50k
-
50k
50k )
( 1+
10k
RTOTAL
U1 = LT1467
GAIN =
10k
U1B
10k
+
-
50k
Micro-Power LCD Contrast Control
5V
300k
240k
5V
+
100k
VOUT = -4.41 ( 1 +
100k
U1A
-
-
VOUT = -8.82V TO -13.23V
U1B
U1 = LMC6042
+
50k
100k
100k
)
50k + RTOTAL
-15V
X93155 (RTOTAL)
Single Supply Variable Gain Amplifier
5V
5V
20k
+
20k
VOUT
U1
-
GAIN =
10k
U1 = LMC6042
VIN
10k
FN8181 Rev 2.00
February 19, 2008
RTOTAL
X93155
(RTOTAL)
Page 7 of 8
X93155
Mini Small Outline Plastic Packages (MSOP)
N
M8.118 (JEDEC MO-187AA)
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
E1
INCHES
E
-B-
INDEX
AREA
1 2
0.20 (0.008)
A B C
TOP VIEW
4X
0.25
(0.010)
R1
R
GAUGE
PLANE
SEATING
PLANE -CA
4X
A2
A1
b
-H-
0.10 (0.004)
L1
SEATING
PLANE
C
D
0.20 (0.008)
C
a
CL
E1
0.20 (0.008)
C D
MAX
MIN
MAX
NOTES
0.037
0.043
0.94
1.10
-
A1
0.002
0.006
0.05
0.15
-
A2
0.030
0.037
0.75
0.95
-
b
0.010
0.014
0.25
0.36
9
c
0.004
0.008
0.09
0.20
-
D
0.116
0.120
2.95
3.05
3
E1
0.116
0.120
2.95
3.05
4
0.026 BSC
-B-
0.65 BSC
-
E
0.187
0.199
4.75
5.05
-
L
0.016
0.028
0.40
0.70
6
0.037 REF
N
C
SIDE VIEW
MIN
A
L1
-A-
e
SYMBOL
e
L
MILLIMETERS
0.95 REF
8
R
0.003
R1
0
-
8
-
0.07
0.003
-
5o
15o
0o
6o
7
-
-
0.07
-
-
5o
15o
-
0o
6o
Rev. 2 01/03
END VIEW
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
and are measured at Datum Plane. - H - Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (0.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Datums -A -H- .
and - B - to be determined at Datum plane
11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only.
FN8181 Rev 2.00
February 19, 2008
Page 8 of 8
