X9319UP8I

DATASHEET X9319 FN8185 Rev 3.00 July 31, 2014 Digitally Controlled Potentiometer (XDCP™) The Intersil X9319 is a digitally controlled potentiometer (XDCP). The device consists of a resistor array, wiper switches, a control section, and nonvolatile memory. The wiper position is controlled by a 3-wire interface. Features The potentiometer is implemented by a resistor array composed of 99 resistive elements and a wiper switching network. Between each element and at either end are tap points accessible to the wiper terminal. The position of the wiper element is controlled by the CS, U/D, and INC inputs. The position of the wiper can be stored in nonvolatile memory and then be recalled upon a subsequent power-up operation. • Terminal voltage, 0 to +10V The device can be used as a three-terminal potentiometer for voltage control or as a two-terminal variable resistor for current control in a wide variety of applications. • Low power CMOS - VCC = 5V - Active current, 3mA max. - Standby current, 1mA max. Applications • Solid-state potentiometer • 3-wire serial interface • 100 wiper tap points - Wiper position stored in nonvolatile memory and recalled on power-up • 99 resistive elements - Temperature compensated - End-to-end resistance range ±20% • DC bias adjustment • High reliability - Endurance, 100,000 data changes per bit - Register data retention, 100 years • Gain and offset trim • RTOTAL value = 10kΩ • Laser diode bias control • Package - 8 Ld SOIC • LCD bias control • Voltage regulator output control • Pb-free (RoHS compliant) Block Diagram U/D INC CS VCC (SUPPLY VOLTAGE) UP/DOWN COUNTER 98 97 RH UP/DOWN (U/D) CONTROL AND MEMORY INCREMENT (INC) DEVICE SELECT (CS) RH 99 7-BIT NONVOLATILE MEMORY RW 96 ONE OF ONE HUNDRED DECODER WIPER SWITCHES RESISTOR ARRAY RL 2 VSS (GROUND) GENERAL VCC VSS STORE AND RECALL CONTROL CIRCUITRY 1 0 RL RW DETAILED FN8185 Rev 3.00 July 31, 2014 Page 1 of 8 X9319 Ordering Information PART NUMBER (Notes 1, 2, 3) PART MARKING X9319WS8Z X9319W Z X9319WS8IZ X9319W ZI PACKAGE (Pb-Free) RTOTAL (kΩ) TEMP RANGE (°C) PKG. DWG. # 10 0 to +70 8 Ld SOIC (150 mil) M8.15E -40 to +85 8 Ld SOIC (150 mil) M8.15E NOTES: 1. Add "T1" suffix for tape and reel. 2. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see product information page for X9319. For more information on MSL, please see tech brief TB363. Pin Configuration X9319 (8 LD SOIC) TOP VIEW INC 1 8 VCC U/D 2 7 CS RH 3 6 RL VSS 4 5 RW Pin Descriptions SOIC SYMBOL 1 INC Increment. Toggling INC while CS is low moves the wiper either up or down. 2 U/D Up/Down. The U/D input controls the direction of the wiper movement. 3 RH The high terminal is equivalent to one of the fixed terminals of a mechanical potentiometer. 4 VSS Ground. 5 R The wiper terminal is equivalent to the movable terminal of a mechanical potentiometer. 6 RL The low terminal is equivalent to one of the fixed terminals of a mechanical potentiometer. 7 CS Chip Select. The device is selected when the CS input is LOW, and deselected when CS is high. 8 VCC Supply Voltage. W FN8185 Rev 3.00 July 31, 2014 BRIEF DESCRIPTION Page 2 of 8 X9319 Absolute Maximum Ratings Thermal Information Voltage on CS, INC, U/D and VCC with respect to VSS . . . . -1V to +7V RH, RW, RL to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+12V IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA Junction Temperature under bias . . . . . . . . . . . . . . . .-65°C to +135°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. Potentiometer Characteristics VCC = 5V ±10%. Boldface limits apply across the operating temperature range, -40°C to +85°C (Industrial) and 0°C to +70°C (Commercial). SYMBOL VRH/RL PARAMETER TEST CONDITIONS MIN TYP MAX (Note 7) (Note 8) (Note 7) End-to-end resistance tolerance See ordering information for values -20 +20 % RH/RL terminal voltage VSS = 0V VSS 10 V 25 mW 200 W +3.0 mA Power rating RW Wiper resistance IW = 1mA IW Wiper current (Note 9) See test circuit Noise (Note 11) Ref: 1kHz 40 -3.0 Resolution Absolute linearity (Note 4) V(RH) = 10V, V(RL) = 0V Relative linearity (Note 5) VCC dBV 1 % +1 MI (Note 6) -0.2 +0.2 MI (Note 6) ±300 Ratiometric temperature coefficient (Notes 9, 10) Potentiometer capacitances -120 -1 RTOTAL temperature coefficient (Note 9) CH/CL/CW (Note 9) UNIT ppm/°C -20 +20 See “Equivalent Circuit” on page 4 Supply Voltage ppm/°C 10/10/25 pF 4.5 5.5 V D.C. Operating Characteristics VCC = 5V ±10%. Boldface limits apply across the operating temperature range, -40°C to +85°C (Industrial) and 0°C to +70°C (Commercial). SYMBOL PARAMETER TEST CONDITIONS MIN (Note 7) TYP (Note 8) MAX (Note 7) UNIT ICC VCC active current (Increment) CS = VIL, U/D = VIL or VIH and INC = 0.4V/2.4V at min. tCYC RL, RH, RW not connected 1 3 mA ISB Standby supply current CS  2.4V, U/D and INC = 0.4V RL, RH, RW not connected 300 1000 µA ILI CS, INC, U/D input leakage current VIN = VSS to VCC -10 +10 µA VIH CS, INC, U/D input HIGH voltage 2 VCC + 1 V VIL CS, INC, U/D input LOW voltage -1 0.8 V CIN (Note 9) CS, INC, U/D input capacitance 10 pF VCC = 5V, VIN = VSS, TA = +25°C, f = 1MHz Endurance and Data Retention VCC = 5V ±10%, TA = Full Operating Temperature Range PARAMETER MIN UNIT Minimum endurance 100,000 Data changes per bit Data retention 100 Years FN8185 Rev 3.00 July 31, 2014 Page 3 of 8 X9319 Test Circuit AC Conditions of Test Equivalent Circuit TEST POINT RTOTAL RH CW CH RW FORCE CURRENT CL RL 10pF Input pulse levels 0.8V to 2V Input rise and fall times 10ns Input reference levels 1.4V 25pF 10pF RW A.C. Operating Characteristics VCC = 5V ±10%. Boldface limits apply across the operating temperature range, -40°C to +85°C (Industrial) and 0°C to +70°C (Commercial). SYMBOL tCl PARAMETER MIN (Note 7) CS to INC setup 100 TYP (Note 8) MAX (Note 7) UNIT ns tlD (Note 9) INC HIGH to U/D change 100 ns tDI (Note 9) U/D to INC setup 1 µs tlL INC LOW period 1 µs tlH INC HIGH period 1 µs tlC INC inactive to CS inactive 1 µs tCPHS CS deselect time (STORE) 20 ms CS deselect time (NO STORE) 1 µs tCPHNS (Note 9) tIW (Note 9) INC to RW change tCYC tR, tF (Note 9) INC cycle time 100 INC input rise and fall time VCC power-up rate µs 4 µs 500 tPU (Note 9) Power-up to wiper stable tR VCC (Note 9) 500 0.2 µs 500 µs 50 V/ms NOTES: 4. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = [V(RW(n)(actual)) - V(RW(n)(expected))]/MI V(RW(n)(expected)) = n(V(RH) - V(RL))/99 + V(RL), with n from 0 to 99. 5. Relative linearity is a measure of the error in step size between taps = [V(RW(n+1)) - (V(RW(n)) - MI)]/MI. 6. 1 Ml = Minimum Increment = [V(RH) - V(RL)]/99. 7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 8. Typical values are for TA = +25°C and nominal supply voltage. 9. Guaranteed by device characterization. 10. Ratiometric temperature coefficient = (V(RW)T1(n) - V(RW)T2(n))/[V(RW)T1(n)(T1 - T2) x 106], with T1 and T2 being 2 temperatures, and n from 0 to 99. 11. Measured with wiper at tap position 31, RL grounded, using test circuit. Power-Up and Down Requirements In order to prevent unwanted tap position changes, or an inadvertent store, bring the CS and INC high before or concurrently with the VCC pin on power-up. The potentiometer voltages must be applied after this sequence is completed. During power-up, the data sheet parameters for the DCP do FN8185 Rev 3.00 July 31, 2014 not fully apply until 1 millisecond after VCC reaches its final value. The VCC ramp spec is always in effect. Page 4 of 8 X9319 A.C. Timing CS tCYC tCI tIL tIC tIH tCPHNS tCPHS 90% 90% 10% INC tID tDI tF tR U/D tIW RW MI (3) Pin Descriptions RH and RL The high (RH) and low (RL) terminals of the X9319 are equivalent to the fixed terminals of a mechanical potentiometer. The terminology of RL and RH references the relative position of the terminal in relation to wiper movement direction selected by the U/D input and not the voltage potential on the terminal. RW RW is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the control inputs. The wiper terminal series resistance is typically 40Ω. Up/Down (U/D) The U/D input controls the direction of the wiper movement and whether the counter is incremented or decremented. Increment (INC) The INC input is negative-edge triggered. Toggling INC will move the wiper and either increment or decrement the counter in the direction indicated by the logic level on the U/D input. Chip Select (CS) The device is selected when the CS input is LOW. The current counter value is stored in nonvolatile memory when CS is returned HIGH while the INC input is also HIGH. After the store operation is complete the X9319 will be placed in the low power standby mode until the device is selected once again. Principles of Operation There are three sections of the X9319: the control section, the nonvolatile memory, and the resistor array. The control section operates just like an up/down counter. The output of this counter is decoded to turn on a single electronic switch connecting a point on the resistor array to the wiper output. FN8185 Rev 3.00 July 31, 2014 The contents of the counter can be stored in nonvolatile memory and retained for future use. The resistor array is comprised of 99 individual resistors connected in series. Electronic switches at either end of the array and between each resistor provide an electrical connection to the wiper pin, RW. The wiper acts like its mechanical equivalent and does not move beyond the first or last position. That is, the counter does not wrap around when clocked to either extreme. The electronic switches on the device operate in a “make-before-break” mode when the wiper changes tap positions. If the wiper is moved several positions, multiple taps are connected to the wiper for tIW (INC to VW change). The RTOTAL value for the device can temporarily be reduced by a significant amount if the wiper is moved several positions. When the device is powered down, the last wiper position stored will be maintained in the nonvolatile memory. When power is restored, the contents of the memory are recalled and the wiper is set to the value last stored. Instructions and Programming The INC, U/D and CS inputs control the movement of the wiper along the resistor array. With CS set LOW, the device is selected and enabled to respond to the U/D and INC inputs. HIGH-to-LOW transitions on INC will increment or decrement (depending on the state of the U/D input) the seven bit counter. The output of this counter is decoded to select one of one hundred wiper positions along the resistive array. The value of the counter is stored in nonvolatile memory whenever CS transitions HIGH while the INC input is also HIGH. The system may select the X9319, move the wiper and deselect the device without having to store the latest wiper position in nonvolatile memory. After the wiper movement is Page 5 of 8 X9319 performed as described above and once the new position is reached, the system must keep INC LOW while taking CS HIGH. The new wiper position will be maintained until changed by the system or until a power-up/down cycle recalled the previously stored data. This procedure allows the system to always power-up to a preset value stored in nonvolatile memory; then during system operation minor adjustments could be made. The adjustments might be based on user preference, system parameter changes due to temperature drift, etc. The state of U/D may be changed while CS remains LOW. This allows the host system to enable the device and then move the wiper up and down until the proper trim is attained. INC CS (Continued) INC U/D H X Store wiper position to nonvolatile memory X X Standby L X No store, return to standby L H Wiper Up (not recommended) L L Wiper Down (not recommended) H MODE Applications Information Electronic digitally controlled (XDCP) potentiometers provide three powerful application advantages: Mode Selection CS Mode Selection U/D MODE 1. The variability and reliability of a solid-state potentiometer L H Wiper up 2. The flexibility of computer-based digital controls L L Wiper down 3. The retentivity of nonvolatile memory used for the storage of multiple potentiometer settings or data. Basic Configurations of Electronic Potentiometers VREF VREF RH RW RL I FIGURE 2. TWO TERMINAL VARIABLE RESISTOR; VARIABLE CURRENT FIGURE 1. THREE TERMINAL POTENTIOMETER; VARIABLE VOLTAGE DIVIDER Basic Circuits +V +V R1 R1 VS +V +5V VREF RW + X RW LMC7101 - VOUT VOUT = VW/RW FIGURE 3. BUFFERED REFERENCE VOLTAGE - 100k +V (a) (b) FIGURE 4. CASCADING TECHNIQUES VO + +10V RW FN8185 Rev 3.00 July 31, 2014 +8V R2 LMC7101 100k VO = (R2/R1)VS FIGURE 5. SINGLE SUPPLY INVERTING AMPLIFIER Page 6 of 8 X9319 Basic Circuits (Continued) R1 R2 VS VIN VO (REG) 317 +12V 100kΩ VS LT311A - - R1 + Iadj 10kΩ +15V VO (REG) = 1.25V (1+R2/R1)+Iadj R2 FIGURE 6. VOLTAGE REGULATOR FIGURE 7. OFFSET VOLTAGE ADJUSTMENT } 10kΩ } LMC7101 10kΩ R2 VO + VO R1 R2 VUL = {R1/(R1+R2)} VO(max) VLL = {R1/(R1+R2)} VO(min) FIGURE 8. COMPARATOR WITH HYSTERESIS © Copyright Intersil Americas LLC 2005-2014. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8185 Rev 3.00 July 31, 2014 Page 7 of 8 X9319 Package Outline Drawing M8.15E 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 0, 08/09 4 4.90 ± 0.10 A DETAIL "A" 0.22 ± 0.03 B 6.0 ± 0.20 3.90 ± 0.10 4 PIN NO.1 ID MARK 5 (0.35) x 45° 4° ± 4° 0.43 ± 0.076 1.27 0.25 M C A B SIDE VIEW “B” TOP VIEW 1.75 MAX 1.45 ± 0.1 0.25 GAUGE PLANE C SEATING PLANE 0.10 C 0.175 ± 0.075 SIDE VIEW “A 0.63 ±0.23 DETAIL "A" (1.27) (0.60) NOTES: (1.50) (5.40) 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side. 5. The pin #1 identifier may be either a mold or mark feature. 6. Reference to JEDEC MS-012. TYPICAL RECOMMENDED LAND PATTERN FN8185 Rev 3.00 July 31, 2014 Page 8 of 8