X9401WS24

APPLICATION NOTES A V A I L A B L E AN99 • AN115 • AN120 • AN124 • AN133 • AN134 Low Noise/Low Power/SPI Bus X9401 Preliminary Information Quad, 64 Tap, Digitally Controlled Potentiometer (XDCP™) FEATURES DESCRIPTION • • • • • • • • • • • The X9401 integrates 4 digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated microcircuit. Quad–4 separate pots, 64 taps/pot Nonvolatile storage of wiper position Four Nonvolatile Data Registers for Each Pot 16-bytes of EEPROM memory SPI serial interface RTotal = 10kΩ Wiper resistance = 150Ω typical Standby current < 1µA (total package) Operating current < 400µA max. VCC = 2.7V to 5V Packages–24-lead TSSOP, SOIC, CSP (Chip Scale Package) • 100 year data retention The digitally controlled potentiometer is implemented using 64 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the SPI bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and 4 nonvolatile Data Registers (DR0:DR3) that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array through the switches. Power up recalls the contents of DR0 to the WCR. The XDCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. BLOCK DIAGRAM Pot 0 VCC VSS R0 R1 R2 R3 HOLD CS SCK SO SI A0 A1 Interface and Control Circuitry WP VL0/RL0 R0 R1 R2 R3 Wiper Counter Register (WCR) Resistor Array Pot 2 VH2/RH2 VL2/RL2 VW0/RW0 VW2/RW2 VW1/RW1 VW3/RW3 8 Data R0 R1 R2 R3 REV 1.9 4/13/04 VH0/RH0 Wiper Counter Register (WCR) Wiper Counter Register (WCR) Resistor Array Pot 1 VH1/RH1 VL1/RL1 www.xicor.com R0 R1 R2 R3 Wiper Counter Register (WCR) Resistor Array Pot 3 VH3/RH3 VL3/RL3 Characteristics subject to change without notice. 1 of 21 X9401 – Preliminary Information PIN DESCRIPTIONS Hold (HOLD) HOLD is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LOW while SCK is LOW. To resume communication, HOLD is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times. Host Interface Pins Serial Output (SO) SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. Serial Input SI is the serial data input pin. All opcodes, byte addresses and data to be written to the pots and pot registers are input on this pin. Data is latched by the rising edge of the serial clock. Device Address (A0–A1) The address inputs are used to set the least significant 2 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the address input in order to initiate communication with the X9401. A maximum of 4 devices may occupy the SPI serial bus. Serial Clock (SCK) The SCK input is used to clock data into and out of the X9401. Potentiometer Pins VH (VH0–VH3), VL (VL0–VL3), RH (RH0–RH3), RL (RL0–RL3) The VH/RH and VL/RL inputs are equivalent to the terminal connections on either end of a mechanical potentiometer. Chip Select (CS) When CS is HIGH, the X9401 is deselected and the SO pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. CS LOW enables the X9401, placing it in the active power mode. It should be noted that after a power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. VW (VW0–VW3), RW (RW0–RW3) The wiper outputs are equivalent to the wiper output of a mechanical potentiometer. Hardware Write Protect Input (WP) The WP pin when LOW prevents nonvolatile writes to the Wiper Counter Registers. PIN CONFIGURATION SOIC VCC 1 CSP 24 NC VL0/RL0 2 23 VL3/RL3 VH0/RH0 3 22 VH3/RH3 VW0/RW0 4 21 VW3/RW3 CS 5 20 A0 WP 6 19 SO X9401 SI 7 18 HOLD A1 8 17 SCK VL1/RL1 9 16 VL2/RL2 15 VH2/RH2 11 14 VW2/RW2 12 13 NC VH1/RH1 10 VW1/RW1 V SS REV 1.9 4/13/04 1 A B C D E F VW0/RW0 VL0/RL0 TSSOP 2 3 CS A1 WP SI VH0/RH0 VH1/RH1 VCC VH3/RH3 VH2/RH2 NC VL3/RL3 VW3/RW3 SO A0 4 VL1/RL1 VW1/RW1 VSS NC HOLD VW2/RW2 SCK VL2/RL2 Top View–Bumps Down www.xicor.com SI 1 24 WP A1 2 23 VL1/RL1 VH1/RH1 3 22 CS VW0/RW0 4 21 VH0/RH0 VW1/RW1 5 20 VL0/RL0 VSS 6 19 VCC X9401 NC 7 18 NC VW2/RW2 8 17 VL3/RL3 VH2/RH2 9 16 VH3/RH3 VL2/RL2 10 15 VW3/RW3 SCK 11 14 A0 HOLD 12 13 SO Characteristics subject to change without notice. 2 of 21 X9401 – Preliminary Information These switches are controlled by a Wiper Counter Register (WCR). The six bits of the WCR are decoded to select, and enable, one of sixty-four switches. PIN NAMES Symbol Description SCK Serial Clock SI, SO Serial Data A0-A1 Device Address VH0/RH0–VH3/RH3, VL0/RL0–VL3/RL3 Potentiometers (terminal equivalent) VW0/RW0–VW1/RW1 Potentiometers (wiper equivalent) WP Hardware Write Protection VCC System Supply Voltage VSS System Ground NC No Connection DEVICE DESCRIPTION The X9401 is a highly integrated microcircuit incorporating four resistor arrays and their associated registers and counters and the serial interface logic providing direct communication between the host and the XDCP potentiometers. Serial Interface The X9401 supports the SPI interface hardware conventions. The device is accessed via the SI input with data clocked in on the rising SCK. CS must be LOW and the HOLD and WP pins must be HIGH during the entire operation. The SO and SI pins can be connected together, since they have three state outputs. This can help to reduce system pin count. Array Description The X9401 is comprised of four resistor arrays. Each array contains 63 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (VH/RH and VL/RL inputs). At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (VW/RW) output. Within each individual array only one switch may be turned on at a time. REV 1.9 4/13/04 Wiper Counter Register (WCR) The X9401 contains four Wiper Counter Registers, one for each XDCP potentiometer. The WCR is equivalent to a serial-in, parallel-out register/counter with its outputs decoded to select one of sixty-four switches along its resistor array. The contents of the WCR can be altered in four ways: it may be written directly by the host via the Write Wiper Counter Register instruction (serial load); it may be written indirectly by transferring the contents of one of four associated data registers via the XFR Data Register or Global XFR Data Register instructions (parallel load); it can be modified one step at a time by the Increment/Decrement instruction. Finally, it is loaded with the contents of its data register zero (R0) upon power-up. The Wiper Counter Register is a volatile register; that is, its contents are lost when the X9401 is powereddown. Although the register is automatically loaded with the value in R0 upon power-up, this may be different from the value present at power-down. The wiper position must be stored in R0 to insure restoring the wiper position after power-up. Data Registers Each potentiometer has four 6-bit nonvolatile data registers. These can be read or written directly by the host. Data can also be transferred between any of the four data registers and the associated Wiper Counter Register. All operations changing data in one of the data registers is a nonvolatile operation and will take a maximum of 10ms. If the application does not require storage of multiple settings for the potentiometer, the data registers can be used as memory locations for system parameters or user preference data. Data Register Detail (MSB) (LSB) D5 D4 D3 D2 D1 D0 NV NV NV NV NV NV www.xicor.com Characteristics subject to change without notice. 3 of 21 X9401 – Preliminary Information Detailed Potentiometer Block Diagram (One of Four Arrays) Serial Data Path Serial Bus Input From Interface Circuitry Register 0 6 Parallel Bus Input Wiper Counter Register (WCR) Register 3 D e c o d e INC/DEC Logic If WCR = 00[H] then VW/RW = VL/RL If WCR = 3F[H] then VW/RW = VH/RH C o u n t e r Register 1 8 Register 2 VH/RH UP/DN Modified SCL UP/DN VL/RL CLK VW/RW Write in Process The contents of the Data Registers are saved to nonvolatile memory when the CS pin goes from LOW to HIGH after a complete write sequence is received by the device. The progress of this internal write operation can be monitored by a Write In Process bit (WIP). The WIP bit is read with a Read Status command. continue the command sequence. The A0–A1 inputs can be actively driven by CMOS input signals or tied to VCC or VSS. The remaining two bits in the slave byte must be set to 0. Figure 1. Identification Byte Format Device Type Identifier INSTRUCTIONS Identification (ID) Byte The first byte sent to the X9401 from the host, following a CS going HIGH to LOW, is called the Identification byte. The most significant four bits of the slave address are a device type identifier, for the X9401 this is fixed as 0101[B] (refer to Figure 1). The two least significant bits in the ID byte select one of four devices on the bus. The physical device address is defined by the state of the A0-A1 input pins. The X9401 compares the serial data stream with the address input state; a successful compare of both address bits is required for the X9401 to successfully REV 1.9 4/13/04 0 1 0 1 0 0 A1 A0 Device Address Instruction Byte The next byte sent to the X9401 contains the instruction and register pointer information. The four most significant bits are the instruction. The next four bits point to one of the four pots and, when applicable, they point to one of four associated registers. The format is shown below in Figure 2. www.xicor.com Characteristics subject to change without notice. 4 of 21 X9401 – Preliminary Information Five instructions require a three-byte sequence to complete. These instructions transfer data between the host and the X9401; either between the host and one of the data registers or directly between the host and the Wiper Counter Register. These instructions are: Figure 2. Instruction Byte Format Register Select I3 I2 I1 Instructions I0 R1 R0 P1 P0 – Read Wiper Counter Register— read the current wiper position of the selected pot, Pot Select The four high order bits of the instruction byte specify the operation. The next two bits (R1 and R0) select one of the four registers that is to be acted upon when a register oriented instruction is issued. The last two bits (P1 and P0) selects which one of the four potentiometers is to be affected by the instruction. Four of the ten instructions are two bytes in length and end with the transmission of the instruction byte. These instructions are: – XFR Data Register to Wiper Counter Register—This transfers the contents of one specified Data Register to the associated Wiper Counter Register. – XFR Wiper Counter Register to Data Register—This transfers the contents of the specified Wiper Counter Register to the specified associated Data Register. – Global XFR Data Register to Wiper Counter Register — This transfers the contents of all specified Data Registers to the associated Wiper Counter Registers. – Global XFR Wiper Counter Register to Data Register— This transfers the contents of all Wiper Counter Registers to the specified associated Data Registers. – Write Wiper Counter Register—change current wiper position of the selected pot, – Read Data Register—read the contents of the selected data register; – Write Data Register—write a new value to the selected data register. – Read Status—This command returns the contents of the WIP bit which indicates if the internal write cycle is in progress. The sequence of these operations is shown in Figure 4 and Figure 5. The final command is Increment/Decrement. It is different from the other commands, because it’s length is indeterminate. Once the command is issued, the master can clock the selected wiper up and/or down in one resistor segment steps; thereby, providing a fine tuning capability to the host. For each SCK clock pulse (tHIGH) while SI is HIGH, the selected wiper will move one resistor segment towards the VH/RH terminal. Similarly, for each SCK clock pulse while SI is LOW, the selected wiper will move one resistor segment towards the VL/RL terminal. A detailed illustration of the sequence and timing for this operation are shown in Figure 6 and Figure 7. The basic sequence of the two byte instructions is illustrated in Figure 3. These two-byte instructions exchange data between the WCR and one of the data registers. A transfer from a data register to a WCR is essentially a write to a static RAM, with the static RAM controlling the wiper position. The response of the wiper to this action will be delayed by tWRL. A transfer from the WCR (current wiper position), to a data register is a write to nonvolatile memory and takes a minimum of tWR to complete. The transfer can occur between one of the four potentiometers and one of its associated registers; or it may occur globally, where the transfer occurs between all potentiometers and one associated register. REV 1.9 4/13/04 www.xicor.com Characteristics subject to change without notice. 5 of 21 X9401 – Preliminary Information Figure 3. Two-Byte Command Sequence CS SCK SI 0 1 0 1 0 0 A1 A0 I3 I2 I1 I0 R1 R0 P1 P0 Figure 4. Three-Byte Command Sequence (Write) CS SCL SI 0 1 0 0 1 0 A1 A0 I3 I2 I1 I0 R1 R0 P1 P0 0 0 D5 D4 D3 D2 D1 D0 Figure 5. Three-Byte Command Sequence (Read) CS SCL SI Don’t Care 0 1 0 0 1 0 A1 A0 I3 I2 I1 I0 R1 R0 P1 P0 S0 0 0 D5 D4 D3 D2 D1 D0 Figure 6. Increment/Decrement Command Sequence CS SCK SI 0 REV 1.9 4/13/04 1 0 1 0 0 A1 A0 I3 I2 I1 I0 0 www.xicor.com 0 P1 P0 I N C 1 I N C 2 I N C n D E C 1 Characteristics subject to change without notice. D E C n 6 of 21 X9401 – Preliminary Information Figure 7. Increment/Decrement Timing Limits tWRID SCK SI Voltage Out VW/RW INC/DEC CMD Issued Table 1. Instruction Set Instruction I3 I2 Instruction Set I1 I0 R1 R0 P1 P0 Read Wiper Counter Register 1 0 0 1 0 0 Write Wiper Counter Register 1 0 1 0 0 0 Read Data Register 1 0 1 1 R1 R0 Write Data Register 1 1 0 0 R1 R0 XFR Data Register to Wiper Counter Register 1 1 0 1 R1 R0 XFR Wiper Counter Register to Data Register 1 1 1 0 R1 R0 Global XFR Data Register to Wiper Counter Register 0 0 0 1 R1 R0 Global XFR Wiper Counter Register to Data Register 1 0 0 0 R1 R0 Increment/Decrement Wiper Counter Register Read Status (WIP bit) 0 0 1 0 0 0 0 1 0 1 0 0 REV 1.9 4/13/04 Operation P1 P0 Read the contents of the Wiper Counter Register pointed to by P1-P0 P1 P0 Write new value to the Wiper Counter Register pointed to by P1-P0 P1 P0 Read the contents of the Data Register pointed to by P1-P0 and R1–R0 P1 P0 Write new value to the Data Register pointed to by P1-P0 and R1–R0 P1 P0 Transfer the contents of the Data Register pointed to by R1–R0 to the Wiper Counter Register pointed to by P1-P0 P1 P0 Transfer the contents of the Wiper Counter Register pointed to by P1-P0 to the Register pointed to by R1–R0 0 0 Transfer the contents of the Data Registers pointed to by R1–R0 of all four pots to their respective Wiper Counter Register 0 0 Transfer the contents of all Wiper Counter Registers to their respective data Registers pointed to by R1–R0 of all four pots P1 P0 Enable Increment/decrement of the Wiper Counter Register pointed to by P1-P0 0 1 Read the status of the internal write cycle, by checking the WIP bit. www.xicor.com Characteristics subject to change without notice. 7 of 21 X9401 – Preliminary Information Instruction Format Notes: (1) (2) (3) (4) “A1 ~ A0”: stands for the device addresses sent by the master. WPx refers to wiper position data in the Counter Register “I”: stands for the increment operation, SI held HIGH during active SCK phase (high). “D”: stands for the decrement operation, SI held LOW during active SCK phase (high). Read Wiper Counter Register (WCR) device type identifier device addresses instruction opcode CS Falling Edge 0 1 0 1 0 0 A A 1 1 0 0 0 WCR addresses 1 0 wiper position (sent by X9401 on SO) CS W W W W W W Rising P P 0 0 0 P P P P P P Edge 1 0 5 4 3 2 1 0 Write Wiper Counter Register (WCR) device type identifier device addresses instruction opcode CS Falling Edge 0 1 0 1 0 0 A A 1 1 0 0 1 WCR addresses 0 0 Data Byte (sent by Host on SI) CS W W W W W W Rising P P 0 0 0 P P P P P P Edge 1 0 5 4 3 2 1 0 Read Data Register (DR) device type identifier device addresses instruction opcode DR and WCR addresses CS Falling Edge 0 1 0 1 0 0 A A 1 0 1 1 R R P 1 0 1 0 1 Data Byte (sent by X9401 on SO) CS W W W W W W Rising P 0 0 P P P P P P Edge 0 5 4 3 2 1 0 Write Data Register (DR) device type device identifier addresses instruction opcode DR and WCR addresses CS Falling Edge 0 1 0 1 0 0 A A 1 1 0 0 R 1 0 1 R 0 P 1 Data Byte (sent by host on SI) CS W W W W W W Rising P 0 0 P P P P P P Edge 0 5 4 3 2 1 0 HIGH-VOLTAGE WRITE CYCLE Transfer Data Register (DR) to Wiper Counter Register (WCR) device type device instruction DR and WCR CS CS identifier addresses opcode addresses Falling Rising Edge 0 1 0 1 0 0 A A 1 1 0 1 R R P P Edge 1 0 1 0 1 0 REV 1.9 4/13/04 www.xicor.com Characteristics subject to change without notice. 8 of 21 X9401 – Preliminary Information Transfer Wiper Counter Register (WCR) to Data Register (DR) device type device instruction DR and WCR CS CS identifier addresses opcode addresses Falling Rising Edge 0 1 0 1 0 0 A A 1 1 1 0 R R P P Edge 1 0 1 0 1 0 HIGH-VOLTAGE WRITE CYCLE Increment/Decrement Wiper Counter Register (WCR) device type device instruction WCR increment/decrement CS CS identifier addresses opcode addresses (sent by master on SDA) Falling Rising Edge 0 1 0 1 0 0 A A 0 0 1 0 X X P P I/ I/ . . . . I/ I/ Edge 1 0 1 0 D D D D Global Transfer Data Register (DR) to Wiper Counter Register (WCR) device type device instruction DR CS CS identifier addresses opcode addresses Falling Rising Edge 0 1 0 1 0 0 A A 0 0 0 1 R R 0 0 Edge 1 0 1 0 Global Transfer Wiper Counter Register (WCR) to Data Register (DR) device type device instruction DR CS CS identifier addresses opcode addresses Falling Rising Edge 0 1 0 1 0 0 A A 1 0 0 0 R R 0 0 Edge 1 0 1 0 HIGH-VOLTAGE WRITE CYCLE Read Status device type device instruction wiper Data Byte identifier addresses opcode addresses (sent by X9401 on SO) CS CS Falling Rising W Edge 0 1 0 1 0 0 A A 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 I Edge 1 0 P REV 1.9 4/13/04 www.xicor.com Characteristics subject to change without notice. 9 of 21 X9401 – Preliminary Information ABSOLUTE MAXIMUM RATINGS COMMENT Temperature under bias.................... –65°C to +135°C Storage temperature......................... –65°C to +150°C Voltage on SCK, SCL or any address input with respect to VSS ........................ –1V to +7V ∆V = |(VH–VL)| ......................................................5.5V Lead temperature (soldering, 10 seconds) ........ 300°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Min. Device Max. Supply Voltage (VCC) Limits Commercial 0°C +70°C X9401 5V ±10% Industrial –40°C +85°C X9401-2.7 2.7V to 5.5V ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.) Limits Symbol RTOTAL Parameter End to end resistance Min. Typ. –20 Power rating IW Wiper current RW Wiper resistance VTERM –6 150 Voltage on any VH or VL Pin VSS Noise Resolution Absolute linearity Relative (1) linearity (2) Temperature coefficient of RTOTAL Max. Unit +20 % 50 mW +6 mA 500 Ω VCC Test Condition 25°C, each pot Wiper Current = ± 3mA V VSS = 0V -120 dBV Ref: 1kHz 1.6 % –1 –0.2 +1 MI(3) Vw(n)(actual)—Vw(n)(expected) +0.2 MI(3) Vw(n + 1)—[Vw(n) + MI] ±300 Ratiometric temp. coefficient ppm/°C ±20 CH/CL/CW Potentiometer capacitances 10/10/25 IAL RH, RL, RW leakage current 0.1 10 ppm/°C pF See Macro model µA VIN = VSS to VCC. Device is in stand-by mode. POWER UP AND DOWN REQUIREMENTS The are no restrictions on the power-up or power-down conditions of VCC and the voltages applied to the potentiometer pins provided that VCC is always more positive than or equal to VH, VL, and VW, i.e., VCC ≥ VH, VL, VW. The VCC power-up spec is always in effect. Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. (2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. (3) MI = RTOT/63 or (VH–VL)/63, single pot REV 1.9 4/13/04 www.xicor.com Characteristics subject to change without notice. 10 of 21 X9401 – Preliminary Information D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Limits Symbol Parameter Min. Typ. Max. Unit Test Conditions 400 µA fSCK = 2MHz, SO = Open, Other Inputs = VSS ICC1 VCC supply current (active) ICC2 VCC supply current (nonvolatile write) 1 mA fSCK = 2MHz, SO = Open, Other Inputs = VSS ISB VCC current (standby) 1 µA SCK = SI = VSS, Addr. = VSS, CS = VCC ILI Input leakage current 10 µA VIN = VSS to VCC ILO Output leakage current 10 µA VOUT = VSS to VCC VIH Input HIGH voltage VCC x 0.7 VCC + 0.5 V VIL Input LOW voltage –0.5 VCC x 0.1 V VOL Output LOW voltage 0.4 V IOL = 3mA ENDURANCE AND DATA RETENTION Parameter Min. Unit Minimum endurance 100,000 Data changes per bit per register Data retention 100 years CAPACITANCE Symbol (4) COUT (4) CIN Test Max. Unit Test Condition Output capacitance (SO) 8 pF VOUT = 0V Input capacitance (A0, A1, SI, and SCK) 6 pF VIN = 0V POWER-UP TIMING Symbol (6) tr VCC Parameter VCC Power-up rate Min. Max. Unit 0.2 50 V/ms (5) tPUR Power-up to initiation of read operation 1 ms tPUW(5) Power-up to initiation of write operation 5 ms A.C. TEST CONDITIONS EQUIVALENT A.C. LOAD CIRCUIT Input pulse levels VCC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level VCC x 0.5 1533Ω Notes: (4) This parameter is periodically sampled and not 100% tested (5) tPUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued. These parameters are periodically sampled and not 100% tested. (6) This is not a tested or guaranteed parameter and should be used only as a guideline. REV 1.9 4/13/04 SPICE Macro Model 5V SDA Output www.xicor.com RTOTAL RH CW CL 100pF RL CL 10pF 25pF 10pF RW Characteristics subject to change without notice. 11 of 21 X9401 – Preliminary Information AC TIMING Symbol Parameter Min. Max. Unit 2.0 MHz fSCK SSI/SPI clock frequency tCYC SSI/SPI clock cycle rime 500 ns tWH SSI/SPI clock high rime 200 ns tWL SSI/SPI clock low time 200 ns tLEAD Lead time 250 ns tLAG Lag time 250 ns tSU SI, SCK, HOLD and CS input setup time 50 ns tH SI, SCK, HOLD and CS input hold time 50 ns tRI SI, SCK, HOLD and CS input rise time 2 µs tFI SI, SCK, HOLD and CS input fall time 2 µs 500 ns 100 ns SO output disable time tDIS tV SO output valid time tHO SO output hold time tRO SO output rise time tFO SO output fall time 0 0 ns 50 ns 50 ns tHOLD HOLD time 400 ns tHSU HOLD setup time 100 ns tHH HOLD hold time 100 ns tHZ HOLD low to output in high Z 100 ns tLZ HOLD high to output in low Z 100 ns TI Noise suppression time constant at SI, SCK, HOLD and CS inputs 20 ns CS deselect time 2 µs tWPASU WP, A0 and A1 setup time 0 ns tWPAH WP, A0 and A1 hold time 0 ns tCS HIGH-VOLTAGE WRITE CYCLE TIMING Symbol Parameter tWR High-voltage write cycle time (store instructions) Typ. Max. Unit 5 10 ms XDCP TIMING Symbol Max. Unit Wiper response time after the third (last) power supply is stable 10 µs tWRL Wiper response time after instruction issued (all load instructions) 10 µs tWRID Wiper response time from an active SCL/SCK edge (increment/decrement instruction) 450 ns tWRPO Parameter REV 1.9 4/13/04 www.xicor.com Min. Characteristics subject to change without notice. 12 of 21 X9401 – Preliminary Information SYMBOL TABLE WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from Low to High Will change from Low to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed N/A Changing: State Not Known Center Line is High Impedance TIMING DIAGRAMS Input Timing tCS CS tLAG tCYC tLEAD SCK ... tSU tH tWL ... MSB SI tRI tFI tWH LSB High Impedance SO Output Timing CS SCK ... tV REV 1.9 4/13/04 tDIS ... MSB SO SI tHO LSB ADDR www.xicor.com Characteristics subject to change without notice. 13 of 21 X9401 – Preliminary Information Hold Timing CS tHSU tHH SCK ... tRO tFO SO tHZ tLZ SI tHOLD HOLD XDCP Timing (for All Load Instructions) CS SCK ... tWRL SI ... MSB LSB VW/RW SO High Impedance XDCP Timing (for Increment/Decrement Instruction) CS SCK ... tWRID ... VW/RW SI SO REV 1.9 4/13/04 ADDR Inc/Dec Inc/Dec ... High Impedance www.xicor.com Characteristics subject to change without notice. 14 of 21 X9401 – Preliminary Information Write Protect and Device Address Pins Timing (Any Instruction) CS tWPASU tWPAH WP A0 A1 APPLICATIONS INFORMATION Basic Configurations of Electronic Potentiometers +VR VR VW/RW I Three terminal Potentiometer; Variable voltage divider REV 1.9 4/13/04 Two terminal Variable Resistor; Variable current www.xicor.com Characteristics subject to change without notice. 15 of 21 X9401 – Preliminary Information Application Circuits Noninverting Amplifier VS Voltage Regulator + VO – VIN VO (REG) 317 R1 R2 Iadj R1 R2 VO = (1+R2/R1)VS VO (REG) = 1.25V (1+R2/R1)+Iadj R2 Offset Voltage Adjustment R1 Comparator with Hysteresis R2 VS VS – VO + 100KΩ – VO + } } TL072 R1 R2 10KΩ VUL = {R1/(R1+R2)} VO(max) VLL = {R1/(R1+R2)} VO(min) 10KΩ 10KΩ +5V Attenuator Filter C VS + R2 R1 VS + R VO R3 R4 R2 All RS = 10kΩ R1 GO = 1 + R2/R1 fc = 1/(2pRC) VO = G VS -1/2 ≤ G ≤ +1/2 REV 1.9 4/13/04 VO – – www.xicor.com Characteristics subject to change without notice. 16 of 21 X9401 – Preliminary Information Application Circuits (continued) R1 R2 } } Inverting Amplifier Equivalent L-R Circuit VS R2 C1 – VS VO + + – R1 ZIN VO = G VS G = - R2/R1 R3 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2 Function Generator C R2 – + R1 – } RA + } RB frequency ∝ R1, R2, C amplitude ∝ RA, RB REV 1.9 4/13/04 www.xicor.com Characteristics subject to change without notice. 17 of 21 X9401 – Preliminary Information PACKAGING INFORMATION 24-Lead Plastic Small Outline Gull Wing Package Type S 0.290 (7.37) 0.393 (10.00) 0.299 (7.60) 0.420 (10.65) Pin 1 Index Pin 1 0.014 (0.35) 0.020 (0.50) 0.598 (15.20) 0.610 (15.49) (4X) 7° 0.092 (2.35) 0.105 (2.65) 0.003 (0.10) 0.012 (0.30) 0.050 (1.27) 0.050" Typical 0.010 (0.25) X 45° 0.020 (0.50) 0.050" Typical 0° – 8° 0.009 (0.22) 0.013 (0.33) 0.420" 0.015 (0.40) 0.050 (1.27) FOOTPRINT 0.030" Typical 24 Places NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) REV 1.9 4/13/04 www.xicor.com Characteristics subject to change without notice. 18 of 21 X9401 – Preliminary Information PACKAGING INFORMATION 24-Lead Plastic, TSSOP Package Type V .026 (.65) BSC .169 (4.3) .252 (6.4) BSC .177 (4.5) .303 (7.70) .311 (7.90) .047 (1.20) .0075 (.19) .0118 (.30) .002 (.06) .005 (.15) .010 (.25) Gage Plane 0°–8° (4.16) (7.72) Seating Plane .020 (.50) .030 (.75) (1.78) Detail A (20X) (0.42) (0.65) .031 (.80) .041 (1.05) ALL MEASUREMENTS ARE TYPICAL See Detail “A” NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) REV 1.9 4/13/04 www.xicor.com Characteristics subject to change without notice. 19 of 21 X9401 – Preliminary Information PACKAGING INFORMATION 24-Bump Chip Scale Package (CSP B24) Package Outline Drawing a 9401WRR YWW I2.7 LOT # f j m d A4 A3 A2 A1 B4 B3 B2 B1 C4 C3 C2 C1 D4 D3 D2 D1 E4 E3 E2 E1 F4 F3 F2 F1 e k l Top View (Sample Marking) b Bottom View (Bumped Side) Side View e c Side View Package Dimensions Ball Matrix: Min Package Width Package Length Package Height Body Thickness Ball Height Ball Diameter Ball Pitch – Width Ball Pitch – Length Ball to Edge Spacing – Width Ball to Edge Spacing – Length REV 1.9 4/13/04 Symbol a b c d e f j k l m 2.595 3.814 0.644 0.444 0.220 0.310 0.538 0.647 Nominal Millimeters 2.625 3.844 0.677 0.457 0.240 0.330 0.5 0.5 0.563 0.672 Max 2.655 3.874 0.710 0.470 0.260 0.350 A B C D E F X9401W/X9401Y 4 3 2 RL1 A1 CS RW1 SI WP VSS RH1 RH0 NC RH2 RH3 RW2 HOLD SO RL2 SCK A0 1 RW0 RL0 VCC NC RL3 RW3 0.588 0.697 www.xicor.com Characteristics subject to change without notice. 20 of 21 X9401 – Preliminary Information ORDERING INFORMATION X9401 Y P T V VCC Limits Blank = 5V ±10% –2.7 = 2.7 to 5.5V Device Temperature Range Blank = Commercial = 0°C to +70°C I = Industrial = –40°C to +85°C Package S24 = 24-Lead SOIC V24 = 24-Lead TSSOP B24 = 24 Lead CSP Potentiometer Organization Pot 0 Pot 1 Pot 2 Pot 3 W= 10KW 10KW 10KW 10KW Y= 2.5KΩ 2.5KΩ 2.5KΩ 2.5KΩ LIMITED WARRANTY ©Xicor, Inc. 2003 Patents Pending Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied. TRADEMARK DISCLAIMER: Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All others belong to their respective owners. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending. LIFE RELATED POLICY In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. Xicor’s products are not authorized for use in critical components in life support devices or systems. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. REV 1.9 4/13/04 www.xicor.com Characteristics subject to change without notice. 21 of 21