X9401WS24T1

DATASHEET X9401 FN8190 Rev 5.00 September 14, 2015 Low Noise/Low Power/SPI Bus Quad, 64 Tap, Digitally Controlled Potentiometer (XDCP™) Description Features The X9401 integrates 4 digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated microcircuit. • Quad - 4 Separate Pots, 64 Taps/Pot The digitally controlled potentiometer is implemented using 64 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the SPI bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and 4 nonvolatile Data Registers (DR0:DR3) that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array through the switches. Power-up recalls the contents of DR0 to the WCR. The XDCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. • Nonvolatile Storage of Wiper Position • Four Nonvolatile Data Registers for Each Pot • 16-bytes of EEPROM Memory • SPI Serial Interface • RTOTAL = 10k • Wiper Resistance = 150 Typical • Standby Current < 3µA (Total Package) • Operating Current < 700µA max. • VCC = 2.7V to 5V • 24 Ld SOIC and 24 Ld TSSOP Package • 100 year Data Retention • Pb-Free Available (RoHS Compliant) Block Diagram POT 0 VCC VSS R0 R2 HOLD R1 R3 VH0/RH0 WIPER COUNTER REGISTER (WCR) VL0/RL0 CS SCK SO SI A0 R0 R2 R1 R3 WIPER COUNTER REGISTER (WCR) RESISTOR ARRAY POT 2 VL2/RL2 VW0/RW0 INTERFACE AND CONTROL CIRCUITRY A1 WP VW2/RW2 8 VW1/RW1 DATA R0 R2 FN8190 Rev 5.00 September 14, 2015 VH2/RH2 R1 R3 WIPER COUNTER REGISTER (WCR) RESISTOR ARRAY POT 1 VH1/RH1 VL1/RL1 VW3/RW3 R0 R2 R1 R3 WIPER COUNTER REGISTER (WCR) RESISTOR ARRAY POT 3 VH3/RH3 VL3/RL3 Page 1 of 20 X9401 Ordering Information VCC LIMITS (V) POTENTIOMETER ORGANIZATION (k) TEMP RANGE (°C) 5 ±10% 10 -40 to +85 24 Ld SOIC (300 mil) (Pb-free) M24.3 X9401WS24Z* (Note 1) (No X9401WS Z longer available, recommended replacement: X9401WS24IZ-2.7T1) -40 to +85 24 Ld SOIC (300 mil) M24.3 X9401WV ZI -40 to +85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044 X9401WV24Z* (Note 1) (No X9401WV Z longer available, recommended replacement: X9401WV24IZ-2.7T1) -40 to +85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044 PART NUMBER X9401WS24IZ* (Note 1) (No longer available, recommended replacement: X9401WS24IZ-2.7T1) X9401WV24IZ* (Note 1) (No longer available, recommended replacement: X9401WV24IZ-2.7T1) X9401WS24IZ-2.7* (Note) PART MARKING X9401WS ZI X9401WS ZG 2.7 to 5.5 PKG. DWG. # PACKAGE -40 to +85 24 Ld SOIC (300 mil) (Pb-free) M24.3 X9401WS24Z-2.7* (Note 1) X9401WS ZF (No longer available, recommended replacement: X9401WS24IZ-2.7T1) -40 to +85 24 Ld SOIC (300 mil) (Pb-free) M24.3 X9401WV24IZ-2.7* (Note 1) X9401WV ZG -40 to +85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044 X9401WV24Z-2.7* (Note 1) X9401WV ZF (No longer available, recommended replacement: X9401WV24IZ-2.7T1) -40 to +85 24 Ld TSSOP (4.4mm) (Pb-free) MDP0044 *Add “T1” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. Not recommended for new designs. Pin Descriptions Host Interface Pins SERIAL OUTPUT (SO) SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock. SERIAL INPUT SI is the serial data input pin. All opcodes, byte addresses and data to be written to the pots and pot registers are input on this pin. Data is latched by the rising edge of the serial clock. FN8190 Rev 5.00 September 14, 2015 SERIAL CLOCK (SCK) The SCK input is used to clock data into and out of the X9401. CHIP SELECT (CS) When CS is HIGH, the X9401 is deselected and the SO pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. CS LOW enables the X9401, placing it in the active power mode. It should be noted that after a power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. Page 2 of 20 X9401 HOLD (HOLD) (24 LD TSSOP) TOP VIEW HOLD is used in conjunction with the CS pin to select the device. Once the part is selected and a serial sequence is underway, HOLD may be used to pause the serial communication with the controller without resetting the serial sequence. To pause, HOLD must be brought LOW while SCK is LOW. To resume communication, HOLD is brought HIGH, again while SCK is LOW. If the pause feature is not used, HOLD should be held HIGH at all times. DEVICE ADDRESS (A0 - A1) 24 WP 23 CS VL1/RL1 3 22 VW0/RW0 VH1/RH1 4 21 VH0/RH0 VW1/RW1 5 20 VL0/RL0 VSS 6 19 VCC NC 7 18 NC VW2/RW2 8 17 VL3/RL3 VH2/RH2 9 16 VH3/RH3 VL2/RL2 10 15 VW3/RW3 The address inputs are used to set the least significant 2 bits of the 8bit slave address. A match in the slave address serial data stream must be made with the address input in order to initiate communication with the X9401. A maximum of 4 devices may occupy the SPI serial bus. Potentiometer Pins SI 1 A1 2 SCK 11 14 A0 HOLD 12 13 S0 Pin Descriptions VH (VH0 - VH3)/ RH (RH0 - RH3), VL (VL0 - VL3)/RL (RL0 - RL3) SOIC TSSOP PIN # PIN # The VH/RH and VL/RL inputs are equivalent to the terminal connections on either end of a mechanical potentiometer. SYMBOL DESCRIPTION 5 23 CS Chip select 17 11 SCK Serial Clock VW (VW0 - VW3)/ RW (RW0 - RW3) 7, 19 1, 13 SI, S0 Serial Data The wiper outputs are equivalent to the wiper output of a mechanical potentiometer. 20, 8 14, 2 A0 - A1 Device Address HARDWARE WRITE PROTECT INPUT (WP) The WP pin when LOW prevents nonvolatile writes to the Wiper Counter Registers. Pinouts X9401 (24 LD SOIC) TOP VIEW 24 NC VCC 1 3, 10, 21, 4, 15, 22, 9, 16, 20, 3, 2, 9, 16, 23 10, 17 4, 11, 14, 21 22, 5, 8, 15 VH0/RH0,VH1/RH1, Potentiometer end VH2/RH2, VH3/RH3, terminals VL0/RL0, VL1/RL1, VL2/RL2, VL3/RL3 VW0/RW0, VW1/RW1, Wipers VW2/RW2, VW3/RW3 6 24 WP 18 12 HOLD Hardware Write Protection Hardware Hold 1 19 VCC System Supply Voltage 12 6 VSS System Ground 13, 24 7, 18 NC No Connection VL0/RL0 2 23 VL3/RL3 VH0/RH0 3 22 VH3/RH3 Device Description VW0/RW0 4 21 VW3/RW3 The X9401 is a highly integrated microcircuit incorporating four resistor arrays and their associated registers and counters and the serial interface logic providing direct communication between the host and the XDCP potentiometers. CS 5 20 A0 WP 6 19 S0 SI 7 18 HOLD A1 8 17 SCK VL1/RL1 9 16 VL2/RL2 VH1/RH1 10 15 VH2/RH2 VW1/RW1 11 14 VW2/RW2 13 NC VSS 12 X9401 Serial Interface The X9401 supports the SPI interface hardware conventions. The device is accessed via the SI input with data clocked in on the rising SCK. CS must be LOW and the HOLD and WP pins must be HIGH during the entire operation. The SO and SI pins can be connected together, since they have three state outputs. This can help to reduce system pin count. Array Description The X9401 is comprised of four resistor arrays. Each array contains 63 discrete resistive segments that are connected in FN8190 Rev 5.00 September 14, 2015 Page 3 of 20 X9401 series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (VH/RH and VL/RL inputs). At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (VW/RW) output. Within each individual array only one switch may be turned on at a time. These switches are controlled by a Wiper Counter Register (WCR). The six bits of the WCR are decoded to select, and enable, one of sixty-four switches. Wiper Counter Register (WCR) The X9401 contains four Wiper Counter Registers, one for each XDCP potentiometer. The WCR is equivalent to a serialin, parallel-out register/counter with its outputs decoded to select one of sixty-four switches along its resistor array. The contents of the WCR can be altered in four ways: it may be written directly by the host via the Write Wiper Counter Register instruction (serial load); it may be written indirectly by transferring the contents of one of four associated data registers via the XFR Data Register or Global XFR Data Register instructions (parallel load); it can be modified one step at a time by the Increment/Decrement instruction. Finally, it is loaded with the contents of its data register zero (R0) upon power-up. The Wiper Counter Register is a volatile register; that is, its contents are lost when the X9401 is powered-down. Although the register is automatically loaded with the value in R0 upon power-up, this may be different from the value present at power-down. The wiper position must be stored in R0 to insure restoring the wiper position after power-up. Data Registers Each potentiometer has four 6-bit nonvolatile data registers. These can be read or written directly by the host. Data can also be transferred between any of the four data registers and the associated Wiper Counter Register. All operations changing data in one of the data registers is a nonvolatile operation and will take a maximum of 10ms. If the application does not require storage of multiple settings for the potentiometer, the data registers can be used as memory locations for system parameters or user preference data. progress of this internal write operation can be monitored by a Write In Process bit (WIP). The WIP bit is read with a Read Status command. Instructions Identification (ID) Byte The first byte sent to the X9401 from the host, following a CS going HIGH to LOW, is called the Identification byte. The most significant four bits of the slave address are a device type identifier. For the X9401 this is fixed as 0101[B] (refer to Figure 1). The two least significant bits in the ID byte select one of four devices on the bus. The physical device address is defined by the state of the A0 - A1 input pins. The X9401 compares the serial data stream with the address input state; a successful compare of both address bits is required for the X9401 to successfully continue the command sequence. The A0 - A1 inputs can be actively driven by CMOS input signals or tied to VCC or VSS. The remaining two bits in the slave byte must be set to 0. DEVICE TYPE IDENTIFIER 0 1 0 1 0 0 A1 A0 DEVICE ADDRESS FIGURE 1. IDENTIFICATION BYTE FORMAT Instruction Byte The next byte sent to the X9401 contains the instruction and register pointer information. The four most significant bits are the instruction. The next four bits point to one of the four pots and, when applicable, they point to one of four associated registers. The format is shown below in Figure 2. I I3 I2 I1 INSTRUCTIONS I0 R1 R0 P1 P0 POT SELECT FIGURE 2. IDENTIFICATION BYTE FORMAT DATA REGISTER DETAIL (MSB) (LSB) D5 D4 D3 D2 D1 D0 NV NV NV NV NV NV Write in Process The four high order bits of the instruction byte specify the operation. The next two bits (R1 and R0) select one of the four registers that is to be acted upon when a register oriented instruction is issued. The last two bits (P1 and P0) selects which one of the four potentiometers is to be affected by the instruction. The contents of the Data Registers are saved to nonvolatile memory when the CS pin goes from LOW to HIGH after a complete write sequence is received by the device. The FN8190 Rev 5.00 September 14, 2015 Page 4 of 20 X9401 Four of the ten instructions are two bytes in length and end with the transmission of the instruction byte. These instructions are: • XFR Data Register to Wiper Counter Register: This transfers the contents of one specified Data Register to the associated Wiper Counter Register. Similarly, for each SCK clock pulse while SI is LOW, the selected wiper will move one resistor segment towards the VL/RL terminal. A detailed illustration of the sequence and timing for this operation are shown in Figure 6 and Figure 7. • XFR Wiper Counter Register to Data Register: This transfers the contents of the specified Wiper Counter Register to the specified associated Data Register. • Global XFR Data Register to Wiper Counter Register: This transfers the contents of all specified Data Registers to the associated Wiper Counter Registers. • Global XFR Wiper Counter Register to Data Register: This transfers the contents of all Wiper Counter Registers to the specified associated Data Registers. The basic sequence of the two byte instructions is illustrated in Figure 3. These two-byte instructions exchange data between the WCR and one of the data registers. A transfer from a data register to a WCR is essentially a write to a static RAM, with the static RAM controlling the wiper position. The response of the wiper to this action will be delayed by tWRL. A transfer from the WCR (current wiper position), to a data register is a write to nonvolatile memory and takes a minimum of tWR to complete. The transfer can occur between one of the four potentiometers and one of its associated registers; or it may occur globally, where the transfer occurs between all potentiometers and one associated register. Five instructions require a three-byte sequence to complete. These instructions transfer data between the host and the X9401; either between the host and one of the data registers or directly between the host and the Wiper Counter Register. These instructions are: • Read Wiper Counter Register: read the current wiper position of the selected pot, • Write Wiper Counter Register: change current wiper position of the selected pot, • Read Data Register: read the contents of the selected data register; • Write Data Register: write a new value to the selected data register. • Read Status: This command returns the contents of the WIP bit which indicates if the internal write cycle is in progress. The sequence of these operations is shown in Figure 4 and Figure 5. The final command is Increment/Decrement. It is different from the other commands, because it’s length is indeterminate. Once the command is issued, the master can clock the selected wiper up and/or down in one resistor segment steps; thereby, providing a fine tuning capability to the host. For each SCK clock pulse (tHIGH) while SI is HIGH, the selected wiper will move one resistor segment towards the VH/RH terminal. FN8190 Rev 5.00 September 14, 2015 Page 5 of 20 X9401 Detailed Potentiometer Block Diagram (ONE OF FOUR ARRAYS) SERIAL DATA PATH SERIAL BUS INPUT FROM INTERFACE CIRCUITRY REGISTER 0 VH/RH C O U N T E R REGISTER 1 8 PARALLEL BUS INPUT 6 REGISTER 2 WIPER COUNTER REGISTER (WCR) REGISTER 3 D E C O D E INC/DEC LOGIC IF WCR = 00[H] THEN VW/RW = VL/RL UP/DN IF WCR = 3F[H] THEN VW/RW = VH/RH UP/DN MODIFIED SCL VL/RL CLK VW/RW CS SCK SI 0 1 0 1 0 0 A1 A0 I3 I2 I1 I0 R1 R0 P1 P0 FIGURE 3. TWO-BYTE COMMAND SEQUENCE CS SCL SI 0 1 0 1 0 0 A1 A0 I3 I2 I1 I0 R1 R0 P1 P0 0 0 D5 D4 D3 D2 D1 D0 FIGURE 4. THREE-BYTE COMMAND SEQUENCE (WRITE) FN8190 Rev 5.00 September 14, 2015 Page 6 of 20 X9401 CS SCL SI DON’T CARE 0 1 0 0 1 0 A1 A0 I3 I2 I1 I0 R1 R0 P1 P0 S0 0 0 D5 D4 D3 D2 D1 D0 I N C N D E C 1 FIGURE 5. THREE-BYTE COMMAND SEQUENCE (READ) CS SCK SI 0 1 0 1 0 0 A1 A0 I3 I2 I1 I0 0 0 P1 P0 I N C 1 I N C 2 D E C N FIGURE 6. INCREMENT/DECREMENT COMMAND SEQUENCE TWRID SCK SI VOLTAGE OUT VW/RW INC/DEC CMD ISSUED FIGURE 7. INCREMENT/DECREMENT TIMING LIMITS TABLE 1. INSTRUCTION SET INSTRUCTION SET INSTRUCTION I3 I2 I1 I0 R1 R0 P1 P0 OPERATION Read Wiper Counter Register 1 0 0 1 0 0 P1 P0 Read the contents of the Wiper Counter Register pointed to by P1 - P0 Write Wiper Counter Register 1 0 1 0 0 0 P1 P0 Write new value to the Wiper Counter Register pointed to by P1 - P0 Read Data Register 1 0 1 1 R1 R0 P1 P0 Read the contents of the Data Register pointed to by P1 - P0 and R1 - R0 Write Data Register 1 1 0 0 R1 R0 P1 P0 Write new value to the Data Register pointed to by P1 - P0 and R1 - R0 XFR Data Register to Wiper Counter Register 1 1 0 1 R1 R0 P1 P0 Transfer the contents of the Data Register pointed to by R1 - R0 to the Wiper Counter Register pointed to by P1 - P0 FN8190 Rev 5.00 September 14, 2015 Page 7 of 20 X9401 TABLE 1. INSTRUCTION SET INSTRUCTION SET INSTRUCTION I3 I2 I1 I0 R1 R0 P1 P0 OPERATION XFR Wiper Counter Register to Data Register 1 1 1 0 R1 R0 P1 P0 Transfer the contents of the Wiper Counter Register pointed to by P1 - P0 to the Register pointed to by R1 - R0 Global XFR Data Register to Wiper Counter Register 0 0 0 1 R1 R0 0 0 Transfer the contents of the Data Registers pointed to by R1 - R0 of all four pots to their respective Wiper Counter Register Global XFR Wiper Counter Register to Data Register 1 0 0 0 R1 R0 0 0 Transfer the contents of all Wiper Counter Registers to their respective data Registers pointed to by R1 - R0 of all four pots Increment/Decrement Wiper Counter Register 0 0 1 0 0 0 P1 P0 Enable Increment/decrement of the Wiper Counter Register pointed to by P1 - P0 Read Status (WIP bit) 0 1 0 1 0 0 0 1 Read the status of the internal write cycle, by checking the WIP bit. FN8190 Rev 5.00 September 14, 2015 Page 8 of 20 X9401 Instruction Format NOTES: 3. A1 ~ A0”: stands for the device addresses sent by the master. 4. WPx refers to wiper position data in the Counter Register 5. “I”: stands for the increment operation, SI held HIGH during active SCK phase (high). 6. “D”: stands for the decrement operation, SI held LOW during active SCK phase (high). Read Wiper Counter Register (WCR) DEVICE TYPE IDENTIFIER CS FALLING EDGE 0 1 0 1 DEVICE ADDRESSES 0 0 A1 INSTRUCTION OPCODE A0 1 0 0 WCR ADDRESSES 1 0 0 P1 P0 WIPER POSITION (SENT BY X9401 ON SO) 0 0 WP5 WP4 WP3 WP2 WP1 WP0 CS RISING EDGE Write Wiper Counter Register (WCR) CS FALLING EDGE DEVICE TYPE IDENTIFIER 0 1 0 1 DEVICE ADDRESSES 0 0 A1 INSTRUCTION OPCODE A0 1 0 1 WCR ADDRESSES 0 0 0 P1 P0 DATA BYTE (SENT BY HOST ON SI) 0 0 WP5 WP4 WP3 WP2 WP1 CS RISING WP0 EDGE Read Data Register (DR) CS FALLING EDGE DEVICE TYPE IDENTIFIER 0 1 0 DEVICE ADDRESSES 1 0 0 A1 INSTRUCTION OPCODE A0 1 0 1 DR AND WCR ADDRESSES 1 R1 R0 P1 P0 DATA BYTE (SENT BY X9401 ON SO) 0 0 WP5 WP4 WP3 WP2 WP1 WP0 CS RISING EDGE Write Data Register (DR) CS FALLING EDGE DEVICE TYPE DEVICE INSTRUCTION IDENTIFIER ADDRESSES OPCODE 0 1 0 1 0 0 A1 A0 1 1 0 0 DR AND WCR ADDRESSES DATA BYTE (SENT BY HOST ON SI) HIGHCS VOLTAGE WRITE RISING R1 R0 P1 P0 0 0 WP5 WP4 WP3 WP2 WP1 WP0 CYCLE EDGE Transfer Data Register (DR) to Wiper Counter Register (WCR) CS FALLING EDGE DEVICE TYPE IDENTIFIER 0 1 0 1 DEVICE ADDRESSES 0 0 A1 A0 INSTRUCTION OPCODE 1 1 0 DR AND WCR ADDRESSES CS RISING R1 R0 P1 P0 EDGE 1 Transfer Wiper Counter Register (WCR) to Data Register (DR) CS FALLING EDGE DEVICE TYPE IDENTIFIER 0 1 0 1 DEVICE ADDRESSES 0 0 A1 INSTRUCTION OPCODE A0 1 1 1 0 DR AND WCR ADDRESSES R1 CS RISING P1 P0 EDGE R0 HIGH-VOLTAGE WRITE CYCLE Increment/Decrement Wiper Counter Register (WCR) CS FALLING EDGE DEVICE TYPE IDENTIFIER 0 1 0 1 DEVICE ADDRESSES 0 0 A1 A0 INSTRUCTION OPCODE 0 0 1 0 WCR ADDRESSES X X P1 P0 INCREMENT/DECREMENT (SENT BY MASTER ON SDA) I/D I/D . . . . I/D I/D CS RISING EDGE Global Transfer Data Register (DR) to Wiper Counter Register (WCR) CS FALLING EDGE DEVICE TYPE IDENTIFIER 0 1 0 FN8190 Rev 5.00 September 14, 2015 1 DEVICE ADDRESSES 0 0 A1 A0 INSTRUCTION OPCODE 0 0 0 1 DR ADDRESSES R1 R0 0 0 CS RISING EDGE Page 9 of 20 X9401 Global Transfer Wiper Counter Register (WCR) to Data Register (DR) CS FALLING EDGE DEVICE TYPE IDENTIFIER 0 1 0 DEVICE ADDRESSES 1 0 0 A1 INSTRUCTION OPCODE A0 1 0 0 DR ADDRESSES 0 R1 R0 0 0 CS RISING EDGE HIGH-VOLTAGE WRITE CYCLE Read Status CS FALLING EDGE DEVICE TYPE IDENTIFIER 0 1 0 FN8190 Rev 5.00 September 14, 2015 1 DEVICE ADDRESSES 0 0 A1 A0 INSTRUCTION OPCODE WIPER ADDRESSES 0 0 1 0 1 0 0 1 DATA BYTE (SENT BY X9401 ON SO) 0 0 0 0 0 0 0 WIP CS RISING EDGE Page 10 of 20 X9401 Absolute Maximum Ratings Thermal Information Supply Voltage (VCC Limits) X9401 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10% X9401-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Voltage on SCK, SCL or any address input with respect to VSS: . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V V = |(VH–VL)| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65C to +135C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Temperature Range Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C Industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. Analog Specifications SYMBOL RTOTAL (Over recommended operating conditions unless otherwise stated.) PARAMETER End to End resistance Tolerance Power Rating IW Wiper Current RW Wiper Resistance VTERM TEST CONDITION TYP -20 +25°C, each pot -6 IW = (VH - VL)/RTOTAL VCC = 5V Voltage on any VH or VL Pin Noise MIN (Note 10) 150 VSS Ref: 1kHz Resolution Absolute Linearity (Note 7) VW(n)(actual) - VW(n)(expected) Relative Linearity (Note 8) Vw(n+1) - [Vw(n)+ MI] Temperature Coefficient of RTOTAL V(RH) = VCC, V(RL) = VSS Ratiometric Temperature Coefficient CH/CL/CW Potentiometer Capacitances See Macro model IAL RH, RL, RW Leakage Current VIN = VSS Device is in Stand-by mode. MAX (Note 10) UNIT +20 % 50 mW +6 mA 500  VCC V -120 dBV 1.6 % -1 +1 MI (Note 9) -0.2 +0.2 MI (Note 9) 300 ppm/°C 20 ppm/°C 10/10/25 pF 0.1 10 µA NOTES: 7. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. 8. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. 9. MI = RTOT/63 or (VH - VL)/63, single pot. 10. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. Power-up and Down Requirements The are no restrictions on the power-up or power-down conditions of VCC and the voltages applied to the potentiometer pins provided that VCC is always more positive than or equal to VH, VL, and VW, i.e., VCC VH, VL, VW. The VCC power-up spec is always in effect. FN8190 Rev 5.00 September 14, 2015 Page 11 of 20 X9401 DC Operating Characteristics (Over the recommended operating conditions unless otherwise specified.) SYMBOL PARAMETER MIN (Note 10) TEST CONDITIONS TYP MAX (Note 10) UNIT ICC1 VCC Supply Current (active) fSCK = 2MHz, SO = Open, Other Inputs = VSS 700 µA ICC2 VCC Supply Current (non-volatile write) fSCK = 2MHz, SO = Open, Other Inputs = VSS 3 mA ISB VCC Current (standby) SCK = SI = VSS, Addr. = VSS, CS = VCC 3 µA ILI Input Leakage Current VIN = VSS to VCC 10 µA ILO Output Leakage Current VOUT = VSS to VCC 10 µA VIH Input HIGH Voltage VCC x 0.7 VCC +0.5 V VIL Input LOW Voltage –0.5 VCC x 0.1 V VOL Output LOW Voltage 0.4 V IOL = 3mA Endurance and Data Retention PARAMETER MIN. Minimum endurance 100,000 Data retention 100 UNIT Data changes per bit per register years Capacitance SYMBOL TEST TYP. UNIT TEST CONDITION COUT (Note 11) Output capacitance (SO) 8 pF VOUT = 0V CIN (Note 11) Input capacitance (A0, A1, SI, and SCK) 6 pF VIN = 0V Power-up Timing Input pulse levels = VCC x 0.1 to VCC x 0.9; Input rise and fall times = 10ns; Input and output timing level = VCC x 0.5. SYMBOL PARAMETER MIN. MAX. UNIT 0.2 50 V/ms tr VCC (Note 11) VCC Power-up rate tPUR (Note 12) Power-up to initiation of read operation 1 ms tPUW (Note 12) Power-up to initiation of write operation 5 ms NOTES: 11. This parameter is not 100% tested. 12. tPUR and tPUW are the delays required from the time the (last) power supply (VCC-) is stable until the specific instruction can be issued. These parameters are periodically sampled and not 100% tested. Equivalent AC Load Circuit SPICE MACRO MODEL 5V 1533 SDA OUTPUT RTOTAL RH CW CL 100pF RL CL 10pF 25pF 10pF RW FN8190 Rev 5.00 September 14, 2015 Page 12 of 20 X9401 AC Timing SYMBOL PARAMETER MIN. (Note 10) MAX. (Note 10) UNIT 2.0 MHz fSCK SSI/SPI clock frequency tCYC SSI/SPI clock cycle rime 500 ns tWH SSI/SPI clock high rime 200 ns tWL SSI/SPI clock low time 200 ns tLEAD Lead time 250 ns tLAG Lag time 250 ns tSU SI, SCK, HOLD and CS input setup time 50 ns tH SI, SCK, HOLD and CS input hold time 50 ns tRI SI, SCK, HOLD and CS input rise time 2 µs tFI SI, SCK, HOLD and CS input fall time 2 µs 500 ns 150 ns tDIS SO output disable time 0 tV SO output valid time tHO SO output hold time tRO SO output rise time 50 ns tFO SO output fall time 50 ns tHOLD 0 ns HOLD time 400 ns tHSU HOLD setup time 100 ns tHH HOLD hold time 100 ns tHZ HOLD low to output in high Z 100 ns tLZ HOLD high to output in low Z 100 ns TI Noise suppression time constant at SI, SCK, HOLD and CS inputs 20 ns tCS CS deselect time 2 µs tWPASU WP, A0 and A1 setup time 0 ns tWPAH WP, A0 and A1 hold time 0 ns High-voltage Write Cycle Timing SYMBOL tWR PARAMETER High-voltage write cycle time (store instructions) TYP MAX (Note 10) UNIT 5 10 ms XDCP Timing MAX. (Note 10) UNIT Wiper response time after the third (last) power supply is stable 10 µs tWRL Wiper response time after instruction issued (all load instructions) 10 µs tWRID Wiper response time from an active SCL/SCK edge (increment/decrement instruction) 450 ns SYMBOL tWRPO PARAMETER FN8190 Rev 5.00 September 14, 2015 MIN. Page 13 of 20 X9401 Symbol Table WAVEFORM INPUTS OUTPUTS MUST BE STEADY WILL BE STEADY MAY CHANGE FROM LO W TO HIGH WILL CHANGE FROM LO W TO HIGH MAY CHANGE FROM HIGH TO LOW WILL CHANGE FROM HIGH TO LOW DON’T CARE: CHANGES ALLOWED CHANGING: STATE NOT KNOWN N/A CENTER LINE IS HIGH IMPEDANCE Timing Diagrams Input Timing tCS CS SCK tSU tH ... tWH tWL tRI tFI ... MSB SI tLAG tCYC tLEAD LSB HIGH IMPEDANCE SO Output Timing CS SCK ... tV MSB SO SI tHO tDIS ... LSB ADDR FN8190 Rev 5.00 September 14, 2015 Page 14 of 20 X9401 Hold Timing CS tHSU tHH SCK ... tRO tFO SO tHZ tLZ SI tHOLD HOLD XDCP Timing (for All Load Instructions) CS SCK ... tWRL ... MSB SI LSB VW/RW SO HIGH IMPEDANCE XDCP Timing (for Increment/Decrement Instruction) CS SCK ... tWRID ... VW/RW SI SO ADDR INC/DEC INC/DEC ... HIGH IMPEDANCE Write Protect and Device Address Pins Timing (ANY INSTRUCTION) CS tWPASU tWPAH WP A0 A1 FN8190 Rev 5.00 September 14, 2015 Page 15 of 20 X9401 Applications information Basic Configurations of Electronic Potentiometers +VR VR VW/RW I THREE TERMINAL POTENTIOMETER; TWO TERMINAL VARIABLE RESISTOR; VARIABLE VOLTAGE DIVIDER VARIABLE CURRENT Application Circuits NONINVERTING AMPLIFIER VS VOLTAGE REGULATOR + VIN VO – VO (REG) 317 R1 R2 IADJ R1 R2 VO (REG) = 1.25V (1+R2/R1)+IADJ R2 VO = (1+R2/R1)VS OFFSET VOLTAGE ADJUSTMENT R1 COMPARATOR WITH HYSTERESIS R2 VS VS – VO + – 100K VO + 10K 10K } 10K } TL072 R1 R2 VUL = {R1/(R1+R2)} VO(MAX) VLL = {R1/(R1+R2)} VO(MIN) +5V ATTENUATOR FILTER C VS + R2 R1 – VS + VO R R3 R2 R4 ALL RS = 10K R1 VO = G VS GO = 1 + R2/R1 -1/2  G  +1/2 fc = 1/(2RC) FN8190 Rev 5.00 September 14, 2015 VO – Page 16 of 20 X9401 Application Circuits (continued) } VS R2 } INVERTING AMPLIFIER R1 EQUIVALENT L-R CIRCUIT R2 C1 VS – + VO + – R1 ZIN R3 VO = G VS G = - R2/R1 ZIN = R2 + S R2 (R1 + R3) C1 = R2 + S LEQ (R1 + R3) >> R2 FUNCTION GENERATOR C R2 – R1 – + } RA + } RB FREQUENCY µ R1, R2, C AMPLITUDE µ RA, RB FN8190 Rev 5.00 September 14, 2015 Page 17 of 20 X9401 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION September 14, 2015 FN8190.5 CHANGE - Ordering Information Table on page 2. - Added Revision History. - Added About Intersil Verbiage. - Updated POD M24.3 to most current version change is as follows: Updated to new POD standard by removing table listing dimensions and putting dimensions on drawing. Added Land Pattern. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support. FN8190 Rev 5.00 September 14, 2015 Page 18 of 20 X9401 Package Outline Drawing M24.3 24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE (SOIC) Rev 2, 3/11 24 INDEX AREA 7.60 (0.299) 7.40 (0.291) 10.65 (0.419) 10.00 (0.394) DETAIL "A" 1 2 3 TOP VIEW 1.27 (0.050) 0.40 (0.016) SEATING PLANE 2.65 (0.104) 2.35 (0.093) 15.60 (0.614) 15.20 (0.598) 0.75 (0.029) x 45° 0.25 (0.010) 0.30 (0.012) 0.10 (0.004) 1.27 (0.050) 0.51 (0.020) 0.33 (0.013) 8° 0° 0.32 (0.012) 0.23 (0.009) SIDE VIEW “B” SIDE VIEW “A” 1.981 (0.078) 9.373 (0.369) 1.27 (0.050) NOTES: 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. Package length does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 3. Package width does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 5. Terminal numbers are shown for reference only. 6. The lead width as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 7. Controlling dimension: MILLIMETER. Converted inch dimensions in ( ) are not necessarily exact. 8. This outline conforms to JEDEC publication MS-013-AD ISSUE C. 0.533 (0.021) TYPICAL RECOMMENDED LAND PATTERN FN8190 Rev 5.00 September 14, 2015 Page 19 of 20 X9401 Thin Shrink Small Outline Package Family (TSSOP) MDP0044 0.25 M C A B D THIN SHRINK SMALL OUTLINE PACKAGE FAMILY A MILLIMETERS (N/2)+1 N SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE PIN #1 I.D. E E1 1 (N/2) B 0.20 C B A 2X N/2 LEAD TIPS TOP VIEW 0.05 e C SEATING PLANE H A 1.20 1.20 1.20 1.20 1.20 Max A1 0.10 0.10 0.10 0.10 0.10 ±0.05 A2 0.90 0.90 0.90 0.90 0.90 ±0.05 b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06 c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06 D 5.00 5.00 6.50 7.80 9.70 ±0.10 E 6.40 6.40 6.40 6.40 6.40 Basic E1 4.40 4.40 4.40 4.40 4.40 ±0.10 e 0.65 0.65 0.65 0.65 0.65 Basic L 0.60 0.60 0.60 0.60 0.60 ±0.15 L1 1.00 1.00 1.00 1.00 1.00 Reference Rev. F 2/07 0.10 M C A B b 0.10 C N LEADS SIDE VIEW NOTES: 1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm per side. SEE DETAIL “X” 3. Dimensions “D” and “E1” are measured at dAtum Plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. c END VIEW L1 A A2 GAUGE PLANE 0.25 L A1 0° - 8° DETAIL X © Copyright Intersil Americas LLC 2005-2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8190 Rev 5.00 September 14, 2015 Page 20 of 20