X9409WS24Z

DATASHEET OBSOLETE PRODUCT NO RECOMMENDED REPLACEMENT contact our Technical Support Center at 1-888-INTERSIL or www.intersil.com/tsc X9409 FN8192 Rev.6.00 Sep 3, 2015 Low Noise/Low Power/2-Wire Bus Quad Digitally Controlled Potentiometers (XDCP) Features The X9409 integrates 4 digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated microcircuit. The digitally controlled potentiometer is implemented using 63 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the 2-wire bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and 4 nonvolatile Data Registers (DR0:DR3) that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array through the switches. Power-up recalls the contents of DR0 to the WCR. The XDCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments and signal processing. • Four potentiometers per package • 64 resistor taps • 2-wire serial interface for write, read and transfer operations of the potentiometer • 50Ω wiper resistance, typical at 5V • Four nonvolatile data registers for each potentiometer • Nonvolatile storage of multiple wiper position • Power-on recall. Loads saved wiper position on power-up standby current < 1µA typical • System VCC: 2.7V operation • 10kΩ end-to-end resistance • 100 year data retention • Endurance: 100,000 data changes per bit per register • Low power CMOS • 24 Ld TSSOP • Pb-free (RoHS compliant) POT 0 VCC VSS WP R0 R1 R2 R3 WIPER COUNTER REGISTER (WCR) SCL SDA A0 A1 A2 INTERFACE AND CONTROL CIRCUITRY A3 VH0/RHO R0 R1 VL0/ RLO R2 R3 WIPER COUNTER REGISTER (WCR) RESISTOR ARRAY POT 2 VH2/RH2 VL2/RL2 VW0/ RWO VW2/RW2 VW1/ RW1 VW3/RW3 8 DATA R0 R2 R1 R3 WIPER COUNTER REGISTER (WCR) RESISTOR ARRAY POT 1 VH1/ RH1 R0 VL1/RL1 R2 R1 R3 WIPER COUNTER REGISTER (WCR) RESISTOR ARRAY Pot 3 VH3/RH3 VL3/RL3 FIGURE 1. BLOCK DIAGRAM FN8192 Rev.6.00 Sep 3, 2015 Page 1 of 19 X9409 Ordering Information PART NUMBER (Notes 1, 2, 3) POTENTIOMETER ORGANIZATION TEMP (kΩ) RANGE (°C) PACKAGE (RoHS Compliant) PKG. DWG. # PART MARKING VCC LIMITS (V) X9409WV24IZ (No longer available, X9409WV ZI recommended replacement: X9409WV24IZ-2.7) 2.7 to 5.5 10 -40 to +85 24 Ld TSSOP (4.4mm) M24.173 X9409WV24IZ-2.7 2.7 to 5.5 10 -40 to +85 24 Ld TSSOP (4.4mm) M24.173 X9409WV24Z (No longer available, X9409WV Z recommended replacement: X9409WV24IZ-2.7) 2.7 to 5.5 10 -40 to +85 24 Ld TSSOP (4.4mm) M24.173 X9409WV24Z-2.7 (No longer available, X9409WV ZF recommended replacement: X9409WV24IZ-2.7) 2.7 to 5.5 10 0 to +70 24 Ld TSSOP (4.4mm) M24.173 X9409WV ZG NOTES: 1. Add “T1” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see product information page for X9409. For more information on MSL, please see tech brief TB363. Pin Configuration X9409 (24 LD TSSOP) TOP VIEW SDA 1 24 WP A1 2 23 A2 VL1/RL1 3 22 VW0/RW0 VH1/RH1 4 21 VH0/RH0 VW1/RW1 5 20 VL0/RL0 VSS 6 19 VCC NC 7 18 NC VW2/RW2 8 17 VL3/RL3 VH2/RH2 9 16 VH3/RH3 VL2/RL2 10 15 VW3/RW3 SCL 11 14 A0 A3 12 13 NC Pin Descriptions PIN # SYMBOL DESCRIPTION 11 SCL Serial Clock 1 SDA Serial Data 14, 2, 23, 12 21, 4, 9, 16, 20, 3, 10, 17 22, 5, 8, 15 A0, A1, A2, A3 Device Address VH0/RH0, VH1/RH1, VH2/RH2, VH3/RH3, VL0/RL0, VL1/RL1, VL2/RL2, VL3/RL3 Potentiometer Pin (terminal equivalent) VW0/RW0, VW1/RW1, VW2/RW2, VW3/RW3 Potentiometer Pin (wiper equivalent) 24 WP Hardware Write Protection 19 VCC System Supply Voltage 6 VSS System Ground (Digital) 7, 13, 18 NC No Connection FN8192 Rev.6.00 Sep 3, 2015 Page 2 of 19 X9409 Host Interface Pins Serial Clock (SCL) The SCL input is used to clock data into and out of the X9409. SERIAL DATA (SDA) The SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-O Red with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. DEVICE ADDRESS (A0, A2, A3) The address inputs are used to set the least significant 4 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the address input in order to initiate communication with the X9409. A maximum of 16 devices may occupy the 2-wire serial bus. Potentiometer Pins VH0/RH0 - VH3/RH3, VL0/RL0 - VL3/RL3 The VH/RH and VL/RL inputs are equivalent to the terminal connections on either end of a mechanical potentiometer. VW0/RW0 - VW3/RW3 The wiper outputs are equivalent to the wiper output of a mechanical potentiometer. HARDWARE WRITE PROTECT INPUT (WP) The WP pin when low prevents nonvolatile writes to the Data Registers. PRINCIPLES OF OPERATION The X9409 is a highly integrated microcircuit incorporating four resistor arrays and their associated registers and counters and the serial interface logic providing direct communication between the host and the XDCP potentiometers. Serial Interface The X9409 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X9409 will be considered a slave device in all applications. START CONDITION All commands to the X9409 are preceded by the start condition, which is a HIGH-to-LOW transition of SDA while SCL is HIGH (tHIGH). The X9409 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition is met. STOP CONDITION All communications must be terminated by a stop condition, which is a LOW-to-HIGH transition of SDA while SCL is HIGH. ACKNOWLEDGE Acknowledge is a software convention used to provide a positive handshake between the master and slave devices on the bus to indicate the successful receipt of data. The transmitting device, either the master or the slave, will release the SDA bus after transmitting eight bits. The master generates a ninth clock cycle and during this period the receiver pulls the SDA line LOW to acknowledge that it successfully received the eight bits of data. The X9409 will respond with an acknowledge after recognition of a start condition and its slave address and once again after successful receipt of the command byte. If the command is followed by a data byte the X9409 will respond with a final acknowledge. ARRAY DESCRIPTION The X9409 is comprised of four resistor arrays. Each array contains 63 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (VH/RH and VL/RL inputs). At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (VW/RW) output. Within each individual array only one switch may be turned on at a time. These switches are controlled by the Wiper Counter Register (WCR). The 6 bits of the WCR are decoded to select and enable, one of sixty-four switches. The WCR may be written directly, or it can be changed by transferring the contents of one of four associated Data Registers into the WCR. These Data Registers and the WCR can be read and written by the host system. Clock and Data Conventions Data states on the SDA line can change only during SCL LOW periods (tLOW). The SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. FN8192 Rev.6.00 Sep 3, 2015 Page 3 of 19 X9409 WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from Low to High Will change from Low to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance Guidelines for Calculating Typical Values of Bus Pull-Up Resistors 120 100 RESISTANCE (k) Symbol Table RMIN = 80 RMAX = 60 VCC MAX I OL MIN = 1.8kΩ tR CBUS MAX. RESISTANCE 40 20 MIN. RESISTANCE 0 0 20 40 60 80 100 120 BUS CAPACITANCE (pF) FN8192 Rev.6.00 Sep 3, 2015 Page 4 of 19 X9409 Absolute Maximum Ratings Thermal Information Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Voltage on SDA, SCL or any address input with respect to VSS .-1V to +7V  V = |VH - VL | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ESD Rating Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . 4kV Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . 300V Thermal Resistance JA (°C/W) JC (°C/W) 24 Ld TSSOP (Notes 4, 5) . . . . . . . . . . . . . . 71 19 Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 Recommended Operating Conditions Commercial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 5. For JC, the “case temp” location is taken at the package top center. Analog Characteristics SYMBOL Across the recommended operating conditions unless otherwise specified. PARAMETER TEST CONDITIONS MIN (Note 6) TYP End-to-end Resistance Tolerance Power Rating +25°C, each pot at 5V, 2.5k IW Wiper Current RW Wiper Resistance IW = ±3mA, VCC = 3V to 5V Voltage On Any VH/RH or VL/RL pin VSS = 0V Noise Ref: 1kHz V TERM -3 50 VSS MAX (Note 6) UNITS ±20 % 15 mW +3 mA 150 Ω VCC V - Resolution (Note 10) dBV 1.6 Absolute Linearity (Note 7) Vw(n)(actual) - Vw(n)(expected) Relative Linearity (Note 8) Vw(n + 1) - [Vw(n) + MI] -1 -0.2 % +1 MI (Note 9) +0.2 MI (Note 9) ppm/°C 30 Temperature Coefficient Of RTOTAL Ratiometric Temp. Coefficient CH/CL/CW Potentiometer Capacitances See macro model 10/ IAL RH, RL, RW Leakage Current VIN = VSS to VCC. Device is in stand-by mode. 0.1 20 ppm/°C 10 µA pF D.C. OPERATING CHARACTERISTICS ICC1 VCC Supply Current (Active) fSCL = 400kHz, SDA = open, other inputs = VSS 100 µA ICC2 VCC Supply Current (Nonvolatile Write) fSCL = 400kHz, SDA = open, other inputs = VSS 1 mA ISB VCC Current (Standby) SCL = SDA = VCC, addr. = VSS 3 µA ILI Input Leakage Current VIN = VSS to VCC 10 µA ILO Output Leakage Current VOUT = VSS to VCC 10 µA VIH Input HIGH Voltage VCC x 0.7 VCC + 0.5 V VIL Input LOW Voltage -0.5 VCC x 0.1 V VOL Output LOW Voltage 0.4 V IOL = 3mA ENDURANCE AND DATA RETENTION Minimum Endurance Data Retention FN8192 Rev.6.00 Sep 3, 2015 100,000 100 Data changes per bit per register Years Page 5 of 19 X9409 Analog Characteristics SYMBOL Across the recommended operating conditions unless otherwise specified. PARAMETER MIN (Note 6) TEST CONDITIONS TYP MAX (Note 6) UNITS CAPACITANCE CI/O (Note 10) Input/Output Capacitance (SDA) VI/O = 0V 8 pF CIN (Note 10) Input Capacitance (A0, A1, A2, A3 and SCL) VIN = 0V 6 pF 50 V/ms POWER-UP TIMING tr VCC (Note 11) VCC Power-Up Rate 0.2 A.C. TEST CONDITIONS VCC x 0.1 to VCC x 0.9 Input Pulse Levels Input Rise and Fall Times 10ns Input and Output Timing Level VCC x 0.5 5V RTOTAL 1533Ω RH CL CH SDA Output CW 10pF 100pF RL 10pF 25pF RW FIGURE 3. CIRCUIT #3 SPICE MACRO MODEL FIGURE 2. EQUIVALENT A.C. LOAD CIRCUIT AC TIMING Across recommended operating conditions. SYMBOL PARAMETER MIN (Note 6) MAX (Note 6) UNITS 400 kHz fSCL Clock Frequency tCYC Clock Cycle Time 2500 ns tHIGH Clock High Time 600 ns tLOW Clock Low Time 1300 ns tSU:STA Start Setup Time 600 ns tHD:STA Start Hold Time 600 ns tSU:STO Stop Setup Time 600 ns tSU:DAT SDA Data Input Setup Time 100 ns tHD:DAT SDA Data Input Hold Time (Note 12) 30 ns tR SCL and SDA Rise Time 300 ns tF SCL and SDA Fall Time 300 ns tAA SCL Low to SDA Data Output Valid Time 900 ns tDH SDA Data Output Hold Time 50 ns Noise Suppression Time Constant At SCL and SDA Inputs 50 ns 1300 ns TI tBUF FN8192 Rev.6.00 Sep 3, 2015 Bus Free Time (Prior To Any Transmission) Page 6 of 19 X9409 AC TIMING Across recommended operating conditions. (Continued) SYMBOL tSU:WPA WP, A0, A1, A2 and A3 Setup Time tHD:WPA WP, A0, A1, A2 and A3 Hold Time MAX (Note 6) MIN (Note 6) PARAMETER UNITS 0 ns 0 HIGH-VOLTAGE WRITE CYCLE TIMING SYMBOL tWR PARAMETER High-Voltage Write Cycle Time (Store Instructions) TYP MAX (Note 6) UNIT 5 10 ms XDCP TIMING SYMBOL PARAMETER MIN (Note 6) TYP MAX (Note 6) UNITS tWRPO Wiper Response Time After The Third (Last) Power Supply Is Stable 2 10 µs tWRL Wiper Response Time After Instruction Issued (All Load Instructions) 2 10 µs tWRID Wiper Response Time From An Active SCL/SCK Edge (Increment/Decrement Instruction) 2 10 µs NOTES: 6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 7. Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. 8. Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. 9. MI = RTOT/63 or (VH - VL)/63, single pot. 10. This parameter is periodically sampled and not 100% tested. 11. Sample tested only. 12. A device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. FN8192 Rev.6.00 Sep 3, 2015 Page 7 of 19 X9409 TIMING DIAGRAMS START and STOP Timing (START) (STOP) tR tF SCL tSU:STA tHD:STA tSU:STO tR tF SDA Input Timing tCYC tHIGH SCL tLOW SDA tSU:DAT tHD:DAT tBUF Output Timing SCL SDA tDH tAA Power-up Requirements (Power-up sequencing can affect correct recall of the wiper registers) The preferred power-on sequence is as follows: First VCC, then the potentiometer pins, RH, RL and RW. The VCC ramp rate specification should be met and any glitches or slope changes in the VCC line should be held to > R2 FIGURE 22. EQUIVALENT L-R CIRCUIT FIGURE 21. INVERTING AMPLIFIER C R2 – R1 – + + } RA } RB frequency  R1, R2, C amplitude  RA, RB FIGURE 23. FUNCTION GENERATOR FN8192 Rev.6.00 Sep 3, 2015 Page 16 of 19 X9409 XDCP Timing (for All Load Instructions) (STOP) SCL LSB SDA tWRL VWx XDCP Timing (for Increment/Decrement Instruction) SCL SDA WIPER REGISTER ADDRESS INC/DEC INC/DEC tWRID VW/RW Write Protect and Device Address Pins Timing (START) (STOP) SCL ... (ANY INSTRUCTION) ... SDA ... tSU:WPA tHD:WPA WP A0, A1 A2, A3 FN8192 Rev.6.00 Sep 3, 2015 Page 17 of 19 X9409 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE September 3, 2015 FN8192.6 Updated Ordering Information table on page 2. April 20, 2015 FN8192.5 Updated Template. Added revision history. Removed part numbers X9409WS24I-2.7 and X9409WS24IZ-2.7 from ordering information table. Analog Characteristics table on page 5, in ISB section: Changed max value from 1µ to 3µ. Removed 24 Ld SOIC throughout the document. Removed POD M24.3. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support © Copyright Intersil Americas LLC 2005-2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8192 Rev.6.00 Sep 3, 2015 Page 18 of 19 X9409 Package Outline Drawing M24.173 24 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) Rev 1, 5/10 A 1 3 7.80 ±0.10 SEE DETAIL "X" 13 24 6.40 PIN #1 I.D. MARK 4.40 ±0.10 2 3 0.20 C B A 1 12 0.15 +0.05 -0.06 B 0.65 TOP VIEW END VIEW 1.00 REF H - 0.05 C 0.90 +0.15 -0.10 1.20 MAX GAUGE PLANE SEATING PLANE 0.25 +0.05 -0.06 0.10 M C B A 0.10 C 5 0°-8° 0.05 MIN 0.15 MAX SIDE VIEW 0.25 0.60± 0.15 DETAIL "X" (1.45) NOTES: 1. Dimension does not include mold flash, protrusions or gate burrs. (5.65) Mold flash, protrusions or gate burrs shall not exceed 0.15 per side. 2. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25 per side. 3. Dimensions are measured at datum plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Dimension does not include dambar protrusion. Allowable protrusion shall be 0.08mm total in excess of dimension at maximum material condition. Minimum space between protrusion and adjacent lead (0.65 TYP) (0.35 TYP) TYPICAL RECOMMENDED LAND PATTERN is 0.07mm. 6. Dimension in ( ) are for reference only. 7. Conforms to JEDEC MO-153. FN8192 Rev.6.00 Sep 3, 2015 Page 19 of 19