X9429YS16Z-2.7

DATASHEET X9429 FN8248 Rev 4.00 October 16, 2015 Low Noise/Low Power/2-Wire Bus Single Digitally Controlled Potentiometer (XDCP™) The X9429 integrates a single digitally controlled potentiometer (XDCP) on a monolithic CMOS integrated circuit. The digital controlled potentiometer is implemented using 63 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the 2-wire bus interface. The potentiometer has associated with it a volatile Wiper Counter Register (WCR) and a four non-volatile Data Registers that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array though the switches. Power-up recalls the contents of the default data register (DR0) to the WCR. The XDCP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. Features • Single Voltage Potentiometer • 64 Resistor Taps • 2-wire Serial Interface for Write, Read, and Transfer Operations of the Potentiometer • Wiper Resistance, 150W Typical at 5V • Non-Volatile Storage of Multiple Wiper Positions • Power-on Recall. Loads Saved Wiper Position on Power-up. • Standby Current < 3µA Max • VCC : 2.7V to 5.5V Operation • 2.5kW, 10kW Total Pot Resistance • Endurance: 100,000 Data Changes per Bit per Register • 100 yr. Data Retention • 14 Ld TSSOP, 16 Ld SOIC • Low Power CMOS • Pb-free available (RoHS compliant) Block Diagram VCC ADDRESS DATA STATUS 2-WIRE BUS INTERFACE VH/RH WRITE READ TRANSFER INC/DEC BUS INTERFACE AND CONTROL WIPER COUNTER REGISTER (WCR) CONTROL VSS FN8248 Rev 4.00 October 16, 2015 POWER-ON RECALL WIPER 10k 64-TAPS POT DATA REGISTERS 4 BYTES VL/RL VW/RW Page 1 of 21 X9429 Ordering Information PART NUMBER PART MARKING VCC LIMITS (V) POTENTIOMETER ORGANIZATION (kΩ) TEMP RANGE (°C) 5 ±10% 10 0 to +70 16 Ld SOIC (300 mil) M16.3 16 Ld SOIC (300 mil) M16.3 PACKAGE (RoHS Compliant) PKG DWG. # X9429WS16Z* (Note) (No longer available, recommended replacement: X9429WS16IZT1) X9429WS Z X9429WS16IZ* (Note) X9429WS Z I -40 to +85 X9429WV14Z* (Note) X9429 WV Z 0 to +70 14 Ld TSSOP (4.4mm) M14.173 X9429WV14IZ* (Note) X9429 WV Z I -40 to +85 14 Ld TSSOP (4.4mm) M14.173 X9429WS16Z-2.7* (Note) (No longer available, recommended replacement: X9429WS16IZT1) X9429WS ZF X9429WS16IZ-2.7* (Note) (No longer available, recommended replacement: X9429WS16IZT1) 2.7 to 5.5 10 0 to +70 16 Ld SOIC (300 mil) M16.3 X9429WS ZG -40 to +85 16 Ld SOIC (300 mil) M16.3 X9429WV14Z-2.7* (Note) X9429 WVZF 0 to +70 14 Ld TSSOP (4.4mm) M14.173 X9429WV14IZ-2.7* (Note) X9429 WVZ G -40 to +85 14 Ld TSSOP (4.4mm) M14.173 *Add “T1” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. FN8248 Rev 4.00 October 16, 2015 Page 2 of 21 X9429 Detailed Functional Diagram VCC POWER-ON RECALL DR0 DR1 10k 64--TAPS WIPER CONTROL SCL SDA A3 A2 COUNTER REGISTER (WCR) DR2 DR3 INTERFACE AND CONTROL CIRCUITRY A0 RH/VH RL/VL RW/VW D ATA WP VSS Circuit Level Applications System Level Applications • Vary the Gain of a Voltage Amplifier • Adjust the Contrast in LCD Displays • Provide Programmable DC Reference Voltages for Comparators and Detectors • Control the Power Level of LED Transmitters in Communication Systems • Control the Volume in Audio Circuits • Set and Regulate the DC Biasing Point in an RF Power Amplifier in Wireless Systems • Trim Out the Offset Voltage Error in a Voltage Amplifier Circuit • Set the Output Voltage of a Voltage Regulator • Trim the Resistance in Wheatstone Bridge Circuits • Control the Gain, Characteristic Frequency and Q-factor in Filter Circuits • Set the Scale Factor and Zero Point in Sensor Signal Conditioning Circuits • Control the Gain in Audio and Home Entertainment Systems • Provide the Variable DC Bias for Tuners in RF Wireless Systems • Set the Operating Points in Temperature Control Systems • Control the Operating Point for Sensors in Industrial Systems • Trim Offset and Gain Errors in Artificial Intelligent Systems • Vary the Frequency and Duty Cycle of Timer ICs • Vary the DC Biasing of a Pin Diode Attenuator in RF Circuits • Provide a Control Variable (I, V, or R) in Feedback Circuits FN8248 Rev 4.00 October 16, 2015 Page 3 of 21 X9429 Pinouts X9429 (16 LD SOIC) TOP VIEW X9429 (14 LD TSSOP) TOP VIEW NC 1 14 VCC NC 1 16 VCC NC 2 13 RL/VL NC 2 15 NC NC 3 12 RH/VH NC 3 14 RL/VL A2 4 13 RH/VH A2 4 SCL 5 X9429 11 RW/VW 10 A3 SDA 6 9 A0 VSS 7 8 WP X9429 SCL 5 12 RW/VW SDA 6 11 A3 NC 7 10 A0 VSS 8 9 WP Pin Assignments TSSOP PIN SOIC PIN SYMBOL 1, 2, 3 12, 3, 7, 15 NC BRIEF DESCRIPTION 4 4 A2 5 5 SCL Serial Clock for 2-wire bus. 6 6 SDA Serial Data Input/Output for 2-wire bus. 7 8 VSS System Ground 8 9 WP Hardware Write Protect 9 10 A0 Device Address for 2-wire bus. Device Address for 2-wire bus. No Connect Device Address for 2-wire bus. 10 11 A3 11 12 RW/VW Wiper Terminal of the Potentiometer. 12 13 RH/VH High Terminal of the Potentiometer. 13 14 RL/VL Low Terminal of the Potentiometer. 14 16 VCC System Supply Voltage Pin Descriptions Potentiometer Pins Host Interface Pins RH/VH, RL/VL SERIAL CLOCK (SCL) The RH/VH and RL/VL inputs are equivalent to the terminal connections on either end of a mechanical potentiometer. The SCL input is used to clock data into and out of the X9429. SERIAL DATA (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of a pull-up resistor. For selecting typical values, refer to the guidelines for calculating typical values on the bus pull-up resistors graph. DEVICE ADDRESS (A0, A2, A3) The Address inputs are used to set the least significant 3 bits of the 8-bit slave address. A match in the slave address serial data stream must be made with the Address input in order to initiate communication with the X9429. A maximum of 8 devices may occupy the 2-wire serial bus. FN8248 Rev 4.00 October 16, 2015 RW/VW The wiper outputs are equivalent to the wiper output of a mechanical potentiometer. HARDWARE WRITE PROTECT INPUT WP The WP pin when low prevents nonvolatile writes to the Data Registers. Principals of Operation The X9429 is a highly integrated microcircuit incorporating a resistor array and its associated registers and counters and the serial interface logic providing direct communication between the host and the XDCP potentiometers. Serial Interface The X9429 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a Page 4 of 21 X9429 transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the X9429 will be considered a slave device in all applications. Device Addressing Following a start condition, the master must output the address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier (refer to Figure 1). For the X9429 this is fixed as 0101[B]. DEVICE TYPE IDENTIFIER Clock and Data Conventions Data states on the SDA line can change only during SCL LOW periods (tLOW). SDA state changes during SCL HIGH are reserved for indicating start and stop conditions. 0 1 0 1 A3 A2 0 A0 Start Condition All commands to the X9429 are preceded by the start condition, which is a HIGH to LOW transition of SDA while SCL is HIGH (tHIGH). The X9429 continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition is met. Stop Condition All communications must be terminated by a stop condition, which is a LOW-to-HIGH transition of SDA while SCL is HIGH. Acknowledge Acknowledge is a software convention used to provide a positive handshake between the master and slave devices on the bus to indicate the successful receipt of data. The transmitting device, either the master or the slave, will release the SDA bus after transmitting eight bits. The master generates a ninth clock cycle and during this period, the receiver pulls the SDA line LOW to acknowledge that it successfully received the eight bits of data. The X9429 will respond with an acknowledge after recognition of a start condition and its slave address and once again after successful receipt of the command byte. If the command is followed by a data byte the X9429 will respond with a final acknowledge. Array Description The X9429 is comprised of a resistor array. The array contains 63 discrete resistive segments that are connected in series. The physical ends of the array are equivalent to the fixed terminals of a mechanical potentiometer (VH/RH and VL/RL inputs). At both ends of the array and between each resistor segment is a CMOS switch connected to the wiper (VW/RW) output. Within each individual array only one switch may be turned on at a time. These switches are controlled by the Wiper Counter Register (WCR). The six bits of the WCR are decoded to select, and enable, one of sixty-four switches. The WCR may be written directly, or it can be changed by transferring the contents of one of four associated Data Registers into the WCR. These Data Registers and the WCR can be read and written by the host system. FN8248 Rev 4.00 October 16, 2015 DEVICE ADDRESS FIGURE 1. SLAVE ADDRESS The next four bits of the slave address are the device address. The physical device address is defined by the state of the A0, A2, and A3 inputs. The X9429 compares the serial data stream with the address input state; a successful compare of all three address bits is required for the X9429 to respond with an acknowledge. The A0, A2, and A3 inputs can be actively driven by CMOS input signals or tied to VCC or VSS. Acknowledge Polling The disabling of the inputs, during the internal non-volatile write operation, can be used to take advantage of the typical 5ms EEPROM write cycle time. Once the stop condition is issued to indicate the end of the non-volatile write command, the X9429 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the device slave address. If the X9429 is still busy with the write operation, no ACK will be returned. If the X9429 has completed the write operation, an ACK will be returned, and the master can then proceed with the next operation. Instruction Structure The next byte sent to the X9429 contains the instruction and register pointer information. The four most significant bits are the instruction. The next four bits point to one of four associated registers. The format is shown in Figure 2. REGISTER SELECT I3 I2 I1 I0 R1 R0 0 0 INSTRUCTIONS FIGURE 2. INSTRUCTION BYTE FORMAT The four high order bits define the instruction. The next two bits (R1 and R0) select one of the four registers that is to be acted upon when a register oriented instruction is issued. Bits 0 and 1 are defined to be 0. Page 5 of 21 X9429 Four of the seven instructions end with the transmission of the instruction byte. The basic sequence is illustrated in Figure 3. These two-byte instructions exchange data between the Wiper Counter Register and one of the Data Registers. A transfer from a Data Register to a Wiper Counter Register is essentially a write to a static RAM. The response of the wiper to this action will be delayed tWRL. A transfer from the Wiper Counter Register (current wiper position), to a Data Register is a write to non-volatile memory and takes a minimum of tWR to complete. Flow 1. ACK Polling Sequence NON-VOLATILE WRITE COMMAND COMPLETED ENTER ACK POLLING ISSUE START Four instructions require a three-byte sequence to complete. These instructions transfer data between the host and the X9429; either between the host and one of the Data Registers or directly between the host and the Wiper Counter Register. These instructions are: ISSUE SLAVE ADDRESS ISSUE STOP ACK RETURNED? NO YES NO FURTHER OPERATION? YES ISSUE INSTRUCTION ISSUE STOP PROCEED PROCEED SCL SDA S T A R T 0 1 0 1 A3 A2 0 A0 A C K I3 I2 I1 I0 R1 R0 0 0 A C K S T O P FIGURE 3. TWO-BYTE INSTRUCTION SEQUENCE FN8248 Rev 4.00 October 16, 2015 Page 6 of 21 X9429 TABLE 1. INSTRUCTION SET INSTRUCTION SET INSTRUCTION I3 I2 I1 I0 R1 R0 X1 X0 Read Wiper Counter Register 1 0 0 1 0 0 0 0 Read the contents of the Wiper Counter Register Write Wiper Counter Register 1 0 1 0 0 0 0 0 Write new value to the Wiper Counter Register Read Data Register 1 0 1 1 1/0 1/0 0 0 Read the contents of the Data Register pointed to by R1 - R0 Write Data Register 1 1 0 0 1/0 1/0 0 0 Write new value to the Data Register pointed to by R1 - R0 XFR Data Register to Wiper Counter Register 1 1 0 1 1/0 1/0 0 0 Transfer the contents of the Data Register pointed to by R1 - R0 to its Wiper Counter Register XFR Wiper Counter Register to Data Register 1 1 1 0 1/0 1/0 0 0 Transfer the contents of the Wiper Counter Register to the Data Register pointed to by R1 - R0 Increment/Decrement Wiper Counter Register 0 0 1 0 0 0 0 0 Enable Increment/decrement of the Wiper Counter Register OPERATION selected wiper up and/or down in one segment steps; thereby, providing a fine tuning capability to the host. For each SCL clock pulse (tHIGH) while SDA is HIGH, the selected wiper will move one resistor segment towards the VH/RH terminal. Similarly, for each SCL clock pulse while SDA is LOW, the selected wiper will move one resistor segment towards the VL/RL terminal. A detailed illustration of the sequence and timing for this operation are shown in Figures 5 and 6 respectively. Read Wiper Counter Register (read the current wiper position of the selected pot), write Wiper Counter Register (change current wiper position of the selected pot), read Data Register (read the contents of the selected nonvolatile register) and write Data Register (write a new value to the selected Data Register). The sequence of operations is shown in Figure 4. The Increment/Decrement command is different from the other commands. Once the command is issued and the X9429 has responded with an acknowledge, the master can clock the NOTE: (1)1/0 = data is one or zero SCL SDA 0 S T A R T 1 0 1 A3 A2 0 A0 A C K I3 I2 I1 I0 R1 R0 0 0 A C K 0 0 D5 D4 D3 D2 D1 D0 A C K FIGURE 4. THREE-BYTE INSTRUCTION SEQUENCE S T O P SCL SDA S T A R T 0 1 0 1 A3 A2 0 A0 A C K I3 I2 I1 I0 R1 R0 0 0 A C K I N C 1 I N C 2 I N C n D E C 1 D E C n S T O P FIGURE 5. INCREMENT/DECREMENT INSTRUCTION SEQUENCE FN8248 Rev 4.00 October 16, 2015 Page 7 of 21 X9429 INC/DEC CMD ISSUED TWRID SCL SDA VOLTAGE OUT VW/RW FIGURE 6. INCREMENT/DECREMENT TIMING LIMITS SCL FROM MASTER 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER ACKNOWLEDGE START FIGURE 7. ACKNOWLEDGE RESPONSE FROM RECEIVER FN8248 Rev 4.00 October 16, 2015 Page 8 of 21 X9429 SERIAL DATA PATH SERIAL BUS INPUT FROM INTERFACE CIRCUITRY REGISTER 0 REGISTER 1 8 REGISTER 2 6 PARALLEL BUS INPUT WIPER COUNTER REGISTER (WCR) REGISTER 3 C O U N T E R D E C O D E INC/DEC LOGIC IF WCR = 00[H] THEN VW/RW = VL/RL IF WCR = 3F[H] THEN VW/RW = VH/RH VH/RH UP/DN UP/DN MODIFIED SCL VL/RL CLK VW/RW FIGURE 8. DETAILED POTENTIOMETER BLOCK DIAGRAM Detailed Operation The potentiometer has a Wiper Counter Register and four Data Registers. A detailed discussion of the register organization and array operation follows. Wiper Counter Register The X9429 contains a Wiper Counter Register. The Wiper Counter Register can be envisioned as a 6-bit parallel and serial load counter with its outputs decoded to select one of sixty-four switches along its resistor array. The contents of the WCR can be altered in four ways: it may be written directly by the host via the write Wiper Counter Register instruction (serial load); it may be written indirectly by transferring the contents of one of four associated Data Registers via the XFR Data Register instruction (parallel load); it can be modified one step at a time by the Increment/Decrement instruction. Finally, it is loaded with the contents of its Data Register zero (DR0) upon power-up. The WCR is a volatile register; that is, its contents are lost when the X9429 is powered-down. Although the register is automatically loaded with the value in DR0 upon power-up, it should be noted this may be different from the value present at power-down. Data Registers Wiper Counter Register. It should be noted all operations changing data in one of these registers is a nonvolatile operation and will take a maximum of 10ms. If the application does not require storage of multiple settings for the potentiometer, these registers can be used as regular memory locations that could possibly store system parameters or user preference data. Register Descriptions DATA REGISTERS, (6-BIT), NON-VOLATILE D5 D4 D3 D2 D1 D0 NV NV NV NV NV NV (MSB) (LSB) FOUR 6-BIT DATA REGISTERS FOR EACH XDCP. {D5~D0}: These bits are for general purpose not volatile data storage or for storage of up to four different wiper values. The contents of Data Register 0 are automatically moved to the Wiper Counter Register on power-up. WIPER COUNTER REGISTER, (6-BIT), VOLATILE WP5 WP4 WP3 WP2 WP1 V V V V V (MSB) WP0 V (LSB) The potentiometer has four nonvolatile Data Registers. These can be read or written directly by the host and data can be transferred between any of the four Data Registers and the FN8248 Rev 4.00 October 16, 2015 Page 9 of 21 X9429 ONE 6-BIT WIPER COUNTER REGISTER FOR EACH XDCP. power-up by the value in Data Register 0. The contents of the WCR can be loaded from any of the other Data Register or directly. The contents of the WCR can be saved in a DR. {D5~D0}: These bits specify the wiper position of the respective XDCP. The Wiper Counter Register is loaded on Instruction Format NOTES: 1. “MACK”/”SACK”: stands for the acknowledge sent by the master/slave. 2. A3 ~ A0”: stands for the device addresses sent by the master. 3. X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition. 4. “I”: stands for the increment operation, SDA held high during active SCL phase (high). 5. “D”: stands for the decrement operation, SDA held low during active SCL phase (high). Read Wiper Counter Register (WCR) S T A R T DEVICE TYPE IDENTIFIER 0 1 0 1 DEVICE ADDRESSES A 3 A 2 0 A 0 S A C K INSTRUCTION OPCODE 1 0 0 1 0 0 0 0 S A C K WIPER POSITION (SENT BY SLAVE ON SDA) 0 0 M S W W W W W W A T P P P P P P C O 5 4 3 2 1 0 K P Write Wiper Counter Register (WCR) S T A R T DEVICE TYPE IDENTIFIER 0 1 0 1 DEVICE ADDRESSES A 3 A 2 0 A 0 S A C K INSTRUCTION OPCODE 1 0 1 0 0 0 0 0 WIPER POSITION (SENT BY MASTER ON SDA) S S A 0 0 W W W W W W A P P P P P P C C 5 4 3 2 1 0 K K S T O P Read Data Register (DR) S T A R T DEVICE TYPE IDENTIFIER 0 1 0 1 DEVICE ADDRESSES A 3 A 2 0 A 0 S A C K INSTRUCTION REGISTER OPCODE ADDRESSES 1 0 1 1 R 1 R 0 0 0 S A C K WIPER POSITION/DATA (SENT BY SLAVE ON SDA) 0 0 M S W W W W W W A T P P P P P P C O 5 4 3 2 1 0 K P Write Data Register (DR) S T A R T DEVICE TYPE IDENTIFIER 0 1 0 1 DEVICE ADDRESSES A 3 FN8248 Rev 4.00 October 16, 2015 A 2 0 A 0 S A C K INSTRUCTION REGISTER OPCODE ADDRESSES 1 1 0 0 R 1 R 0 0 0 S A C K WIPER POSITION/DATA (SENT BY MASTER ON SDA) 0 HIGH-VOLTAGE WRITE CYCLE S S 0 W W W W W W A T P P P P P P C O 5 4 3 2 1 0 K P Page 10 of 21 X9429 XFR Data Register (DR) to Wiper Counter Register (WCR) S T A R T DEVICE TYPE IDENTIFIER 0 1 0 DEVICE ADDRESSES 1 A 3 A 2 0 S A C K A 0 INSTRUCTION OPCODE REGISTER ADDRESSES 1 R 1 1 0 1 R 0 0 0 S S A T C O K P XFR Wiper Counter Register (WCR) to Data Register (DR) S T A R T DEVICE TYPE IDENTIFIER 0 1 0 DEVICE S S INSTRUCTION REGISTER OPCODE ADDRESSES ADDRESSES A A A A 0 A C 1 1 1 0 R R 0 0 C K 3 2 0 K 1 0 1 HIGH-VOLTAGE WRITE CYCLE S T O P Increment/Decrement Wiper Counter Register (WCR) S T A R T DEVICE TYPE IDENTIFIER 0 1 0 1 DEVICE ADDRESSES A3 A2 S A A0 C K 0 INSTRUCTION OPCODE 0 0 1 0 0 0 0 0 S A C K INCREMENT/DECREMENT (SENT BY MASTER ON SDA) I/ D I/ D . . . . I/ D I/ D S T O P Symbol Table WAVEFORM INPUTS OUTPUTS MUST BE STEADY WILL BE STEADY MAY CHANGE FROM LOW TO HIGH WILL CHANGE FROM LOW TO HIGH MAY CHANGE FROM HIGH TO LOW WILL CHANGE FROM HIGH TO LOW DON’T CARE: CHANGES ALLOWED CHANGING: STATE NOT KNOWN N/A CENTER LINE IS HIGH IMPEDANCE Guidelines for Calculating Typical Values of Bus Pull-Up Resistors RESISTANCE (k) 120 100 80 60 RMIN = VCC MAX =1.8kW IOL MIN RMAX = TR CBUS MAX. RESISTANCE 40 20 MIN. RESISTANCE 0 0 20 40 60 80 100 120 BUS CAPACITANCE (PF) FN8248 Rev 4.00 October 16, 2015 Page 11 of 21 X9429 Absolute Maximum Ratings Thermal Information Supply Voltage (VCC Limits) X9429 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10% X9429-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Voltage on SCL, SDA any address input with respect to VSS: . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V V = | (VH - VL) | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V Thermal Resistance (Typical, Note 1) IW (10 s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA JA (°C/W) 14 Lead TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 16 Lead SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65C to +135C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Temperature Range Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C Industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details Analog Specifications (Over recommended operating conditions unless otherwise stated.) LIMITS SYMBOL PARAMETER TEST CONDITIONS End-to-End Resistance Tolerance IW Wiper Current Wiper Resistance VTERM MAX. (Note 7) UNIT +20 % 50 mW +25°C, each pot ±3 mA Wiper current = VCC/RTOTAL, VCC = 5V 150 250  Wiper current = VCC/RTOTAL, VCC = 3V 400 1000  VCC V Voltage on Any VH/RH or VL/RL Pin VSS = 0V Noise Ref: 1kHz VSS Resolution (Note 4) CH/CL/CW TYP. -20 Power Rating RW MIN. (Note 7) Absolute Linearity (Note 1) Vw(n)(actual) - Vw(n)(expected) Relative Linearity (Note 2) Vw(n + 1) - [Vw(n) + MI] -120 dBV 1.6 % ±1 MI (Note 3) ±0.2 MI (Note 3) Temperature Coefficient of RTOTAL 300 ppm/C Ratiometric Temperature Coefficient ±20 ppm/°C 10/10/25 pF Potentiometer Capacitances DC Electrical Specifications See Circuit #3, Spice Macromodel (Over the recommended operating conditions unless otherwise specified.) LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN. (Note 7) TYP MAX. (Note 7) UNIT ICC1 VCC Supply Current (nonvolatile write) fSCL = 400kHz, SDA = Open, Other Inputs = VSS 3.5 mA ICC2 VCC Supply Current (move wiper, write, read) fSCL = 400kHz, SDA = Open, Other Inputs = VSS 170 µA ISB VCC Current (standby) SCL = SDA = VCC, Addr. = VSS 3 µA ILI Input Leakage Current VIN = VSS to VCC 10 µA FN8248 Rev 4.00 October 16, 2015 Page 12 of 21 X9429 LIMITS SYMBOL PARAMETER MIN. (Note 7) TEST CONDITIONS TYP MAX. (Note 7) UNIT 10 µA ILO Output Leakage Current VOUT = VSS to VCC VIH Input HIGH Voltage VCC x 0.7 VCC x 0.5 V VIL Input LOW Voltage -0.5 VCC x 0.1 V VOL Output LOW voltage 0.4 V IOL = 3mA ENDURANCE AND DATA RETENTION PARAMETER MIN. Minimum Endurance 100,000 Data Retention 100 UNIT Data changes per bit per register Years CAPACITANCE TYP UNIT TEST CONDITIONS CI/O (Note 5) SYMBOL Input/output capacitance (SDA) TEST 8 pF VI/O = 0V CIN (Note 5) Input capacitance (A0, A2,and A3 and SCL) 6 pF VIN = 0V POWER-UP TIMING SYMBOL tRVCC (Note 6) PARAMETER MIN VCC Power-up ramp rate TYP 0.2 MAX UNIT 50 V/ms NOTES: 1. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. 2. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is a measure of the error in step size. 3. MI = RTOT/63 or (RH - RL)/63, single pot 4. Typical = individual array resolutions. 5. Limits established by characterization and are not production tested. 6. Sample tested only. 7. Parts are 100% tested at +25°C. Over temperature limits established by characterization and are not production tested. Power-up and Power-down Requirements There are no restrictions on the power-up or power-down conditions of VCC and the voltage applied to the potentiometer pins provided that VCC is always more positive than or equal to VH, VL, and VW, i.e., VCC  VH, VL, VW. The VCC ramp rate spec is always in effect. AC Test Conditions Input pulse levels VCC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level VCC x 0.5 Equivalent AC Load Circuit Circuit #3 SPICE Macro Model 5V 2.7V RTOTAL 1533 RH CL CH SDA OUTPUT 100pF 100pF CW 10pF RL 10pF 25pF RW FN8248 Rev 4.00 October 16, 2015 Page 13 of 21 X9429 AC TIMING (Over recommended operating conditions) SYMBOL PARAMETER MIN (Note 7) MAX (Note 7) UNIT 400 kHz fSCL Clock Frequency tCYC Clock Cycle Time 2500 ns tHIGH Clock High Time 700 ns tLOW Clock Low Time 1300 ns tSU:STA Start Setup Time 600 ns tHD:STA Start Hold Time 600 ns tSU:STO Stop Setup Time 600 ns tSU:DAT SDA Data Input Setup Time 100 ns tHD:DAT SDA Data Input Hold Time 30 ns tR SCL and SDA Rise Time 300 ns tF SCL and SDA Fall Time 300 ns tAA SCL low to SDA Data Output Valid Time 900 ns tDH SDA Data Output Hold Hime 50 ns Noise Suppression Time Constant at SCL and SDA Inputs 50 ns 1300 ns tI tBUF Bus Free Time (Prior to Any Transmission) tSU:WPA WP, A0, A2, A3 Setup Time 0 ns tHD:WPA WP, A0, A2, A3 Hold Time 0 ns HIGH-VOLTAGE WRITE CYCLE TIMING SYMBOL PARAMETER High-Voltage Write Cycle Time (Store Instructions) tWR TYP MAX UNIT 5 10 ms XDCP TIMING MAX (Note 7) UNIT Wiper Response Time After the Third (last) Power Supply is Stable 10 µs tWRL Wiper Response Time After Instruction Issued (All Load Instructions) 10 µs tWRID Wiper Response Time From an Active SCL/SCK Edge (Increment/Decrement Instruction) 10 µs SYMBOL tWRPO PARAMETER FN8248 Rev 4.00 October 16, 2015 MIN (Note 7) Page 14 of 21 X9429 Timing Diagrams Start and Stop Timing (START) (STOP) tF tR SCL tSU:STA tHD:STA tSU:STO tF tR SDA Input Timing tCYC tHIGH SCL tLOW SDA tSU:DAT tHD:DAT tBUF Output Timing SCL SDA tDH tAA XDCP Timing (for All Load Instructions) (STOP) SCL SDA LSB tWRL VW/RW FN8248 Rev 4.00 October 16, 2015 Page 15 of 21 X9429 XDCP Timing (for Increment/Decrement Instruction) SCL SDA WIPER REGISTER ADDRESS INC/DEC INC/DEC tWRID VW/RW Write Protect and Device Address Pins Timing (START) (STOP) SCL ... (ANY INSTRUCTION) ... SDA ... tSU:WPA tHD:WPA WP A0, A2, A3 Applications information Basic Configurations of Electronic Potentiometers +VR VR VW/RW I THREE TERMINAL POTENTIOMETER; VARIABLE VOLTAGE DIVIDER FN8248 Rev 4.00 October 16, 2015 TWO TERMINAL VARIABLE RESISTOR; VARIABLE CURRENT Page 16 of 21 X9429 Application Circuits NONINVERTING AMPLIFIER VS VOLTAGE REGULATOR + VO – VIN VO (REG) 317 R1 R2 Iadj R1 R2 VO = (1+R2/R1)VS VO (REG) = 1.25V (1+R2/R1)+Iadj R2 OFFSET VOLTAGE ADJUSTMENT R1 COMPARATOR WITH HYSTERESIS R2 VS VS 100k – + – VO VO + TL072 +5V FN8248 Rev 4.00 October 16, 2015 10k } 10k } 10k R1 R2 VUL = {R1/(R1+R2)} VO(max) VLL = {R1/(R1+R2)} VO(min) Page 17 of 21 X9429 Application Circuits (continued) ATTENUATOR FILTER C VS + R2 R1 VS VO – – R VO + R3 R4 R2 All RS = 10k R1 GO = 1 + R2/R1 fc = 1/(2RC) VO = G VS -1/2 G  +1/2 R1 R2 } VS } INVERTING AMPLIFIER EQUIVALENT L-R CIRCUIT R2 C1 VS – + VO + – R1 ZIN VO = G VS G = - R2/R1 R3 ZIN = R2 + s R2 (R1 + R3) C1 = R2 + s Leq (R1 + R3) >> R2 FUNCTION GENERATOR C R2 – R1 – + } RA + } RB FREQUENCY µR1, R2, C AMPLITUDE µRA, RB FN8248 Rev 4.00 October 16, 2015 Page 18 of 21 X9429 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION October 16, 2015 FN8248.4 CHANGE Updated the Ordering Information table on page 2. Added Revision History and About Intersil sections. Updated Package Outline Drawing M14.173 to the latest revision. Changes are as follows: -Updated drawing to remove table and added land pattern. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support. FN8248 Rev 4.00 October 16, 2015 Page 19 of 21 X9429 Package Outline Drawing M14.173 14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP) Rev 3, 10/09 A 1 3 5.00 ±0.10 SEE DETAIL "X" 8 14 6.40 PIN #1 I.D. MARK 4.40 ±0.10 2 3 1 0.20 C B A 7 B 0.65 0.09-0.20 TOP VIEW END VIEW 1.00 REF 0.05 H C 0.90 +0.15/-0.10 1.20 MAX SEATING PLANE 0.25 +0.05/-0.06 0.10 C 0.10 GAUGE PLANE 0.25 5 0°-8° 0.05 MIN 0.15 MAX CBA SIDE VIEW 0.60 ±0.15 DETAIL "X" (1.45) NOTES: 1. Dimension does not include mold flash, protrusions or gate burrs. (5.65) Mold flash, protrusions or gate burrs shall not exceed 0.15 per side. 2. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25 per side. 3. Dimensions are measured at datum plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Dimension does not include dambar protrusion. Allowable protrusion shall be 0.80mm total in excess of dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm. (0.65 TYP) (0.35 TYP) TYPICAL RECOMMENDED LAND PATTERN FN8248 Rev 4.00 October 16, 2015 6. Dimension in ( ) are for reference only. 7. Conforms to JEDEC MO-153, variation AB-1. Page 20 of 21 X9429 Small Outline Plastic Packages (SOIC) M16.3 (JEDEC MS-013-AA ISSUE C) N 16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INDEX AREA H 0.25(0.010) M B M INCHES E -B- 1 2 3 L SEATING PLANE -A- A D h x 45° -C- e A1 B 0.25(0.010) M C 0.10(0.004) C A M SYMBOL MIN MAX MIN MAX NOTES A 0.0926 0.1043 2.35 2.65 - A1 0.0040 0.0118 0.10 0.30 - B 0.013 0.0200 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 - D 0.3977 0.4133 10.10 10.50 3 E 0.2914 0.2992 7.40 7.60 4 e  B S 0.050 BSC 1.27 BSC - H 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 N  NOTES: MILLIMETERS 16 0° 16 8° 0° 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 7 8° Rev. 1 6/05 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. © Copyright Intersil Americas LLC 2005-2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8248 Rev 4.00 October 16, 2015 Page 21 of 21