DATASHEET
OBSOLETE PRODUCT
POSSIBLE SUBSTITUTE PRODUCT
X9418
X9448
FN8201
Rev 0.00
April 18, 2005
Mixed Signal with 2-Wire Interface Dual Digitally Controlled Potentiometer
(XDCP™) & Voltage Comparator
FEATURES
DESCRIPTION
• Two digitally controlled potentiometers and two
voltage comparators in one package
• 2-wire serial interface
• Register oriented format
—Direct read/write wiper position
—Store as many as four positions per pot
• Fast response comparator
• Enable, latch, or shutdown comparator outputs
through ACR
• Auto-recall of WCR and ACR data from R0
• Hardware write protection, WP
• Separate analog and digital/system supplies
• Direct write cell
—Endurance–100,000 data changes per bit per
register
—Register data retention–100 years
• 16-bytes of EEPROM memory
• Power saving feature and low noise
• Two 10k or two 2.5k potentiometers
• Resolution: 64 taps each pot
• 24-lead TSSOP and 24-lead SOIC packages
The X9448 integrates two nonvolatile digitally controlled potentiometers (XDCP) and two voltage comparators on a CMOS monolithic microcircuit.
The X9448 contains two resistor arrays, each composed of 63 resistive elements. Between each element and at either end are tap points accessible to the
wiper elements. The position of the wiper element on
the array is controlled by the user through the two wire
serial bus interface.
Each potentiometer has an associated voltage comparator. The comparator compares the external input
voltage VNI with the wiper voltage VW and sets the output voltage level to a logic high or low.
Each resistor array and comparator has associated
with it a wiper counter register (WCR), analog control
register (ACR), and eight 6-bit data registers that can
be directly written and read by the user. The contents
of the wiper counter register controls the position of
the wiper on the resistor array. The contents of the
analog control register controls the comparator and its
output. The potentiometer is programmed with a
2-wire serial interface.
BLOCK DIAGRAM
VH (0,1)
(R0-R3)0,1
WCR0,1
WP
VL (0,1)
VW (0,1)
SCL
SDA
Interface
A1
and
Control
A2
Circuitry
A0
VNI (0,1)
A3
(R0-R3)0,1
FN8201 Rev 0.00
April 18, 2005
ACR0,1
+
–
VOUT (0,1)
Page 1 of 19
X9448
PIN DESCRIPTIONS
Hardware Write Protect Input WP
Host Interface Pins
The WP pin when low prevents nonvolatile writes to the
wiper counter and analog control registers.
Serial Clock (SCL)
Analog Supplies V+, V-
The SCL input is used to clock data into and out of the
X9448.
The analog supplies V+, V- are the supply voltages for the
XDCP analog section and the voltage comparators.
Serial Data (SDA)
System Supply VCC and Ground VSS
SDA is a bidirectional pin used to transfer data into and
out of the device. It is an open drain output and may be
wire-ORed with any number of open drain or open collector outputs. An open drain output requires the use of
a pull-up resistor. For selecting typical values, refer to
the guidelines for calculating typical values on the bus
pull-up resistors graph.
The system supply VCC and its reference VSS is used to
bias the interface and control circuits.
PIN CONFIGURATION
SOIC
VCC
1
Device Address (A0 - A3)
24
VL0
2
23
The address inputs are used to set the least significant 4
bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with the
X9448. A maximum of 16 devices may share the same
2-wire serial bus.
VOUT0
VH0
3
22
VNI0
VW0
4
21
NC
A2
5
20
A0
WP
6
19
NC
SDA
7
18
A3
A1
8
17
SCL
X9448
V+
VL1
9
16
NC
10
VH (VH0 - VH1), VL (VL0 - VL1)
VH1
15
VNI1
VW1
11
The VH and VL inputs are equivalent to the terminal connections on either end of a mechanical potentiometer.
14
VOUT1
VSS
12
13
V-
1
24
WP
2
23
A2
Potentiometer Pins
VW (VW0 - VW1)
The wiper output is equivalent to the wiper output of a
mechanical potentiometer and is connected to the
inverting input of the voltage comparator.
Comparator and Device Pins
Voltage Input VNI0, VNI1
VNI0 and VNI1 are the input voltages to the plus (noninverting) inputs of the two comparators.
Buffered Voltage Outputs VOUT0, VOUT1
The VOUT0, and VOUT1 are the buffered voltage
comparator outputs enabled by respective bits in the
volatile analog control register.
FN8201 Rev 0.00
April 18, 2005
TSSOP
SDA
A1
VL1
3
VH1
22
VW0
4
VW1
21
VH0
5
20
VL0
VSS
6
19
VCC
18
NC
X9448
NC
7
V-
8
17
V+
VOUT1
9
VNI1
16
VOUT0
10
15
VNI0
SCL
11
14
A0
A3
12
13
NC
Page 2 of 19
X9448
Start Condition
PIN NAMES
Symbol
Description
SCL
Serial Clock
SDA
Serial Data
A0 - A3
Device Address
VH0 - VH1,
VL0 - VL1
Potentiometers (terminal equivalent)
VW0 - VW1
Potentiometers (wiper equivalent)
VNI0, VNI1
Comparator Input Voltages
VOUT0, VOUT1
Buffered Comparator Outputs
WP
Hardware Write Protection
V+,V-
Analog and Voltage Comparator
Supplies
VCC
System/Digital Supply Voltage
VSS
System Ground
NC
No Connection
PRINCIPLES OF OPERATION
The X9448 is a highly integrated microcircuit incorporating two resistor arrays, two voltage comparators and
their associated registers and counters; and the serial
interface logic providing direct communication between
the host and the digitally-controlled potentiometers and
voltage comparators.
Serial Interface
The X9448 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as
the receiver. The device controlling the transfer is a
master and the device being controlled is the slave. The
master will always initiate data transfers and provide the
clock for both transmit and receive operations. Therefore, the X9448 will be considered a slave device in all
applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW periods (tLOW). SDA state changes during
SCL HIGH are reserved for indicating start and stop
conditions.
FN8201 Rev 0.00
April 18, 2005
All commands to the X9448 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH (tHIGH). The X9448 continuously
monitors the SDA and SCL lines for the start condition
and will not respond to any command until this condition
is met.
Stop Condition
All communications must be terminated by a stop condition, which is a LOW to HIGH transition of SDA while
SCL is HIGH.
Acknowledge
Acknowledge is a software convention used to provide a
positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW to
acknowledge that it successfully received the eight bits
of data.
The X9448 will respond with an acknowledge after recognition of a start condition and its slave address and
once again after successful receipt of the command
byte. If the command is followed by a data byte the
X9448 will respond with a final acknowledge.
Array Description
The X9448 is comprised of two resistor arrays and two
voltage comparators. Each array contains 63 discrete
resistive segments that are connected in series. The
physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (VH and VL
inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper (VW)
output. Within each individual array only one switch may
be turned on at a time. These switches are controlled by
a volatile wiper counter register (WCR). The six bits of
the WCR are decoded to select, and enable, one of
sixty-four switches.
The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
data registers into the WCR. These data registers and
the WCR can be read and written by the host system.
Page 3 of 19
X9448
Flow 1. ACK Polling Sequence
Voltage Comparator
The comparator compares the wiper voltage VW with the
external input voltage VNI. The comparator and its logic
level output are controlled by the Shutdown, Latch, and
Enable bits of the analog control register (ACR). Enable
connects the comparator output to the VOUT pin, Latch
memorizes the output logic state, and Shutdown
removes the analog section supply voltages to save
power. The analog control register is programmed using
the two wire serial interface.
Nonvolatile Write
Command Completed
Enter ACK Polling
Issue
START
Issue Slave
Address
The ACR may be written directly, or it can be changed
by transferring the contents of one of four associated
data registers into the ACR. These data registers and
the ACR may be read and written by the host system.
ACK
Returned?
INSTRUCTIONS AND PROGRAMMING
Further
Operation
Figure 1. Address/Identification Byte Format
Device Type
Identifier
0
1
A3
A2
A1
A0
Device Address
The next four bits of the slave address are the device
address. The physical device address is defined by the
state of the A0 - A3 inputs. The X9448 compares the
serial data stream with the address input state; a successful compare of all four address bits is required for
the X9448 to respond with an acknowledge. The A0 - A3
inputs can be actively driven by CMOS input signals or
tied to VCC or VSS.
Acknowledge Polling
The disabling of the inputs, during the internal nonvolatile write operation, can be used to take advantage of the
typical 5ms EEPROM write cycle time. Once the stop
condition is issued to indicate the end of the nonvolatile
write command the X9448 initiates the internal write
cycle. ACK polling (Flow 1) can be initiated immediately.
This involves issuing the start condition followed by the
device slave address. If the X9448 is still busy with the
write operation no ACK will be returned. If the X9448 has
completed the write operation an ACK will be returned
and the master can then proceed with the next operation.
FN8201 Rev 0.00
April 18, 2005
NO
YES
Following a start condition the master must output the
address of the slave it is accessing. The most significant
four bits of the slave address are the device type identifier (refer to Figure 1 below). For the X9448 this is fixed
as 0101[B].
1
NO
YES
Device Addressing
0
Issue STOP
Issue
Instruction
Issue STOP
PROCEED
PROCEED
Instruction Structure
The byte following the address contains the instruction
and register pointer information. The four most significant bits are the instruction. The next four bits point to
one of two pots or one of two voltage comparators and
when applicable they point to one of four associated registers. The format is shown below in Figure 2.
Figure 2. Instruction Byte Format
Register
Select
I3
I2
I1
Instructions
I0
R1
R0
P1
P0
WCR and ACR Select
The four high order bits define the instruction. The next
two bits (R1 and R0) select one of the four registers that
is to be acted upon when a register oriented instruction
is issued. The last two bits (P1 and P0) select which one
of the two potentiometers or which one of the two voltage comparators is to be affected by the instruction.
Four of the nine instructions end with the transmission of
the instruction byte. The basic sequence is illustrated in
Figure 3. These two-byte instructions exchange data
between the wiper counter register or analog control register and one of the data registers. A transfer from a data
register to a wiper counter register or analog control register is essentially a write to a static RAM. The response
Page 4 of 19
X9448
of the wiper to this action will be delayed tSTPWV. A
transfer from the Wiper Counter Register current wiper
position to a data register is a write to nonvolatile memory and takes a minimum of tWR to complete. The transfer can occur between one of the two potentiometers or
one of the two voltage comparators and one of its associated registers; or it may occur globally, wherein the
transfer occurs between both of the potentiometers and
voltage comparators and one of their associated registers.
Four instructions require a three-byte sequence to complete. The basic sequence is illustrated in Figure 4. These
instructions transfer data between the host and the
X9448; either between the host and one of the data registers or directly between the host and the wiper counter
and analog control registers. These instructions are: read
wiper counter register or analog control register, read the
current wiper position of the selected pot or the comparator control bits, Write wiper counter register or analog con-
trol register, i.e. change current wiper position of the
selected pot or control the voltage comparator; read data
register, read the contents of the selected nonvolatile register; write data register, write a new value to the selected
data register. The bit structures of the instructions are
shown in Figure 6.
The increment/decrement command is different from the
other commands. Once the command is issued and the
X9448 has responded with an acknowledge, the master
can clock the selected wiper up and/or down in one segment steps; thereby, providing a fine tuning capability to
the host. For each SCL clock pulse (tHIGH) while SDA is
HIGH, the selected wiper will move one resistor segment
towards the VH terminal. Similarly, for each SCL clock
pulse while SDA is LOW, the selected wiper will move
one resistor segment towards the VL terminal. A detailed
illustration of the sequence for this operation is shown in
Figure 5.
Figure 3. Two-Byte Command Sequence
SCL
SDA
S
T
A
R
T
0
1
0
1
A3
A2
A1
A0
A
C
K
I3
I2
I1
I0
R1 R0 P1 P0
A
C
K
S
T
O
P
Figure 4. Three-Byte Command Sequence
SCL
SDA
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0 A
C
K
I3
I2
I1 I0
P1 P0 R1 R0 A
C
K
D5 D4 D3 D2 D1 D0
A
C
K
S
T
O
P
Figure 5. Increment/Decrement Command Sequence
SCL
SDA
X
S
T
A
R
T
0
1
FN8201 Rev 0.00
April 18, 2005
0
1
A3 A2 A1 A0
A
C
K
I3
I2
I1
I0
X
P1 P0 R1 R0 A
C
K
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
S
T
O
P
Page 5 of 19
X9448
Figure 6. Instruction Set
Read Wiper Counter Register (WCR) or Analog Control Register (ACR)
Read the contents of the Wiper Counter Register or Analog Control Register pointed to by P1 - P0.
S device type
device
T
identifier
addresses
A
R 0 1 0 1 A A A A
3 2 1 0
T
instruction WCR/ACR
S
opcode
addresses
A
C
P P
K 1 0 0 1 0 0 1 0
register data
S
(sent by slave on SDA)
A
C
D D D D D D
K 0 0 5 4 3 2 1 0
M
A
C
K
S
T
O
P
P1 P0: 00 - WCR0, 01 - WCR1
P1 P0: 10 - ACR0, 11 - ACR1
Write Wiper Counter Register (WCR) or Analog Control Register (ACR)
Write new value to the Wiper Counter Register or Analog Control Register pointed to by P1 - P0.
S device type
device
T
identifier
addresses
A
R 0 1 0 1 A A A A
3 2 1 0
T
instruction WCR/ACR
S
opcode
addresses
A
C
P P
1 0 1 0 0 0
K
1 0
register data
S
(sent by master on SDA)
A
C
D D D D D D
0 0
K
5 4 3 2 1 0
S
A
C
K
S
T
O
P
P1 P0: 00 - WCR0, 01 - WCR1
P1 P0: 10 - ACR0, 11 - ACR1
Read Data Register (DR)
Read the contents of the Register pointed to by P1 - P0 and R1 - R0.
S device type
device
instruction WCR/ACR/DR
register data
S
S
T identifier
addresses
opcode
addresses
(sent by master on SDA)
A
A
A
C
C
R R P P
D D D D D D
R 0 1 0 1 A A A A
1 0 1 1
0 0
3 2 1 0 K
1 0 1 0 K
5 4 3 2 1 0
T
M
A
C
K
S
T
O
P
R1 R0: 00 - R0, 10 - R1
01 - R2, 11 - R3
Definitions:
SACK – Slave acknowledge, MACK – Master acknowledge, I/O – Increment/Decrement (I/O), R – Register,
P – Potentiometer
FN8201 Rev 0.00
April 18, 2005
Page 6 of 19
X9448
Write Data Register (DR)
Write new value to the Register pointed to by P1 - P0 and R1 - R0.
S device type
device
instruction WCR/ACR/DR
register data
S
S
T identifier
addresses
opcode
addresses
(sent by master on SDA)
A
A
A
C
C
R R P P
D D D D D D
R 0 1 0 1 A A A A
1 1 0 0
0 0
3 2 1 0 K
1 0 1 0 K
5 4 3 2 1 0
T
S
A
C
K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
Transfer Data Register to Wiper Counter Register or Analog Control Register
Transfer the contents of the Register pointed to by R1 - R0 to the WCR or ACR pointed to by P1 - P0.
S device type
device
T
identifier
addresses
A
R 0 1 0 1 A A A A
3 2 1 0
T
instruction WCR/ACR/DR
S
S S
opcode
addresses
A
A T
C
C
O
R R P P
K 1 1 0 1 1 0 1 0 K P
Transfer Wiper Counter or Analog Control Register to Data Register
Transfer the contents of the WCR or ACR pointed to by P1 - P0 to the Register pointed to by R1 - R0.
S device type
device
T
identifier
addresses
A
R 0 1 0 1 A A A A
3 2 1 0
T
instruction WCR/ACR/DR
S
S S
opcode
addresses
A
A T
C
C
O
R R P P
1 1 1 0
K
1 0 1 0 K P
HIGH-VOLTAGE
WRITE CYCLE
Global Transfer Data Register to Wiper Counter or Analog Control Register
Transfer the contents of all four Data Registers pointed to by R1 - R0 to their respective WCR or ACR.
S device type
device
T
identifier
addresses
A
R 0 1 0 1 A A A A
3 2 1 0
T
instruction
DR
S
opcode
addresses
A
C
R R
K 0 0 0 1 1 0 0 0
S
A
C
K
S
T
O
P
Global Transfer Wiper Counter or Analog Control Register to Data Register
Transfer the contents of all WCRs and ACRs to their respective data Registers pointed to by R1 - R0.
S device type
device
T identifier
addresses
A
R 0 1 0 1 A A A A
3 2 1 0
T
instruction
DR
S
opcode
addresses
A
C
R R
1 0 0 0
0 0
K
1 0
S
A
C
K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
Increment/Decrement Wiper Counter Register
Enable Increment/decrement of the WCR pointed to by P1 - P0.
S device type
device
T
identifier
addresses
A
R 0 1 0 1 A A A A
3 2 1 0
T
instruction
WCR
S
opcode
addresses
A
C
P P
K 0 0 1 0 0 0 1 0
increment/decrement
S
(sent by master on SDA)
A
C I/ I/
I/ I/
K D D . . . . D D
S
T
O
P
P1 P0: 00 or 01 only.
FN8201 Rev 0.00
April 18, 2005
Page 7 of 19
X9448
REGISTERS OPERATION
Both XDCP potentiometers and voltage comparators
share the serial interface and share a common architecture. Each potentiometer and voltage comparator is
associated with wiper counter and analog control registers and eight data registers. A detailed discussion of the
register organization and array operation follows.
Wiper Counter (WCR) and Analog Control Registers
(ACR)
The X9448 contains two wiper counter registers one for
each XDCP potentiometer and two analog control registers, one for each of the two voltage comparators. The
wiper counter register is equivalent to a serial-in, parallel-out counter with its outputs decoded to select one of
sixty-four switches along its resistor array. The contents
of the wiper counter register and analog control register
can be altered in four ways: it may be written directly by
the host via the Write WCR instruction (serial load); it
may be written indirectly by transferring the contents of
one of four associated data registers (DR) via the XFR
data register instruction (parallel load); it can be modified
one step at a time by the increment/decrement instruction (WCR only). Finally, it is loaded with the contents of
its data register zero (R0) upon power-up.
The wiper counter and analog control register are volatile registers; that is, their contents are lost when the
X9448 is powered-down. Although the registers are
automatically loaded with the value in R0 upon powerup, it should be noted this may be different from the
value present at power-down.
Programming the ACR is similar to the WCR. However,
the 6 bits in the WCR positions the wiper in the resistor
array while 3 bits in the ACR control the comparator and
its output.
REGISTER DESCRIPTIONS
Wiper Counter Register (WCR)
0
0
WP5 WP4 WP3 WP2 WP1
(volatile)
WP0
(LSB)
WP0-WP5 identify wiper position.
Analog Control Register (ACR)
0
User User User
Shut-bit5 -bit4 -bit3 Latch Enable down
0
(volatile)
(LSB)
Shutdown
“1”
indicates power is connected to the voltage comparator.
“0”
indicates power is not connected to the voltage
comparator.
Enable
“1”
indicates the output buffer of the voltage comparator is enabled.
“0”
indicates the output buffer of the voltage comparator is disabled.
Latch
“1”
indicates the output of the voltage comparator is
memorized or latched.
“0”
indicates the output of the voltage comparator is
not latched.
Userbits—available for user applications
Data Registers (DR, R0 - R3)
Data Registers (DR)
Each potentiometer and each voltage comparator has
four nonvolatile data registers (DR). These can be read
or written directly by the host and data can be transferred between any of the four data registers and the
WCR or ACR. It should be noted all operations changing
data in one of these registers is a nonvolatile operation
and will take a maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer or comparator, these registers can be used as regular memory locations that could
store system parameters or user preference data.
FN8201 Rev 0.00
April 18, 2005
Wiper Position or Analog Control Data or User Data
(Nonvolatile)
Memory Map
WCRO
WCR1
ACR0
ACR1
R0
R0
R0
R0
R1
R1
R1
R1
R2
R2
R2
R2
R3
R3
R3
R3
Page 8 of 19
X9448
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias .................... -65°C to +135°C
Storage temperature ......................... -65°C to +150°C
Voltage on SDA, SCL or any
address input with respect to VSS ........... -1V to +7V
Voltage on any V+ (referenced to VSS) ................ 7V
Voltage on any V- (referenced to VSS) .................. -7V
(V+) - (V-) ............................................................. 10V
Any VH .....................................................................V+
Any VL ......................................................................VLead temperature (soldering, 10 seconds) ........ 300°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Min.
0°C
Max.
+70°C
Device
X9448
Supply Voltage (VCC) Limits
5V 10%
Industrial
Military
-40°C
+85°C
X9448-2.7
2.7V to 5.5V
-55°C
+125°C
POTENTIOMETER CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Limits
Symbol
RTOTAL
Parameter
Min.
End to end resistance
Typ.
-20
Power rating
IW
Wiper current
RW
Wiper resistance
Vv+
Voltage on V+ Pin
-3
40
VTERM
Voltage on V- Pin
Unit
%
50
mW
+3
mA
100
VCC = 5V, Wiper Current = 3mA
VCC = 2.7-5V, Wiper Current = 3mA
250
+4.5
+5.5
V
X9440-2.7
+2.7
+5.5
X9440
-5.5
-4.5
X9440-2.7
-5.5
-2.7
V-
V+
Voltage on any VH or VL pin
Noise
-120
Resolution (4)
Test Conditions
+20
X9440
100
Vv-
Max.
V
V
dBv
1.6
25°C, each pot
Ref: 1V
%
Absolute linearity (1)
-1
+1
MI(3)
Vw(n)(actual) - Vw(n)(expected)
Relative linearity (2)
-0.2
+0.2
MI(3)
Vw(n + 1) - [Vw(n) + MI]
Temperature Coefficient of RTOTAL
300
ppm/°C
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used
as a potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(3) MI = RTOT/63 or (VH - VL)/63, single pot.
(4) Individual array resolutions.
FN8201 Rev 0.00
April 18, 2005
Page 9 of 19
X9448
COMPARATOR ELECTRICAL CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
VOS
IB
VIR
Parameter
Input offset voltage
Response time
Output current
AV
Voltage gain
TCVOS
-1
-5
Max.
Unit
1
5
mV
mV
10
Input voltage range
tR
VOR
Typ.
Input current
IO
PSRR
Min.
V-
V+/V- = 3V
V+/V- = 5V
pA
V+
V
1
mA
200
-1
Test Conditions
ns
note 1
V/mV
Power supply rejection ratio
60
Output voltage range
VSS
dB
VCC
Input offset voltage drift
V
6
µV/°C
IS
Supply current (V+ to V-)
1.2
.5
mA
mA
V+/V- = 5V
V+/V- = 3V
TON
Comparator enable time
1
µs
note 2
VOL
Output low voltage
V
IO = 1mA
VOH
Output high voltage
V
IO = 1mA
0.4
VCC - 0.8
Notes: (1) 100mV step with 100mV overdrive, ZL = 10k || 15pF, 10-90% risetime.
(2) Time from leading edge of enable bit to valid VOUT.
SYSTEM/DIGITAL D.C. OPERATING CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified.)l
Limits
Symbol
Parameter
ICC
VCC supply current (active)
ISB
Min.
Typ.
Max.
Unit
400
µA
fSCL = 400kHz, SDA = Open,
Other Inputs = VSS
Test Conditions
VCC current (standby)
1
µA
SCL = SDA = VCC, Addr. = VSS
ILI
Input leakage current
10
µA
VIN = VSS to VCC
ILO
Output leakage current
10
µA
VOUT = VSS to VCC
VIH
Input HIGH voltage
VCC x 0.7
VCC + 0.5
V
VIL
Input LOW voltage
-0.5
VCC x 0.1
V
VOL
Output LOW voltage
0.4
V
IOL = 3mA
ENDURANCE AND DATA RETENTION
Parameter
Min.
Unit
Minimum endurance
100,000
Data changes per bit per register
Data retention
100
Years
FN8201 Rev 0.00
April 18, 2005
Page 10 of 19
X9448
CAPACITANCE
Symbol
Test
Typical
Unit
Test Conditions
CI/O
Input/output capacitance (SDA)
8
pF
VI/O = 0V
CIN
Input capacitance (A0, A1, A2, A3, and SCL)
6
pF
VIN = 0V
10/10/25
pF
CL, CH, CW
Potentiometer capacitance
Power-Up Timing and Sequence
Power-up sequence(1): (1) VCC
{V+ VCC at all times}
(2) V+ and V-
Power-down sequence: no limitation
A.C. TEST CONDITIONS
EQUIVALENT A.C. LOAD CIRCUIT
Input pulse levels
VCC x 0.1 to VCC x 0.9
Input rise and fall times
10ns
Input and output timing level
VCC x 0.5
Note:
5V
2.7V
1533
(1) Applicable to recall and power consumption applications
SD Output
100pF
100pF
TIMING DIAGRAMS
START and STOP Timing
(START)
(STOP)
tR
tF
SCL
tSU:STA
tHD:STA
tSU:STO
tR
tF
SDA
Input Timing
tCYC
tHIGH
SCL
tLOW
SDA
tSU:DAT
FN8201 Rev 0.00
April 18, 2005
tHD:DAT
tBUF
Page 11 of 19
X9448
Output Timing
SCL
SDA
tDH
tAA
XDCP Timing (for All Load Instructions)
(STOP)
SCL
LSB
SDA
tWRL
VWx
XDCP Timing (for Increment/Decrement Instruction)
SCL
SDA
Wiper Register Address
Inc/Dec
Inc/Dec
tWRID
VWx
Write Protect and Device Address Pins Timing
(START)
SCL
(STOP)
...
(Any Instruction)
...
SDA
...
tSU:WPA
tHD:WPA
WP
A0, A1
A2, A3
FN8201 Rev 0.00
April 18, 2005
Page 12 of 19
X9448
AC Timing
Symbol
Parameter
Min.
Max.
Unit
400
kHz
fSCL
Clock frequency
tCYC
Clock cycle time
2500
ns
tHIGH
Clock high time
600
ns
tLOW
Clock low time
1300
ns
tSU:STA
Start setup time
600
ns
tHD:STA
Start hold time
600
ns
tSU:STO
Stop setup time
600
ns
tSU:DAT
SDA data input setup time
100
ns
tHD:DAT(4)
SDA data input hold time
0/30
ns
tR
SCL and SDA rise time
300
ns
tF
SCL and SDA fall time
300
ns
tAA
SCL low to SDA data output valid time
100
900
ns
tDH
SDA Data output hold time
50
ns
TI
Noise suppression time constant at SCL and SDA inputs
50
ns
tBUF
1300
ns
tSU:WPA
Bus free time (prior to any transmission)
WP, A0, A1, A2 and A3 setup time
0
ns
tHD:WPA
WP, A0, A1, A2 and A3 hold time
0
ns
High-Voltage Write Cycle Timing
Symbol
Parameter
Typ.
Max.
Unit
tWR
High-voltage write cycle time (store instructions)
5
10
ms
Symbol
Parameter
Min.
Max.
Unit
tWRL
Wiper response time after instruction issued (all load instructions)
10
µs
XDCP Timing
Note:
(4) VCC = 5V/2.7V
FN8201 Rev 0.00
April 18, 2005
Page 13 of 19
X9448
BASIC APPLICATIONS
Programmable Level Detector with Memory (typical bias conditions)
VREF1 (+5V)
+5V
SCL
SCL VCC
SDA
SDA
(+5V)
VH
V+
VW
–
VOUT
VOUT
+
9448
VSS
VL
VNI
V–
VT>VW, VOUT = High
VREF2 (-5V)
VT the upper limit VUL, (VOUT0 = H) • (VOUT1 = H)
VS < the lower limit VLL, (VOUT0 = L) • (VOUT1 = L)
For the window VLL VS VUL, (VOUT0 = L) • (VOUT1 = H)
FN8201 Rev 0.00
April 18, 2005
Page 14 of 19
X9448
BASIC APPLICATION (continued)
Programmable Oscillator with Memory
+5V
VH
SCL
SDA
9448
R
–
V+
VOUT
+
V–
VL VW
R2
C
R3
+5V
R1
Frequency µ R, C
Duty Cycle µ R1, R2, R3
Programmable Schmitt Trigger with Memory
VR
VH
9448
VW
R
–
V+
VOUT
+
VOUT
V–
VL
VS
VS
R1
R1 + R2
R1
V UL = --------------------- V W – ------- V OUT min
R2
R2
R2
VLL
VUL
R1 + R2
R1
V LL = --------------------- V W – ------- V OUT max
R2
R2
FN8201 Rev 0.00
April 18, 2005
Page 15 of 19
X9448
BASIC APPLICATION (continued)
Programmable Level Detector (alternate technique)
+
VS
R1 {
VOUT
–
R2 {
VOUT
+
VCC
VS
-R1
V
R2 R
+
VSS
VR
R1
V OUT = High for V S – ------- V R
R2
R1
V OUT = Low for V S – ------- V R
R2
R 1 + R 2 = R POT
Programmable Time Delay with Memory
+5V
VH
VOUT
VW
+5v
–
VOUT
+
t
VS
VW
VNI
VL
VNI
+5v
t
+5v
VOUT
VS
t
Dt
R
C
5V
t = RC ln -------------------------
5V – V
W
FN8201 Rev 0.00
April 18, 2005
Page 16 of 19
X9448
PACKAGING INFORMATION
24-Lead Plastic Small Outline Gull Wing Package Type S
0.290 (7.37) 0.393 (10.00)
0.299 (7.60) 0.420 (10.65)
Pin 1 Index
Pin 1
0.014 (0.35)
0.020 (0.50)
0.598 (15.20)
0.610 (15.49)
(4X) 7°
0.092 (2.35)
0.105 (2.65)
0.003 (0.10)
0.012 (0.30)
0.050 (1.27)
0.050" Typical
0.010 (0.25)
X 45°
0.020 (0.50)
0.050"
Typical
0° - 8°
0.009 (0.22)
0.013 (0.33)
0.420"
0.015 (0.40)
0.050 (1.27)
FOOTPRINT
0.030" Typical
24 Places
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
FN8201 Rev 0.00
April 18, 2005
Page 17 of 19
X9448
PACKAGING INFORMATION
24-Lead Plastic, TSSOP Package Type V
.026 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.303 (7.70)
.311 (7.90)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.06)
.005 (.15)
.010 (.25)
Gage Plane
0° - 8°
.020 (.50)
.030 (.75)
(4.16) (7.72)
Seating Plane
(1.78)
Detail A (20X)
(0.42)
(0.65)
.031 (.80)
.041 (1.05)
ALL MEASUREMENTS ARE TYPICAL
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
FN8201 Rev 0.00
April 18, 2005
Page 18 of 19
X9448
ORDERING INFORMATION
X9448
Device
Y
P
T
V
VCC Limits
Blank = 5V 10%
-2.7 = 2.7 to 5.5V
Temperature Range
Blank = Commercial = 0C to +70C
I = Industrial = -40C to +85C
Package
P24 = 24-Lead Plastic DIP
S24 = 24-Lead SOIC
V24 = 24-Lead TSSOP
Potentiometer Organization
Pot 0 Pot 1
W=
10k 10k
Y=
2.5k 2.5k
© Copyright Intersil Americas LLC 2005. All Rights Reserved.
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For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8201 Rev 0.00
April 18, 2005
Page 19 of 19
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