X9C104S

DATASHEET X9C102, X9C103, X9C104, X9C503 FN8222 Rev 4.00 Jan 11, 2019 Digitally Controlled Potentiometer (XDCP™) Features The X9C102, X9C103, X9C104, X9C503 are digitally controlled (XDCP) potentiometers. The device consists of a resistor array, wiper switches, a control section, and nonvolatile memory. The wiper position is controlled by a three-wire interface. • Solid-State Potentiometer • Three-Wire Serial Interface • 100 Wiper Tap Points - Wiper Position Stored in Non-volatile Memory and Recalled on Power-up The potentiometer is implemented by a resistor array composed of 99 resistive elements and a wiper switching network. Between each element and at either end are tap points accessible to the wiper terminal. The position of the wiper element is controlled by the CS, U/D, and INC inputs. The position of the wiper can be stored in non-volatile memory and then be recalled upon a subsequent power-up operation. • 99 Resistive Elements - Temperature Compensated - End-to-End Resistance, ±20% - Terminal Voltages, ±5V The device can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications ranging from control to signal processing to parameter adjustment. Pinout X9C102, X9C103, X9C104, X9C503 (8 LD SOIC, 8 LD PDIP) TOP VIEW • Low Power CMOS - VCC = 5V - Active Current, 3mA max. - Standby Current, 750µA max. • High Reliability - Endurance, 100,000 Data Changes per Bit - Register Data Retention, 100 years • X9C102 = 1k • X9C103 = 10k INC 1 8 VCC U/D 2 7 CS VH/RH 3 6 VL/RL VSS 4 5 VW/RW • X9C503 = 50k • X9C104 = 100k • Packages - 8 Ld SOIC - 8 Ld PDIP • Pb-Free Available (RoHS Compliant) Block Diagram U/D INC CS 7-BIT UP/DOWN COUNTER 99 98 VCC (SUPPLY VOLTAGE) UP/DOWN (U/D) INCREMENT (INC) DEVICE SELECT (CS) 97 7-BIT NON-VOLATILE MEMORY VH/RH CONTROL AND MEMORY RH/VH RW/VW VL/RL 96 ONE OF ONEHUNDRED DECODER TRANSFER GATES RESISTOR ARRAY 2 VSS (GROUND) GENERAL VCC GND STORE AND RECALL CONTROL CIRCUITRY 1 0 DETAILED FN8222 Rev 4.00 Jan 11, 2019 RL/VL RW/VW Page 1 of 12 X9C102, X9C103, X9C104, X9C503 Ordering Information PART NUMBER PART MARKING X9C102PZ (Notes 2, 3) X9C102P Z RTOTAL (k) TEMP RANGE (°C) 1 0 to +70 8 Ld PDIP PACKAGE (RoHS Compliant) PACKAGE DWG. # MDP0031 X9C102PIZ (Notes 2, 3) X9C102P ZI -40 to +85 8 Ld PDIP MDP0031 X9C102SZ (Notes 1, 2) X9C102S Z 0 to +70 8 Ld SOIC M8.15E X9C102SIZ (Notes 1, 2) X9C102S ZI -40 to +85 8 Ld SOIC M8.15E X9C103PZ (Notes 2, 3) X9C103P Z X9C103PIZ (Notes 2, 3) X9C103P ZI 10 0 to +70 8 Ld PDIP MDP0031 -40 to +85 8 Ld PDIP MDP0031 X9C103SZ (Notes 1, 2) X9C103S Z 0 to +70 8 Ld SOIC M8.15 X9C103SIZ (Notes 1, 2) X9C103S ZI -40 to +85 8 Ld SOIC M8.15 X9C503PZ (Notes 2, 3) X9C503P Z 0 to +70 8 Ld PDIP MDP0031 50 X9C503PIZ (Notes 2, 3) X9C503P ZI -40 to +85 8 Ld PDIP MDP0031 X9C503SZ (Notes 1, 2) X9C503S Z 0 to +70 8 Ld SOIC M8.15E X9C503SIZ (Notes 1, 2) X9C503S ZI -40 to +85 8 Ld SOIC M8.15E X9C104PIZ (Notes 2, 3) X9C104P ZI -40 to +85 8 Ld PDIP MDP0031 X9C104SZ (Notes 1, 2) X9C104S Z 0 to +70 8 Ld SOIC M8.15E X9C104SIZ (Notes 1, 2) X9C104S ZI -40 to +85 8 Ld SOIC M8.15E 100 NOTES: 1. Add “T1” suffix for tape and reel. See TB347 for details about reel specifications. 2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. Pb-free PDIPs can be used for through-hole wave solder processing only. They are not intended for use in Reflow solder processing applications. FN8222 Rev 4.00 Jan 11, 2019 Page 2 of 12 X9C102, X9C103, X9C104, X9C503 Pin Descriptions PIN NUMBER PIN NAME 1 INC INCREMENT The INC input is negative-edge triggered. Toggling INC will move the wiper and either increment or decrement the counter in the direction indicated by the logic level on the U/D input. 2 U/D UP/DOWN The U/D input controls the direction of the wiper movement and whether the counter is incremented or decremented. 3 VH/RH 4 VSS 5 VW/RW VW/RW VW/RW is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the control inputs. The wiper terminal series resistance is typically 40. 6 RL/VL RL/VL The low (VL/RL) terminals of the X9C102, X9C103, X9C104, X9C503 are equivalent to the fixed terminals of a mechanical potentiometer. The minimum voltage is -5V and the maximum is +5V. The terminology of VH/RH and VL/RL references the relative position of the terminal in relation to wiper movement direction selected by the U/D input and not the voltage potential on the terminal. 7 CS CS The device is selected when the CS input is LOW. The current counter value is stored in non-volatile memory when CS is returned HIGH while the INC input is also HIGH. After the store operation is complete the X9C102, X9C103, X9C104, X9C503 device will be placed in the low power standby mode until the device is selected once again. 8 VCC VCC FN8222 Rev 4.00 Jan 11, 2019 DESCRIPTION VH/RH The high (VH/RH) terminals of the X9C102, X9C103, X9C104, X9C503 are equivalent to the fixed terminals of a mechanical potentiometer. The minimum voltage is -5V and the maximum is +5V. The terminology of VH/RH and VL/RL references the relative position of the terminal in relation to wiper movement direction selected by the U/D input and not the voltage potential on the terminal. VSS Page 3 of 12 X9C102, X9C103, X9C104, X9C503 Absolute Maximum Ratings Thermal Information Voltage on CS, INC, U/D and VCC with Respect to VSS . -1V to +7V Voltage on VH/RH and VL/RL Referenced to VSS . . . . . . . -8V to +8V V = |VH/RH - VL/RL| X9C102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4V X9C103, X9C104, and X9C503 . . . . . . . . . . . . . . . . . . . . . . . .10V IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8.8mA Power Rating X9C102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16mW X9C103 X0C104, and X9C503 . . . . . . . . . . . . . . . . . . . . . .10mW Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TB493 *Pb-free PDIPs can be used for through-hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Recommended Operating Conditions Commercial Temperature Range. . . . . . . . . . . . . . . . . 0°C to +70°C Industrial Temperature Range . . . . . . . . . . . . . . . . . .-40°C to +85°C Supply Voltage Range (VCC) . . . . . . . . . . . . . . . . . . . . . . . 5V ±10% CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. Electrical Specifications Over recommended operating conditions unless otherwise stated. LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN TYP (Note 7) MAX UNIT POTENTIOMETER CHARACTERISTICS RTOTAL End-to-End Resistance Variation -20 +20 % VVH/RH VH Terminal Voltage -5 +5 V VVL/RL VL Terminal Voltage -5 +5 V -4.4 4.4 mA 100  IW Wiper Current RW Wiper Resistance Wiper Current = ±1mA Resistor Noise (Note 8) Ref 1kHz -120 dBV Charge Pump Noise (Note 8) @ 850kHz 20 mVRMS 1 % 40 Resolution Absolute Linearity (Note 4) VW(n)(actual) - VW(n)(EXPECTED) -1 +1 MI (Note 6) Relative Linearity (Note 5) VW(n + 1)(ACTUAL) - [VW(n) + MI] -0.2 +0.2 MI (Note 6) RTOTAL Temperature Coefficient X9C103, X9C503, X9C104 ±300 (Note 8) ppm/°C RTOTAL Temperature Coefficient X9C102 ±600 (Note 8) ppm/°C ±20 ppm/°C 10/10/25 pF Ratiometric Temperature Coefficient CH/CL/CW (Note 8) Potentiometer Capacitances See “Circuit #3 SPICE Macro Model” on page 5. DC OPERATING CHARACTERISTICS ICC VCC Active Current CS = VIL, U/D = VIL or VIH and INC = 0.4V to 2.4V at Max tCYC ISB Standby Supply Current CS = VCC - 0.3V, U/D and INC = VSS or VCC - 0.3V ILI CS, INC, U/D Input Leakage Current VIN = VSS to VCC VIH CS, INC, U/D input HIGH Voltage VIL CS, INC, U/D input LOW Voltage CIN CS, INC, U/D Input Capacitance (Note 8) FN8222 Rev 4.00 Jan 11, 2019 1 3 mA 200 750 µA ±10 µA 2 V 0.8 VCC = 5V, VIN = VSS, TA = +25°C, f = 1MHz 10 V pF Page 4 of 12 X9C102, X9C103, X9C104, X9C503 Electrical Specifications Over recommended operating conditions unless otherwise stated. (Continued) LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN TYP (Note 7) MAX UNIT AC OPERATION CHARACTERISTICS tCl CS to INC Setup 100 ns tlD INC HIGH to U/D Change 100 ns tDI U/D to INC Setup 2.9 µs tlL INC LOW Period 1 µs tlH INC HIGH Period 1 µs tlC INC Inactive to CS Inactive 1 µs tCPH CS Deselect Time (STORE) 20 ms tCPH CS Deselect Time (NO STORE) 100 ns tIW (5) INC to VW/RW Change 100 tCYC INC Cycle Time tCYC INC Input Rise and Fall Time t R , tF Power-up to Wiper Stable (Note 8) tPU µs 2 µs 500 µs 500 VCC Power-up Rate (Note 8) µs 0.2 50 V/ms NOTES: 4. Absolute linearity is utilized to determine actual wiper voltage vs expected voltage = [VW(n)(actual) - VW(n)(expected )] = ±1 MI Maximum. 5. Relative linearity is a measure of the error in step size between taps = VW(n + 1) - [VW(n) + MI] = +0.2 MI. 6. 1 MI = Minimum Increment = RTOT/99. 7. Typical values are for TA = +25°C and nominal supply voltage. 8. This parameter is not 100% tested. Test Circuit #1 Test Circuit #2 Circuit #3 SPICE Macro Model VH/RH VR/RH RTOTAL TEST POINT VS TEST POINT Vw/RW VL/RL VL/RL VW/Rw FORCE CURRENT RL CL CW 10pF 25pF CL RH 10pF RW Power-up and Down Requirements Endurance and Data Retention PARAMETER Medium Endurance Data Retention MIN 100,000 100 UNIT Data changes per bit per register years At all times, voltages on the potentiometer pins must be less than ±VCC. The recall of the wiper position from non-volatile memory is not in effect until the VCC supply reaches its final value. The VCC ramp rate specification is always in effect. AC Conditions of Test Input Pulse Levels 0V to 3V Input Rise and Fall Times 10ns Input Reference Levels 1.5V FN8222 Rev 4.00 Jan 11, 2019 Page 5 of 12 X9C102, X9C103, X9C104, X9C503 AC Timing Diagram CS tCYC tCI tIL tCPH tIC tIH 90% INC 90% 10% tID tDI tF tR U/D tIW VW MI (NOTE) NOTE: MI REFERS TO THE MINIMUM INCREMENTAL CHANGE IN THE VW OUTPUT DUE TO A CHANGE IN THE WIPER POSITION. Pin Descriptions Principles of Operation RH/VH and RL/VL There are three sections of the X9C102, X9C103, ISL9C104 and ISL9C503: the input control, counter and decode section; the non-volatile memory; and the resistor array. The input control section operates just like an up/down counter. The output of this counter is decoded to turn on a single electronic switch connecting a point on the resistor array to the wiper output. Under the proper conditions, the contents of the counter can be stored in non-volatile memory and retained for future use. The resistor array is comprised of 99 individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. The high (VH/RH) and low (V /R ) terminals of the ISLX9C102, L L X9C103, X9C104, X9C503 are equivalent to the fixed terminals of a mechanical potentiometer. The minimum voltage is -5V and the maximum is +5V. The terminology of VH/RH and V /R references the relative position of the terminal in relation L L to wiper movement direction selected by the U/D input and not the voltage potential on the terminal. RW/VW VW/RW is the wiper terminal, and is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the control inputs. The wiper terminal series resistance is typically 40. Up/Down (U/D) The U/D input controls the direction of the wiper movement and whether the counter is incremented or decremented. Increment (INC) The INC input is negative-edge triggered. Toggling INC will move the wiper and either increment or decrement the counter in the direction indicated by the logic level on the U/D input. Chip Select (CS) The device is selected when the CS input is LOW. The current counter value is stored in non-volatile memory when CS is returned HIGH while the INC input is also HIGH. After the store operation is complete the ISLX9C102, X9C103, X9C104, X9C503 device will be placed in the low power standby mode until the device is selected once again. FN8222 Rev 4.00 Jan 11, 2019 The wiper, when at either fixed terminal, acts like its mechanical equivalent and does not move beyond the last position. That is, the counter does not wrap around when clocked to either extreme. The electronic switches on the device operate in a “make-before-break” mode when the wiper changes tap positions. If the wiper is moved several positions, multiple taps are connected to the wiper for tIW (INC to VW/RW change). The RTOTAL value for the device can temporarily be reduced by a significant amount if the wiper is moved several positions. When the device is powered-down, the last wiper position stored will be maintained in the non-volatile memory. When power is restored, the contents of the memory are recalled and the wiper is reset to the value last stored. The internal charge pump allows a wide range of voltages (from -5V to 5V) applied to XDCP terminals yet given a convenience of single power supply. The typical charge pump noise of 20mV at 850kHz should be taken in consideration when designing an application circuit. Page 6 of 12 X9C102, X9C103, X9C104, X9C503 Instructions and Programming The INC, U/D and CS inputs control the movement of the wiper along the resistor array. With CS set LOW, the device is selected and enabled to respond to the U/D and INC inputs. HIGH to LOW transitions on INC will increment or decrement (depending on the state of the U/D input) a 7-bit counter. The output of this counter is decoded to select one of one-hundred wiper positions along the resistive array. The value of the counter is stored in non-volatile memory whenever CS transitions HIGH while the INC input is also HIGH. The system may select the X9Cxxx, move the wiper and deselect the device without having to store the latest wiper position in non-volatile memory. After the wiper movement is performed as previously described and once the new position is reached, the system must keep INC LOW while taking CS HIGH. The new wiper position will be maintained until changed by the system or until a power-down/up cycle recalled the previously stored data. This procedure allows the system to always power-up to a preset value stored in non-volatile memory; then during system operation, minor adjustments could be made. The adjustments might be based on user preference, i.e.: system parameter changes due to temperature drift, etc. The state of U/D may be changed while CS remains LOW. This allows the host system to enable the device and then move the wiper up and down until the proper trim is attained. Mode Selection CS INC U/D MODE L H Wiper Up L L Wiper Down X Store Wiper Position H H X X Standby Current L X No Store, Return to Standby L H Wiper Up (not recommended) L L Wiper Down (not recommended) Symbol Table WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from Low to High Will change from Low to High May change from High to Low Will change from High to Low Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance Performance Characteristics Contact the factory for more information. Applications Information Electronic digitally controlled (XCDP) potentiometers provide three powerful application advantages: 1. The variability and reliability of a solid-state potentiometer. 2. The flexibility of computer-based digital controls. 3. The retentivity of non-volatile memory used for the storage of multiple potentiometer settings or data. FN8222 Rev 4.00 Jan 11, 2019 Page 7 of 12 X9C102, X9C103, X9C104, X9C503 Basic Configurations of Electronic Potentiometers VR VR VH/RH VW/RW VL/RL I THREE TERMINAL POTENTIOMETER; VARIABLE VOLTAGE DIVIDER TWO TERMINAL VARIABLE RESISTOR; VARIABLE CURRENT Basic Circuits +V R1 +V +5V VS +V +5V VW VREF X VW/RW VOUT – VO – OP-07 + LM308A + -5V +V R2 -5V R1 VW/RW VOUT = VW/RW (a) BUFFERED REFERENCE VOLTAGE CASCADING TECHNIQUES R1 VIN VO (REG) 317 VO = (1+R2/R1)VS (b) NONINVERTING AMPLIFIER R2 VS VS LT311A 100k R1 VO + 10k 10k R1 R2 VUL = {R1/(R1 + R2)} VO(MAX) VLL = {R1/(R1 + R2)} VO(MIN) VO (REG) = 1.25V (1+R2/R1)+Iadj R2 +12V } 10k } TL072 R2 VO + – Iadj – -12V (FOR ADDITIONAL CIRCUITS SEE AN1145) VOLTAGE REGULATOR OFFSET VOLTAGE ADJUSTMENT COMPARATOR WITH HYSTERESIS Revision History Rev. Date 4.00 Jan 11, 2019 FN8222 Rev 4.00 Jan 11, 2019 Description Updated Ordering Information table to remove Obsolete and Retired parts. Added Revision History. Updated PODs for X9C102, X9C104, and X9C503 SOICs from: MDP0027 to: M8.15E and X9C103 SOIC from: MDP0027 to: M8.15, to include the Land Pattern design and convert dimensions from table to graphics. Updated Intersil disclaimer to Renesas disclaimer. Page 8 of 12 X9C102, X9C103, X9C104, X9C503 Package Outline Drawings For the most recent package outline drawing, see M8.15. M8.15 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 4, 1/12 DETAIL "A" 1.27 (0.050) 0.40 (0.016) INDEX 6.20 (0.244) 5.80 (0.228) AREA 0.50 (0.20) x 45° 0.25 (0.01) 4.00 (0.157) 3.80 (0.150) 1 2 8° 0° 3 0.25 (0.010) 0.19 (0.008) SIDE VIEW “B” TOP VIEW 2.20 (0.087) SEATING PLANE 5.00 (0.197) 4.80 (0.189) 1.75 (0.069) 1.35 (0.053) 1 8 2 7 0.60 (0.023) 1.27 (0.050) 3 6 4 5 -C- 1.27 (0.050) 0.51(0.020) 0.33(0.013) SIDE VIEW “A 0.25(0.010) 0.10(0.004) 5.20(0.205) TYPICAL RECOMMENDED LAND PATTERN NOTES: 9. Dimensioning and tolerancing per ANSI Y14.5M-1994. 10. Package length does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 11. Package width does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 12. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 13. Terminal numbers are shown for reference only. 14. The lead width as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 15. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 16. This outline conforms to JEDEC publication MS-012-AA ISSUE C. FN8222 Rev 4.00 Jan 11, 2019 Page 9 of 12 X9C102, X9C103, X9C104, X9C503 M8.15E For the most recent package outline drawing, see M8.15E. 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 0, 08/09 4 4.90 ± 0.10 A DETAIL "A" 0.22 ± 0.03 B 6.0 ± 0.20 3.90 ± 0.10 4 PIN NO.1 ID MARK 5 (0.35) x 45° 4° ± 4° 0.43 ± 0.076 1.27 0.25 M C A B SIDE VIEW “B” TOP VIEW 1.75 MAX 1.45 ± 0.1 0.25 GAUGE PLANE C SEATING PLANE 0.10 C 0.175 ± 0.075 SIDE VIEW “A 0.63 ±0.23 DETAIL "A" (1.27) (0.60) NOTES: (1.50) (5.40) 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side. 5. The pin #1 identifier may be either a mold or mark feature. 6. Reference to JEDEC MS-012. TYPICAL RECOMMENDED LAND PATTERN FN8222 Rev 4.00 Jan 11, 2019 Page 10 of 12 X9C102, X9C103, X9C104, X9C503 Plastic Dual-In-Line Packages (PDIP) For the most recent package outline drawing, see MDP0031. E D A2 SEATING PLANE L N A PIN #1 INDEX E1 c e b A1 NOTE 5 1 eA eB 2 N/2 b2 MDP0031 PLASTIC DUAL-IN-LINE PACKAGE INCHES SYMBOL PDIP8 PDIP14 PDIP16 PDIP18 PDIP20 TOLERANCE A 0.210 0.210 0.210 0.210 0.210 MAX A1 0.015 0.015 0.015 0.015 0.015 MIN A2 0.130 0.130 0.130 0.130 0.130 ±0.005 b 0.018 0.018 0.018 0.018 0.018 ±0.002 b2 0.060 0.060 0.060 0.060 0.060 +0.010/-0.015 c 0.010 0.010 0.010 0.010 0.010 +0.004/-0.002 D 0.375 0.750 0.750 0.890 1.020 ±0.010 E 0.310 0.310 0.310 0.310 0.310 +0.015/-0.010 E1 0.250 0.250 0.250 0.250 0.250 ±0.005 e 0.100 0.100 0.100 0.100 0.100 Basic eA 0.300 0.300 0.300 0.300 0.300 Basic eB 0.345 0.345 0.345 0.345 0.345 ±0.025 L 0.125 0.125 0.125 0.125 0.125 ±0.010 N 8 14 16 18 20 Reference NOTES 1 2 Rev. C 2/07 NOTES: 17. Plastic or metal protrusions of 0.010” maximum per side are not included. 18. Plastic interlead protrusions of 0.010” maximum per side are not included. 19. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane. 20. Dimension eB is measured with the lead tips unconstrained. 21. 8 and 16 lead packages have half end-leads as shown. FN8222 Rev 4.00 Jan 11, 2019 Page 11 of 12 Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation or any other use of the circuits, software, and information in the design of your product or system. Renesas Electronics disclaims any and all liability for any losses and damages incurred by you or third parties arising from the use of these circuits, software, or information. 2. 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Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products. (Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its directly or indirectly controlled subsidiaries. (Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics. (Rev.4.0-1 November 2017) http://www.renesas.com SALES OFFICES Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics Corporation TOYOSU FORESIA, 3-2-24 Toyosu, Koto-ku, Tokyo 135-0061, Japan Renesas Electronics America Inc. 1001 Murphy Ranch Road, Milpitas, CA 95035, U.S.A. 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