XP Family of Ultra-low Phase Noise
Quartz-based PLL Oscillators
XP
Datasheet
Description
Features
The XP devices are ultra-low phase noise quartz-based PLL
oscillators supporting a large range of frequencies and output
interface types. These devices are designed to operate at three
different power supplies and are available in three package sizes
with several pinout configurations, as well as three operational
temperature ranges.
▪ Output types: LVDS, LVPECL, CML
• Frequency range: 15MHz to 2100MHz
▪ Output type: HCSL
• Frequency range: 15MHz to 725MHz
▪ Supply voltage options: 1.8V, 2.5V, or 3.3V
▪ Phase jitter (12kHz to 20MHz): 120fs typical
▪ Package options:
The XP devices can be programmed to generate an output
frequency from 15MHz to 2100MHz with a resolution as low as
1Hz accuracy. The configuration capability of this family of devices
allows for fast delivery times for both sample and large production
orders.
• 7.0 × 5.0 × 1.7 mm
• 5.0 × 3.2 × 1.17 mm
• 3.2 × 2.5 × 1.07 mm
Parts are for one time programming (OTP) at the factory for a
fixed frequency application, or can be field programmable using
I2C, based on system needs (see note 1 under Pin Descriptions).
▪ Operating temperatures and frequency stability:
• -40°C to +85°C, ±25ppm
• -40°C to +105°C, ±50ppm
Pin Assignments
Figure 1. 7.0 × 5.0 mm, 5.0 × 3.2 mm, and 3.2 × 2.5 mm Packages
SDA
7
OE 1
6 VDD
NC 2
5 OUT0b
GND 3
4 OUT0
8
SCL
Table 1. Pin Descriptions
1
Pin #
Pin Name
Description
1
2
3
4
5
6
7
8
OE
NC
GND
OUT0
OUT0b
VDD
SDA 1
SCL 1
Output Enable (0 = output disabled, pulled high internally)
No connect
Connect to ground
Output
Complementary output
Supply voltage
Serial data
Serial clock
Pins 7 and 8 are no connect for non-I2C applications.
See Revision History for more details.
©2022 Renesas Electronics Corporation
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R31DS0067EU0401 February 10, 2022
XP Datasheet
Ordering Information
XP
L
7
3
5
125.000000
I
Family and ASIC
Output Type
Package
Voltage
Precision
Frequency
Temperature Range
I: Industrial range: ‐40 to +85°C, ±25ppm
K: Extended industrial range: ‐40 to +105°C, ±50ppm
1: 1.8 VDC ±5%
2: 2.5 VDC ±5%
3: 3.3 VDC ±5%
125.000000 Listed in MHz as example
3 digits before decimal and 6 digits past decimal
7: 7.0 x 5.0 mm
5: 5.0 x 3.2 mm
3.2 x 2.5 mm
3:
015.000000 to 099.999999 15MHz to 99.999999MHz
100.000000 to 999.999999 100MHz to 999.999999MHz
A00.000000 to A99.999999 1000MHz to 1099.999999MHz
B00.000000 to B99.999999 1100MHz to 1199.999999MHz
C00.000000 to C99.999999 1200MHz to 1299.999999MHz
D00.000000 to D99.999999 1300MHz to 1399.999999MHz
E00.000000 to E99.999999 1400MHz to 1499.999999MHz
F00.000000 to F99.999999 1500MHz to 1599.999999MHz
G00.000000 to G99.999999 1600MHz to 1699.999999MHz
H00.000000 to H99.999999 1700MHz to 1799.999999MHz
I00.000000 to I99.999999 1800MHz to 1899.999999MHz
J00.000000 to J99.999999 1900MHz to 1999.999999MHz
K00.000000 to K99.999999 2000MHz to 2099.999999MHz
L00.000000 2100MHz
C: CML Enable/Disable Pin 1
L: LVDS Enable/Disable Pin 1
P: LVPECL Enable/Disable Pin 1
N: HCSL Enable/Disable Pin 1
XP: 150fs jitter
5: ±50ppm (K only)
6: ±25ppm (I only)
©2022 Renesas Electronics Corporation
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R31DS0067EU0401 February 10, 2022
XP Datasheet
Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
ESD Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Mechanical Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Solder Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Termination for 3.3V LVPECL Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Termination for 2.5V LVPECL Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
LVDS Driver Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Recommended Termination for HCSL Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
CML Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Package Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Marking Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
©2022 Renesas Electronics Corporation
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R31DS0067EU0401 February 10, 2022
XP Datasheet
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the device. These ratings, which are standard values for
Renesas commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above
those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature
range. Thermal characteristics, in actual applications, should be assessed case by case to guarantee junction temperature does not
exceed 125°C.
Table 2. Absolute Maximum Ratings
Item
Rating
VDD
OE
Storage Temperature
Maximum Junction Temperature
Theta JA 1
Theta JB 1
1
JD8
75.9 °C/W
48.6 °C/W
-0.5V to +3.8V
-0.5V to +3.8V
-55°C to 125°C
125°C
89.6 °C/W
JX8
54.3 °C/W
JSW8
97.4 °C/W
66.8 °C/W
Thermal characteristics are based on simulation in standard condition.
ESD Compliance
Table 3. ESD Compliance
Human Body Model (HBM)
2000V
Mechanical Testing
Table 4. Mechanical Testing *
Parameter
Test Method
Mechanical Shock
Half-sine wave with 0.3ms 3000G. X, Y, Z each direction 1 time.
Mechanical Vibration
Frequency: 10 to 55MHz amplitude: 1.5mm.
Frequency: 55–2000Hz peak value: 20G.
Duration time: 4H for each X,Y,Z axis; total 12hours.
High Temp Operating Life (HTOL)
1000 hours at 125°C (under power).
Hermetic Seal
Gross leak (air leak test). Fine leak (Helium leak test) He-pressure: 6kgf/cm² 2 hours.
* MSL level does not apply.
Solder Reflow Profile
tP
10 seconds Max within 5°C of
260°C peak
260°C
225°C
Ramp up 3°C/s Max
50 ±10 seconds
above 225°C
reflow area
180°C
160°C
Ramp down not to
exceed 6°C/s
120 ±20 seconds in
pre-heating area
25°C
400 seconds Max from +25°C to 260°C peak
©2022 Renesas Electronics Corporation
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R31DS0067EU0401 February 10, 2022
XP Datasheet
DC Electrical Characteristics
Note for all DC Electrical Characteristics tables: A pull-up resistor from VDD to OE enables output when pin 1 is left open.
Table 5. 3.3V IDD DC Electrical Characteristics
VDD = 3.3V ±5%, TA = -40°C to +85°C, -40°C to +105°C, typical at 156.25MHz.
Symbol
Parameter
Output Type
Minimum
Typical
Maximum
15MHz to 400MHz.
—
59
67
400MHz to 2.1GHz.
—
—
85
15MHz to 212.5MHz.
—
84
94
212MHz to 400MHz.
—
—
110
400MHz to 2.1GHz.
—
—
110
HCSL
15MHz to 725MHz.
—
74
83
CML
15MHz to 2.1GHz.
—
45
61
Minimum
Typical
Maximum
15MHz to 400MHz.
—
59
66
400MHz to 2.1GHz.
—
—
85
15MHz to 156.25MHz.
—
84
94
156.25MHz to 400MHz.
—
—
110
400MHz to 2.1GHz.
—
—
110
15MHz to 400MHz.
—
—
95
400MHz to 725MHz.
—
74
82
15MHz to 2.1GHz.
—
54
61
Minimum
Typical
Maximum
15MHz to 400MHz.
—
59
66
400MHz to 2.1GHz.
—
—
85
15MHz to 250MHz.
—
84
93
250MHz to 2.1GHz.
—
—
110
15MHz to 400MHz.
—
—
95
400MHz to 725MHz.
—
74
81
15MHz to 2.1GHz.
—
54
61
LVDS
IDD
Current Consumption
LVPECL
Conditions
Units
mA
Table 6. 2.5V IDD DC Electrical Characteristics
VDD = 2.5V ±5%, TA = -40°C to +85°C, -40°C to +105°C, typical at 156.25MHz.
Symbol
Parameter
Output Type
LVDS
IDD
Current Consumption
LVPECL
HCSL
CML
Conditions
Units
mA
Table 7. 1.8V IDD DC Electrical Characteristics
VDD = 1.8V ±5%, TA = -40°C to +85°C, -40°C to +105°C, typical at 156.25MHz.
Symbol
Parameter
Output Type
LVDS
IDD
Current Consumption
LVPECL
HCSL
CML
©2022 Renesas Electronics Corporation
Conditions
5
Units
mA
R31DS0067EU0401 February 10, 2022
XP Datasheet
Table 8. LVCMOS DC Electrical Characteristics
VDD = 3.3V, 2.5V, 1.8V ±5%, TA = -40°C to +85°C, -40°C to +105°C, typical at 156.25MHz.
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Units
VIH
Input High Voltage (OE pin only)
VDD = 3.3V, 2.5V, 1.8V ±5%
0.7 × VDD
—
VDD + 0.3
V
VIL
Input Low Voltage (OE pin only)
VDD = 3.3V, 2.5V, 1.8V ±5%
GND - 0.3
—
0.3 × VDD
V
Table 9. LVDS DC Electrical Characteristics
VDD = 3.3V, 2.5V, 1.8V ±5%, TA = -40°C to +85°C, -40°C to +105°C, typical at 156.25MHz.
Symbol
VOD
VOS
Parameter
Differential Output Voltage
Output Offset Voltage
Conditions
Minimum
Typical
Maximum
VDD = 3.3V, 2.5V, 1.8V ±5%
0.30
0.44
0.60
VDD = 3.3V ±5%
1.11
1.26
1.41
VDD = 2.5V ±5%
1.08
1.25
1.41
VDD = 1.8V ±5%
0.75
0.88
1.01
Units
V
Table 10. LVPECL DC Electrical Characteristics
VDD = 3.3V, 2.5V, 1.8V ±5%, TA = -40°C to +85°C, -40°C to +105°C, typical at 156.25MHz.
Symbol
VOH
VOL
Parameter
Output High Voltage
Output Low Voltage
Conditions
Minimum
Typical
Maximum
VDD = 3.3V ±5%.
2.28
2.49
2.72
VDD = 2.5V ±5%.
1.52
1.69
1.87
VDD = 1.8V ±5%.
0.83
0.96
1.11
VDD = 3.3V ±5%.
1.68
1.84
2.01
VDD = 2.5V ±5%.
0.92
1.04
1.17
VDD = 1.8V ±5%.
0.19
0.30
0.42
Units
V
Table 11. HCSL DC Electrical Characteristics
VDD = 3.3V, 2.5V, 1.8V ±5%, TA = -40°C to +85°C, -40°C to +105°C, typical at 156.25MHz.
Symbol
VOH
VOL
Parameter
Output High Voltage
Output Low Voltage
©2022 Renesas Electronics Corporation
Conditions
Minimum
Typical
Maximum
VDD = 3.3V ±5%.
0.78
0.92
1.07
VDD = 2.5V ±5%.
0.74
0.88
1.03
VDD = 1.8V ±5%.
0.67
0.81
0.95
—
-0.06
0.07
0.20
6
Units
V
R31DS0067EU0401 February 10, 2022
XP Datasheet
Table 12. CML DC Electrical Characteristics
VDD = 3.3V, 2.5V, 1.8V ±5%, TA = -40°C to +85°C, -40°C to +105°C, typical at 156.25MHz.
Symbol
VOH
VOL
Parameter
Conditions
Minimum
Typical
Maximum
VDD = 3.3V ±5%.
3.09
3.26
3.43
VDD = 2.5V ±5%.
2.33
2.46
2.59
VDD = 1.8V ±5%.
1.66
1.76
1.85
VDD = 3.3V ±5%.
2.70
2.85
3.00
VDD = 2.5V ±5%.
1.95
2.06
2.17
VDD = 1.8V ±5%.
1.30
1.37
1.45
Minimum
Typical
Maximum
-5
0.81
5
-5
1.36
5
SDATA
-5
1.44
5
OE
-20
-17.44
-14
-37
-33.49
-30
-20
-17.02
-14
Output High Voltage
Output Low Voltage
Units
V
V
Table 13. DC Electrical Characteristics – Leakage Current
VDD = 3.3V, 2.5V, 1.8V ±5%, TA = -40°C to +85°C, -40°C to +105°C, typical at 156.25MHz.
Symbol
Parameter
Input
Conditions
OE
IIH
IIL
Input Leakage High
Input Leakage Low
SCLK
SCLK
VDD = 3.3V ±5%.
VDD = 3.3V ±5%.
SDATA
©2022 Renesas Electronics Corporation
7
Units
µA
µA
R31DS0067EU0401 February 10, 2022
XP Datasheet
AC Electrical Characteristics
Notes for all AC Electrical Characteristics tables:
1. A pull-up resistor from VDD to OE enables output when pin 1 is left open.
2. Installation should include a 0.01μF bypass capacitor placed between VDD and GND to minimize power supply line noise.
Table 14. 3.3V AC Electrical Characteristics
VDD = 3.3V ±5%, TA = -40°C to +85°C, -40°C to +105°C.
Symbol
F
Parameter
Minimum
Typical
Maximum
LVDS, LVPECL, CML.
15
—
2100
HCSL.
15
—
725
Temperature = -40°C to +85°C.
—
—
±25
ppm
Temperature = -40°C to +105°C.
—
—
±50
ppm
Frequency Tolerance (25°C)
Temperature = 25°C.
-15
±10
-15
ppm
Aging (1st year)
TA = 25°C.
—
—
±3
ppm
Aging (10 years)
TA = 25°C.
—
—
±10
ppm
Output Frequency Range
Frequency Stability
Output Load
TST
tR
tF
Start-up Time
Output Rise Time
Output Fall Time
Test Condition
LVDS.
Differential.
—
100
—
LVPECL.
VDD - 2.0V.
—
50
—
HCSL.
To GND.
—
50
—
Output valid time after VDD meets minimum
specified level.
—
5
—
LVDS.
—
299
400
—
287
400
—
306
400
CML
—
301
400
LVDS.
—
279
400
—
274
400
—
284
400
—
279
400
LVPECL.
20% – 80%,
156.25MHz
HCSL.
LVPECL.
80% – 20%,
156.25MHz
HCSL.
CML
ODC
TOE
Output Clock Duty Cycle
Output Enable/Disable Time
©2022 Renesas Electronics Corporation
LVDS.
156.25MHz
48
—
52
LVPECL.
156.25MHz
48
—
52
HCSL.
156.25MHz
48
—
52
CML
156.25MHz
48
—
52
—
1
—
—
—
8
Units
MHz
Ω
ms
ps
ps
%
ms
R31DS0067EU0401 February 10, 2022
XP Datasheet
Table 15. 2.5V AC Electrical Characteristics
VDD = 2.5V ±5%, TA = -40°C to +85°C, -40°C to +105°C.
Symbol
F
Parameter
Minimum
Typical
Maximum
LVDS, LVPECL, CML.
15
—
2100
HCSL.
15
—
725
Temperature = -40°C to +85°C.
—
—
±25
ppm
Temperature = -40°C to +105°C.
—
—
±50
ppm
Frequency Tolerance (25°C)
Temperature = 25°C.
-15
±10
+15
ppm
Aging (1st year)
TA = 25°C.
—
—
±3
Aging (10 years)
TA = 25°C.
—
—
±10
Output Frequency Range
Frequency Stability
Output Load
TST
tR
tF
Start-up Time
Output Rise Time
Output Fall Time
Test Condition
LVDS.
Differential.
—
100
—
LVPECL.
VDD - 2.0V.
—
50
—
HCSL.
To GND.
—
50
—
Output valid time after VDD meets minimum
specified level.
—
5
—
LVDS.
—
303
400
—
292
400
—
310
400
CML
—
304
400
LVDS.
—
282
400
—
278
400
—
288
400
—
281
400
LVPECL.
20% – 80%,
156.25MHz
HCSL.
LVPECL.
80% – 20%,
156.25MHz
HCSL.
CML
ODC
TOE
Output Clock Duty Cycle
Output Enable/Disable Time
©2022 Renesas Electronics Corporation
LVDS.
156.25MHz
48
—
52
LVPECL.
156.25MHz
48
—
52
HCSL.
156.25MHz
48
—
52
CML
156.25MHz
48
—
52
—
1
—
—
—
9
Units
MHz
Ω
ms
ps
ps
%
ms
R31DS0067EU0401 February 10, 2022
XP Datasheet
Table 16. 1.8V AC Electrical Characteristics
VDD = 1.8V ±5%, TA = -40°C to +85°C, -40°C to +105°C.
Symbol
F
Parameter
Minimum
Typical
Maximum
LVDS, LVPECL, CML.
15
—
2100
HCSL.
15
—
725
Temperature = -40°C to +85°C.
—
—
±25
ppm
Temperature = -40°C to +105°C.
—
—
±50
ppm
Frequency Tolerance (25°C)
Temperature = 25°C.
-15
±10
+15
ppm
Aging (1st year)
TA = 25°C.
—
—
±3
Aging (10 years)
TA = 25°C.
—
—
±10
Output Frequency Range
Frequency Stability
Output Load
TST
tR
tF
Start-up Time
Output Rise Time
Output Fall Time
Test Condition
LVDS.
Differential.
—
100
—
LVPECL, HCSL.
To GND.
—
50
—
Output valid time after VDD meets minimum
specified level.
—
5
—
LVDS.
—
311
450
—
312
450
—
316
450
CML
—
313
450
LVDS.
—
290
450
—
297
450
—
294
450
—
289
450
LVPECL.
20% – 80%,
156.25MHz
HCSL.
LVPECL.
80% – 20%,
156.25MHz
HCSL.
CML
ODC
TOE
Output Clock Duty Cycle
LVDS.
156.25MHz
48
—
52
LVPECL.
156.25MHz
48
—
52
HCSL.
156.25MHz
48
—
52
CML
156.25MHz
48
—
52
—
1
—
Output Enable/Disable Time
—
—
Units
MHz
Ω
ms
ps
ps
%
ms
Table 17. Phase Jitter Characteristics
VDD = 3.3V, 2.5V, 1.8V ±5%, TA = -40°C to +85°C, -40°C to +105°C.
Symbol
fJITTER
Parameter
Phase Jitter (12kHz – 20MHz)
©2022 Renesas Electronics Corporation
Conditions
Minimum
Typical
Maximum
Units
250.00MHz
—
115
—
fsec
312.50MHz
—
125
—
fsec
625.00MHz
—
123
—
fsec
644.53MHz
—
120
—
fsec
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Output Waveforms
Figure 2. LVDS Output Waveforms
Output Levels /Rise Time/Fall Time Measurements
TF
TR
OUT0b
VOS
20% to 80%
VOD
OUT0
Oscillator Symmetry
VOH
OUT0b
VOL
OUT0
½ Period
Period
Figure 3. LVPECL Output Waveforms
Rise Time/Fall Time Measurements
TF
TR
VOH
OUT0b
20% to 80%
OUT0
VOL
Oscillator Symmetry
VOH
OUT0b
OUT0
VOL
½ Period
Period
©2022 Renesas Electronics Corporation
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XP Datasheet
Figure 4. HCSL Output Waveforms
Rise Time/Fall Time Measurements
TF
TR
VOH
OUT0b
20% to 80%
OUT0
VOL
Oscillator Symmetry
VOH
OUT0b
OUT0
VOL
½ Period
Period
Figure 5. CML Output Waveforms
Rise Time/Fall Time Measurements
TF
TR
VOH
OUT0b
20% to 80%
OUT0
VOL
Oscillator Symmetry
VOH
OUT0b
OUT0
VOL
½ Period
Period
©2022 Renesas Electronics Corporation
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XP Datasheet
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential output is a low impedance follower output that generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω
transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion.
Figure 6 and Figure 7 show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and
it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component
process variations.
Figure 6. 3.3V LVPECL Output Termination
Figure 7. 3.3V LVPECL Output Termination
©2022 Renesas Electronics Corporation
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XP Datasheet
Termination for 2.5V LVPECL Outputs
Figure 8 and Figure 9 show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to
VCCO – 2V. For VCCO = 2.5V, the VCCO – 2V is very close to ground level. The R3 in Figure 9 can be eliminated and the termination is
shown in Figure 10.
Figure 8. 2.5V LVPECL Driver Termination Example
Figure 9. 2.5V LVPECL Driver Termination Example
Figure 10. 2.5V LVPECL Driver Termination Example
©2022 Renesas Electronics Corporation
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XP Datasheet
LVDS Driver Termination
For a general LVDS interface, the recommended value for the termination impedance (ZT) is between 90Ω and 132Ω. The actual value
should be selected to match the differential impedance (Z0) of your transmission line. A typical point-to-point LVDS design uses a 100Ω
parallel resistor at the receiver and a 100Ω differential transmission-line environment. In order to avoid any transmission-line reflection
issues, the components should be surface mounted and must be placed as close to the receiver as possible. Renesas offers a full line of
LVDS compliant devices with two types of output structures: current source and voltage source.
The standard termination schematic as shown in Figure 11 can be used with either type of output structure. Figure 12, which can also be
used with both output types, is an optional termination with center tap capacitance to help filter common mode noise. The capacitor value
should be approximately 50pF. If using a non-standard termination, it is recommended to contact Renesas and confirm if the output
structure is current source or voltage source type. In addition, since these outputs are LVDS compatible, the input receiver’s amplitude
and common-mode input range should be verified for compatibility with the output.
Figure 11. Standard LVDS Termination
Figure 12. Optional LVDS Termination
©2022 Renesas Electronics Corporation
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XP Datasheet
Recommended Termination for HCSL Outputs
Figure 13 is the recommended source termination for applications where the driver and receiver will be on a separate PCBs. This
termination is the standard for PCI Express™ and HCSL output types. All traces should be 50Ω impedance single-ended or 100Ω
differential. Figure 14 is the recommended termination for applications where a point-to-point connection can be used. A point-to-point
connection contains both the driver and the receiver on the same PCB. With a matched termination at the receiver, transmission-line
reflections will be minimized. In addition, a series resistor (Rs) at the driver offers flexibility and can help dampen unwanted reflections.
The optional resistor can range from 0Ω to 33Ω. All traces should be 50Ω impedance single-ended or 100Ω differential.
Figure 13. Recommended Source Termination (where the driver and receiver will be on separate PCBs)
0.5" Max
Rs
22 to 33 +/-5%
0-0.2"
1-14"
0.5 - 3.5"
L1
L2
L4
L5
L1
L2
L4
L5
PCI Expres s
PCI Expres s
Connector
Driver
0-0.2"
L3
L3
PCI Expres s
Add-in Card
49.9 +/- 5%
Rt
Figure 14. Recommended Termination (where a point-to-point connection can be used)
Rs
0.5" Max
0 to 33
L1
0 to 33
L1
0-18"
0-0.2"
L2
L3
L2
L3
PCI Expres s
Rt
Driver
49.9 +/- 5%
CML Termination
Figure 15 shows an example of the termination for a CML driver. In this example, the transmission line characteristic impedance is 50Ω.
The R1 and R2 50Ω matched load terminations are pulled up to VDDO. The matched loads are located close to the receiver.
Figure 15. CML Termination Example
VDDO
VDDO
R1
50
R2
50
Zo = 50
Zo = 50
CML Driv er
©2022 Renesas Electronics Corporation
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XP Datasheet
Package Outline Drawings
The package outline drawings are located at the end of this document and are accessible from the Renesas website. The package
information is the most current data available and is subject to change without revision of this document.
7.0 × 5.0 mm, 8-CLCC (JD8D1) package
5.0 × 3.2 mm, CLCC-8 (JX8D1) package
3.2 × 2.5 mm, 8-COL (JSW8D1) package
Marking Diagrams
Figure 16. Marking Configuration for the 7.0 × 5.0 mm and 5.0 × 3.2 mm Packages
XPxxxx
ABC-YW
$PF**
▪ Line 1 denotes the truncated part number (e.g., “xxxx” is L726, P516).
▪ Line 2 indicates the following:
• “ABC” denotes the truncated first three digits of the frequency code (e.g., 156).
• “-YW” denotes the last digit of the year and week when the part was assembled.
▪ Line 3 indicates the following:
• “$” denotes the mark location.
• “PF” is where “P” denotes the package coding number and “F” denotes the frequency coding number.
• “**” denotes the sequential lot number.
Figure 17. Marking Configuration for the 3.2 × 2.5 mm Package
▪ Line 1 indicates the following:
ABC-YW
$PF**
• “ABC” denotes the truncated first three digits of the frequency code (e.g., 156).
• “-YW” denotes the last digit of the year and week when the part was assembled.
▪ Line 2 indicates the following:
• “$” denotes the mark location.
• “PF” is where “P” denotes the package coding number and “F” denotes the frequency coding number.
• “**” denotes the sequential lot number.
©2022 Renesas Electronics Corporation
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Revision History
Revision Date
Description of Change
February 10, 2022
Updated Output Clock Duty Cycle minimum and maximum specifications for LVDS, LVPECL, HCSL, and CML
in Table 14, Table 15, and Table 16.
July 13, 2021
▪ Updated Ordering Information “Precision” option.
▪ Updated Package Outline Drawings section.
September 21, 2020
Updated ordering code to have I2C (was precision field, which is redundant with temperature field).
July 22, 2019
Updated LVDS Differential Output Voltage minimum from 0.28 to 0.30V.
May 22, 2019
Changed 3.3V, 2.5V, and 1.8V LVPECL current consumption conditions value from 670MHz to 2.1GHz.
April 1, 2019
Initial release.
©2022 Renesas Electronics Corporation
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R31DS0067EU0401 February 10, 2022
8-CLCC, Package Outline Drawing
7.0 x 5.0 x 1.7 mm Body, 2.54mm Pitch
JD8D1, PSC-4733-01, Rev 01, Page 1
6
5
4
1
2
3
1
2
3
6
5
4
© Integrated Device Technology, Inc.
8-CLCC, Package Outline Drawing
7.0 x 5.0 x 1.7 mm Body, 2.54mm Pitch
JD8D1, PSC-4733-01, Rev 01, Page 2
Package Revision History
Date Created
© Integrated Device Technology, Inc.
Description
Rev No.
March 6, 2019 Rev 01
Update Drawing and Dimensions
Aug. 9, 2018
Initial Release
Rev 00
CLCC-8, Package Outline Drawing
5.0 x 3.2 x 1.17 mm Body 1.27mm Pitch
JX8D1, PSC-4754-01, Rev 01, Page 1
© Integrated Device Technology, Inc.
CLCC-8, Package Outline Drawing
5.0 x 3.2 x 1.17 mm Body 1.27mm Pitch
JX8D1, PSC-4754-01, Rev 01, Page 2
Package Revision History
© Integrated Device Technology, Inc.
Description
Date Created
Rev No.
March 6, 2019
Rev 01
Update Drawing and Dimensions
July 13, 2018
Rev 00
Initial Release
8-COL, Package Outline Drawing
3.2 x 2.5 x 1.07 mm Body,
JSW8D1, PSC-4775-01, Rev 01, Page 1
5
5
© Integrated Device Technology, Inc.
8-COL, Package Outline Drawing
3.2 x 2.5 x 1.07 mm Body,
JSW8D1, PSC-4775-01, Rev 01, Page 2
Package Revision History
© Integrated Device Technology, Inc.
Description
Date Created
Rev No.
April 10, 2019
Rev 01. Update Drawing, Thickness and Tolerance
Aug. 8, 2018
Rev 00
Initial Release
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