NOT RECOMMENDED FOR NEW DESIGNS
RECOMMENDED REPLACEMENT PART ZL8101
ZL2004
Adaptive Digital DC-DC Controller with Current Sharing
Description
Features
The ZL2004 is a digital DC-DC controller designed to
work with the ZL1505 MOSFET driver IC. Current
sharing allows multiple devices to be connected in
parallel to source loads with very high current
demands.
Adaptive
performance
optimization
algorithms improve power conversion efficiency across
the entire load range. Zilker Labs Digital-DC™
technology enables a blend of power conversion
performance and power management features.
Power Conversion
The ZL2004 is designed to be a flexible building block
for DC power and can be easily adapted to designs
ranging from a single-phase power supply operating
from a 4.5 V input to a multi-phase supply operating
from a 12V input. The ZL2004 eliminates the need for
complicated power supply managers as well as
numerous external discrete components.
SS
V (0,1)
VMON
MGN
SYNC
DDC
SCL
SDA
SALRT
FN6846
Rev. 3.00
February 15, 2011
Efficient synchronous buck controller
Adaptive performance optimization algorithms
4.5 V to 14 V input range
0.54 V to 4 V output range (with margin)
± 1% VOUT set-point accuracy
Fast load transient response
Current sharing and phase interleaving
Digitally adjustable current sense range
Snapshot™ parameter capture
RoHS compliant (5 x 5 mm) QFN package
Power Management
All operating features can be configured by simple pinstrap/resistor selection or through the SMBus™ serial
interface. The ZL2004 uses the PMBus™ protocol for
communication with a host controller and the DigitalDC bus for communication between other Zilker Labs
devices.
EN PG
DATASHEET
Digital soft start/stop
Precision delay and ramp-up
Power good/enable
Voltage tracking, sequencing and margining
Voltage/current/temperature monitoring
SMBus communication (PMBus compliant)
Output voltage and current protection
Internal non-volatile memory (NVM)
Applications
FC
ILIM CFG
Servers / storage equipment
Telecom / datacom equipment
Power supplies (memory, DSP, ASIC, FPGA)
V25 VR VDD
LDO
POWER
MANAGEMENT
LEVEL
SHIFTER
NONVOLATILE
MEMORY
PWM
CONTROLLER
I2 C
MONITOR
ADC
SA (0,1)
VTRK
VSEN+/XTEMP
CURRENT
SENSE
PWMH
PWML
ISENA
ISENB
TEMP
SENSOR
SGND DGND
Figure 1. Block Diagram
FN6846 Rev. 3.00
February 15, 2011
Page 1 of 42
ZL2004
Table of Contents
1. Electrical Characteristics................................................................................................................................................................. 3
2. Pin Descriptions .............................................................................................................................................................................. 6
3. Typical Application Circuit............................................................................................................................................................. 8
4. ZL2004 Overview ........................................................................................................................................................................... 9
4.1 Digital-DC Architecture......................................................................................................................................................... 9
4.2 Power Conversion Overview ............................................................................................................................................... 10
4.3 Power Management Overview ............................................................................................................................................. 11
4.4 Multi-mode Pins .................................................................................................................................................................. 11
5. Power Conversion Functional Description.................................................................................................................................... 12
5.1 Internal Bias Regulators and Input Supply Connections...................................................................................................... 12
5.2 Output Voltage Selection ..................................................................................................................................................... 12
5.3 Start-up Procedure ............................................................................................................................................................... 15
5.4 Soft Start Delay and Ramp Times ........................................................................................................................................ 15
5.5 Power Good ......................................................................................................................................................................... 16
5.6 Switching Frequency and PLL ............................................................................................................................................. 17
5.7 Power Train Component Selection ...................................................................................................................................... 18
5.8 Current Limit Threshold Selection....................................................................................................................................... 22
5.9 Loop Compensation ............................................................................................................................................................. 25
5.10 Adaptive Loop Compensation ........................................................................................................................................... 25
5.11 Non-linear Response (NLR) Settings................................................................................................................................. 26
5.12 Efficiency Optimized Driver Dead-time Control ............................................................................................................... 26
5.13 Adaptive Diode Emulation................................................................................................................................................. 27
5.14 Adaptive Frequency Control .............................................................................................................................................. 27
6. Power Management Functional Description ................................................................................................................................. 28
6.1 Input Undervoltage Lockout ................................................................................................................................................ 28
6.2 Output Overvoltage Protection ............................................................................................................................................ 28
6.3 Output Pre-Bias Protection .................................................................................................................................................. 28
6.4 Output Overcurrent Protection ............................................................................................................................................. 29
6.5 Thermal Overload Protection ............................................................................................................................................... 30
6.6 Voltage Tracking ................................................................................................................................................................. 30
6.7 Voltage Margining ............................................................................................................................................................... 31
6.8 External Voltage Monitoring ............................................................................................................................................... 31
6.9 I2C/SMBus Communications ............................................................................................................................................... 32
6.10 I2C/SMBus Device Address Selection ............................................................................................................................... 32
6.11 Digital-DC Bus .................................................................................................................................................................. 33
6.12 Phase Spreading ................................................................................................................................................................. 33
6.13 Output Sequencing ............................................................................................................................................................. 34
6.14 Fault Spreading .................................................................................................................................................................. 35
6.15 Active Current Sharing ...................................................................................................................................................... 35
6.16 Phase Adding/Dropping ..................................................................................................................................................... 36
6.17 Monitoring via I2C/SMBus ................................................................................................................................................ 36
6.18 Temperature Monitoring Using the XTEMP Pin ............................................................................................................... 37
6.19 Snapshot™ Parameter Capture .......................................................................................................................................... 37
6.20 Non-Volatile Memory and Device Security Features ........................................................................................................ 38
7. Package Dimensions ..................................................................................................................................................................... 39
8. Ordering Information .................................................................................................................................................................... 40
9. Related Tools and Documentation ................................................................................................................................................ 40
10. Revision History ......................................................................................................................................................................... 41
FN6846 Rev. 3.00
February 15, 2011
Page 2 of 42
ZL2004
1. Electrical Characteristics
Table 1. Absolute Maximum Ratings
Operating beyond these limits may cause permanent damage to the device. Functional operation beyond the
Recommended Operating Conditions is not implied. Voltage measured with respect to SGND.
Parameter
Pin(s)
Value
DC supply voltage
VDD
-0.3 to 17
V
Logic I/O voltage
CFG, DDC, EN, FC, ILIM, MGN, PG,
SA(0,1), SALRT, SCL, SDA, SS,
SYNC, VMON, V(0,1)
-0.3 to 6.5
V
VSEN+, VSEN-, VTRK, XTEMP
-0.3 to 6.5
V
ISENA, ISENB
VR
V25
-1.5 to 6.5
-0.3 to 6.5
-0.3 to 3
V
V
V
DGND, SGND
-0.3 to +0.3
V
–
–
-55 to 150
-55 to 150
o
All
300
o
Analog input voltages
MOSFET drive reference
Logic reference
Ground voltage differential
(VDGND-VSGND)
Junction temperature
Storage temperature range
Lead temperature
(soldering, 10 s)
Table 2. Recommended Operating Conditions and Thermal Information
Symbol
Parameter
Input Supply Voltage Range
VDD
Output Voltage Range (Inductor sensing)1
Operating Junction Temperature Range
Junction to Ambient Thermal Impedance
Junction to Case Thermal Impedance3
2
Min
4.5
Unit
Typ
–
o
C
C
C
Max
14
Unit
V
4.0
V
VOUT
0.54
TJ
-40
–
125
°C
ΘJA
–
35
–
°C/W
ΘJC
–
5
–
°C/W
Notes:
1. Includes margin limits.
2. ΘJA is measured in free air with the device mounted on a multi-layer FR4 test board and the exposed metal pad soldered to a low impedance
ground plane using multiple vias.
3. For ΘJC, the “case” temperature is measured at the center of the exposed metal pad.
FN6846 Rev. 3.00
February 15, 2011
Page 3 of 42
ZL2004
Table 3. Electrical Specifications
VDD = 12 V, TA = -40C to 85C unless otherwise noted. Typical values are at TA = 25C. Boldface limits apply over
the operating temperature range, -40°C to +85°C.
Parameter
Input and Supply Characteristics
IDD supply current at fSW = 200 kHz
IDD supply current at fSW = 1.4 MHz
IDDS shutdown current
VR reference output voltage
V25 reference output voltage
Output Characteristics
Output voltage adjustment range1
Output voltage set-point resolution
Output voltage accuracy 3
VSEN input bias current
Current sense differential input
voltage (VOUT referenced)
Current sense input bias current
(VOUT referenced, VOUT 6 V, IVR < 50 mA
VR > 3 V, IV25 < 50 mA
–
4.5
2.25
6.5
5.2
2.5
8
5.7
2.75
mA
V
V
VIN > VOUT
Set using resistors
Set using I2C/SMBus
Includes line, load, temp
VSEN = 4 V
0.6
–
–
-1
–
–
10
±0.025
–
80
3.6
–
–
1
150
V
mV
% FS2
%
µA
VISENA - VISENB
- 50
–
50
mV
ISENA
ISENB
Set using SS pin or resistor
Set using I2C/SMBus
-1
- 100
2
0.002
–
–
–
2
0
–
–
–
–
–
±0.25
-0.25/+4
-0.25/+4
–
–
100
1
100
20
500
–
–
–
20
200
–
µA
µA
ms
s
ms
ms
ms
ms
ms
µs
- 10
-1
–
–
2.0
–
2.25
–
–
–
1.4
–
–
–
10
1
0.8
–
–
0.4
–
µA
mA
V
V
V
V
V
Turn-on delay (precise mode) 4,5
Turn-on delay (normal mode) 6
Turn-off delay 6
Set using SS pin or resistor
Set using I2C
EN,PG,SCL,SDA,SALRT pins
Multi-mode logic pins
IOL ≤ 4 mA
IOH ≥ -2 mA
1. Set point adjustment range does not include margin limits.
2. Percentage of Full Scale (FS) with temperature compensation applied.
3. VOUT set-point measured at the termination of the VSEN+ and VSEN- sense points.
4. The device requires approximately 2 ms following an enable signal and prior to ramping its output. The delay accuracy will vary by
±0.25 ms around the 2 ms minimum delay value.
5. Precise ramp timing mode is only valid when using EN pin to enable the device rather than PMBus enable.
6. The devices may require up to a 4 ms delay following an assertion of the enable signal (normal mode) or following the de-assertion
of the enable signal.
FN6846 Rev. 3.00
February 15, 2011
Page 4 of 42
ZL2004
Table 3. Electrical Characteristics (continued)
VDD = 12 V, TA = -40C to 85C unless otherwise noted. Typical values are at TA = 25C.
Parameter
Oscillator and Switching Characteristics
Switching frequency range
Switching frequency set-point accuracy
Maximum PWM duty cycle
Minimum SYNC pulse width
Input clock frequency drift tolerance
Tracking
VTRK input bias current
VTRK tracking ramp accuracy
VTRK regulation accuracy
Fault Protection Characteristics
UVLO threshold range
UVLO set-point accuracy
UVLO hysteresis
UVLO delay
Power good VOUT low threshold
Power good VOUT high threshold
Power good VOUT hysteresis
Power good delay
VSEN undervoltage threshold
VSEN overvoltage threshold
Conditions
Min 10
Typ
Max 10
Unit
Factory default
External clock source
200
-5
95
150
- 13
–
–
–
–
–
1400
5
–
–
13
kHz
%
%
ns
%
VTRK = 4.0 V
100% Tracking, VOUT - VTRK
100% Tracking, VOUT - VTRK
–
- 100
-1
110
–
–
200
+ 100
1
µA
mV
%
Configurable via I2C/SMBus
2.85
- 150
–
0
–
–
–
–
2
0
–
0
–
0
–
–
5
–
–
3
–
–
90
115
5
–
–
85
–
115
–
5
16
–
16
150
–
100
2.5
–
–
–
20
500
–
110
–
115
–
–
60
V
mV
%
%
µs
% VOUT
% VOUT
%
ms
s
% VOUT
% VOUT
% VOUT
% VOUT
% VOUT
µs
µs
–
±10
–
% FS8
–
1
5
–
4400
–
32
tSW 9
tSW 9
ppm /
°C
°C
°C
°C
Factory default
Configurable via I2C/SMBus
Factory default
Factory default
Factory default
Using pin-strap or resistor 7
Configurable via I2C/SMBus
Factory default
Configurable via I2C/SMBus
Factory default
Configurable via I2C/SMBus
VSEN undervoltage hysteresis
VSEN undervoltage/ overvoltage fault
response time
Factory default
Configurable via I2C/SMBus
Current limit set-point accuracy
(VOUT referenced)
Current limit protection delay
Temperature compensation of
current limit protection threshold
Thermal protection threshold (junction
temperature)
Thermal protection hysteresis
Notes:
Factory default
Configurable via I2C/SMBus
Factory default
Configurable via I2C/SMBus
Factory default
Configurable via I2C/SMBus
100
–
- 40
–
125
–
15
12700
–
125
–
7. Factory default Power Good delay is set to the same value as the soft start ramp time.
8. Percentage of Full Scale (FS) with temperature compensation applied.
9. tSW = 1/fSW, where fSW is the switching frequency.
10. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
FN6846 Rev. 3.00
February 15, 2011
Page 5 of 42
25
26
28
27
29
30
1
24
2
23
32-Pin QFN
5 x 5 mm
3
4
22
21
5
20
Exposed Paddle
6
19
Connect to SGND
7
18
8
15
16
14
VDD
VR
PWMH
SGND
PWML
ISENA
ISENB
NC
VTRK
VSEN+
VSEN-
13
12
11
9
FC
10
17
V0
V1
VMON
NC
DGND
SYNC
SA0
SA1
ILIM
SCL
SDA
SALRT
31
32
PG
SS
EN
CFG
MGN
DDC
XTEMP
V25
ZL2004
2. Pin Descriptions
Figure 2. ZL2004 Pin Configurations (top view)
Table 4. Pin Descriptions
Pin
Label
Type1
1
DGND
PWR
2
SYNC
I/O, M2
3
4
5
6
7
8
9
10
11
SA0
SA1
ILIM
SCL
SDA
SALRT
FC
V0
V1
12
VMON
I, M
13
14
NC
VTRK
I
15
VSEN+
I
16
VSEN-
I
17
18
19
NC
ISENB
ISENA
I
I
FN6846 Rev. 3.00
February 15, 2011
Description
I, M
I/O
I/O
O
I
Digital ground. Connect to low impedance ground plane.
Clock synchronization input. Used to set the frequency of the internal switch
clock, to sync to an external clock or to output internal clock.
Serial address select pins. Used to assign unique address for each individual
device or to enable certain management features.
Current limit select. Sets the overcurrent threshold voltage for ISENA, ISENB.
Serial clock. Connect to external host and/or to other ZL devices.
Serial data. Connect to external host and/or to other ZL devices.
Serial alert. Connect to external host if desired.
Loop compensation selection pin.
I, M
Output voltage selection pins. Used to set VOUT set-point and VOUT max.
I, M
External voltage monitoring (Can be used for external driver bias monitoring for
Power good).
No Connect.
Tracking sense input. Used to track an external voltage source.
Differential Output voltage sense feedback. Connect to positive output regulation
point.
Differential Output voltage sense feedback. Connect to negative output regulation
point.
No Connect.
Differential voltage input for current sensing.
Differential voltage input for current sensing. High voltage (DCR).
Page 6 of 42
ZL2004
Table 4. Pin Descriptions (continued)
Pin
Label
Type1 Description
20
21
22
23
24
25
PWML
SGND
PWMH
VR
VDD3
V25
O
PWR
O
PWR
PWR
PWR
26
XTEMP
I
27
28
DDC
MGN
I
I
29
CFG
M
30
EN
I
31
SS
I, M
32
PG
O
EPAD
SGND
PWR
PWM Gate low signal.
Connect to low impedance ground plane. Internal connection to SGND.
PWM Gate High signal.
Internal 5V reference used to power internal drivers.
Supply voltage.
Internal 2.5 V reference used to power internal circuitry.
External temperature sensor input. Connect to external 2N3904 (Base Emitter
junction).
Single wire DDC bus (Current sharing, inter device communication).
VOUT margin control.
Configuration pin. Used to control the switching phase offset, sequencing and
other management features.
Enable. Active signal enables PWM switching.
Soft start delay and ramp select. Sets the delay from when EN is asserted until the
output voltage starts to ramp and the ramp time.
Power good output.
Exposed thermal pad. Connect to low impedance ground plane. Internal
connection to SGND.
Notes:
1. I = Input, O = Output, PWR = Power or Ground. M = Multi-mode pins. (Refer to page 11).
2. The SYNC pin can be used as a logic pin, a clock input or a clock output.
3. VDD is measured internally and the value is used to modify the PWM loop gain.
FN6846 Rev. 3.00
February 15, 2011
Page 7 of 42
ZL2004
3. Typical Application Circuit
The following application circuit represents a typical implementation of the ZL2004.
F.B.1
VIN 12V
CIN
3 x 10 µF
25 V
ENABLE
POWER GOOD OUTPUT
SGND
29
28
27
26
25
MGN
DDC
XTEMP
V25
3 SA0
4 SA1
ZL2004
5 ILIM
7 SDA
PWMH
22
SGND
21
PWML
20
ISENA
19
ISENB
18
NC
17
VIN
Power Train
Module
PWMH
GH
VOUT
PWMH
ZL1505
SW
PWML
GL
TEMP+
16 VSEN-
15 VSEN+
14 VRTK
13 NC
12 VMON
11 V1
9 FC
8 SALRT
10 V0
(OPTIONAL)2
23
PWML
6 SCL
I2C/SMBus
VR
GND
30
CFG
2 SYNC
24
VDD
31
EN
1 DGND
VDD
VDD
LSEL
HSEL
BST
32
SS
VBIAS
PG
(To VR)
10 µF
4V
CV25
DDC Bus 3
TEMP-
GND
CS+
CS-
EPAD
RTN
4.7 µF
6.3 V
100k
CVR
SGND
6.65k
Notes:
1. Ferrite bead is optional for input noise suppression.
2. The I2C/SMBus requires pull-up resistors. Please refer to the I2C/SMBus specifications for more details.
3. The DDC bus requires a pull-up resistor. The resistance will vary based on the capacitive loading of the bus (and on the number of devices
connected). The 10 kW default value, assuming a maximum of 100 pF per device, provides the necessary 1 µs pull-up rise time. Please refer to
section 6.11 for more details.
Figure 3. 12 V to 1.8 V / 20 A Application Circuit
(4.5 V UVLO, 5 ms SS delay, 5 ms SS ramp)
FN6846 Rev. 3.00
February 15, 2011
Page 8 of 42
ZL2004
4. ZL2004 Overview
4.1 Digital-DC Architecture
The ZL2004 is an innovative mixed-signal power
conversion and power management IC based on Zilker
Labs’ patented Digital-DC technology that provides an
integrated, high performance step-down converter for a
wide variety of power supply applications.
Today’s embedded power systems are typically
designed for optimal efficiency at maximum load,
reducing the peak thermal stress by limiting the total
thermal dissipation inside the system. Unfortunately,
many of these systems are often operated at load levels
far below the peak where the power system has been
optimized, resulting in reduced efficiency. While this
may not cause thermal stress to occur, it does
contribute to higher electricity usage and results in
higher overall system operating costs.
Zilker Labs’ efficiency-adaptive ZL2004 DC-DC
controller helps mitigate this scenario by enabling the
power converter to automatically change their
operating state to increase efficiency and overall
performance with little or no user interaction needed.
Its unique digital PWM loop utilizes an innovative
mixed-signal topology to enable precise control of the
power conversion process with no software required,
resulting in a very flexible device that is also easy to
use. An extensive set of power management functions
is fully integrated and can be configured using simple
pin connections or via the I2C/SMBus hardware
interface using standard PMBus commands. The user
configuration can be saved in an on-chip non-volatile
memory (NVM), allowing ultimate flexibility.
FN6846 Rev. 3.00
February 15, 2011
Once enabled, the ZL2004 is immediately ready to
regulate power and perform power management tasks
with no programming required. The ZL2004 can be
configured by simply connecting its pins according to
the tables provided in this document. Advanced
configuration options and real-time configuration
changes are available via the I2C/SMBus interface if
desired, and continuous monitoring of multiple
operating parameters is possible with minimal
interaction from a host controller. Integrated subregulation circuitry enables single supply operation
from any supply between 4.5 V and 14 V with no
secondary bias supplies needed.
Zilker Labs provides a comprehensive set of
application notes to assist with power supply design
and simulation. An evaluation board is also available to
help the user become familiar with the device. This
board can be evaluated as a stand-alone platform using
pin configuration settings. Additionally, a Windows™based GUI is provided to enable full configuration and
monitoring capability via the I2C/SMBus interface
using an available computer and the included USB
cable.
Please refer to www.zilkerlabs.com for access to the
most up-to-date documentation or call your local Zilker
Labs’ sales office to order an evaluation kit.
Page 9 of 42
ZL2004
4.2 Power Conversion Overview
Input Voltage Bus
>
PG
EN
MGN ILIM SS
VMON V(0,1)
FC
VDD
LDO
VTRK
Power Management
VR
NVM
PWMH
SYNC
GEN
Digital
Compensator
MOSFET
D-PWM
Pre
Drivers
Driver
PWML
VOUT
MOSFET
NLR
PLL
SYNC
ADC
-
VSEN
+
ISENA
ISENB
ADC
REFCN
DAC
VDD
DDC
I2C
MUX
SALRT
SDA
SCL
SA(0,1)
Voltage
Sensor
ADC
Communication
VSEN+
VSENXTEMP
TEMP
Sensor
Figure 4. ZL2004 Block Diagram
The ZL2004 operates as a voltage-mode, synchronous
buck converter with a selectable constant frequency
pulse width modulator (PWM) control scheme that
uses external driver, MOSFETs, capacitors, and an
inductor to perform power conversion.
VIN
ZL2004
DRIVER
VOUT
Figure 5. Synchronous Buck Converter
Figure 5 illustrates the basic synchronous buck
converter topology showing the primary power train
components. This converter is also called a step-down
converter, as the output voltage must always be lower
than the input voltage.
FN6846 Rev. 3.00
February 15, 2011
Dual output PWM ZL2004
The ZL2004 provides a dual PWM signal which
removes the need of a tri-state function and
significantly improves conversion performance.
The ZL2004 has been designed to drive the QH and
QL independently, allowing greater control of the
MOSFETs and higher overall performance. A special
driver with two PWM inputs is required (ZL1505).
Using two PWM signals (PWMH and PWML) offers
more options during fault event and pre-bias
conditions, eliminating the need for a tri-state driver
and reducing the delays associated with this scheme.
The ZL2004 has several features to improve the power
conversion efficiency. A non-linear response (NLR)
loop improves the response time and reduces the
output deviation as a result of a load transient. The
ZL2004 monitors the power converter’s operating
conditions and continuously adjusts the turn-on and
turn-off timing of the high-side and low-side
MOSFETs to optimize the overall efficiency of the
power supply. Adaptive performance optimization
algorithms such as dead-time control, diode emulation,
Page 10 of 42
ZL2004
and adaptive frequency are available to provide greater
efficiency improvement.
The ZL2004 can also be used with a single-ended
MOSFET driver. Simple parameter changes allow the
device to use a single PWM to drive the logic input of
such drivers. The trade-offs for using this mode may
include reduced efficiency, reduced ramp-up timing
accuracy, and degraded pre-bias protection.
Table 5. Multi-mode Pin Configuration
Pin Tied To
Value
LOW
< 0.8 VDC
(Logic LOW)
OPEN
No connection
(N/C)
HIGH
> 2.0 VDC
(Logic HIGH)
Resistor to SGND
Set by resistor value
4.3 Power Management Overview
The ZL2004 incorporates a wide range of configurable
power management features that are simple to
implement with no external components. Additionally,
the ZL2004 includes circuit protection features that
continuously safeguard the device and load from
damage due to unexpected system faults. The ZL2004
can continuously monitor input voltage, output
voltage/current, internal temperature, and the
temperature of an external thermal diode. A Power
Good output signal is also included to enable power-on
reset functionality for an external processor.
All power management functions can be configured
using either pin configuration techniques (see Figure 6)
or via the I2C/SMBus interface. Monitoring parameters
can also be pre-configured to provide alerts for specific
conditions. See Application Note AN33 for more
details on SMBus monitoring.
4.4 Multi-mode Pins
In order to simplify circuit design, the ZL2004
incorporates patented multi-mode pins that allow the
user to easily configure many aspects of the device
with no programming. Most power management
features can be configured using these pins. The multimode pins can respond to four different connections as
shown in Table 5. These pins are sampled when power
is applied or by issuing a PMBus Restore command
(See Application Note AN33).
Pin-strap Settings: This is the simplest implementation
method, as no external components are required. Using
this method, each pin can take on one of three possible
states: LOW, OPEN, or HIGH. These pins can be
connected to the V25 pin for logic HIGH settings as
this pin provides a regulated voltage higher than 2 V.
Using a single pin, one of three settings can be
selected. Using two pins, one of nine settings can be
selected.
FN6846 Rev. 3.00
February 15, 2011
Logic
high
Open
ZL
ZL
Multi-mode Pin
Multi-mode Pin
RSET
Logic
low
Pin-strap
Settings
Resistor
Settings
Figure 6. Pin-strap and Resistor Setting Examples
Resistor Settings: This method allows a greater range
of adjustability when connecting a finite value resistor
(in a specified range) between the multi-mode pin and
SGND. Standard 1% resistor values are used, and only
every fourth E96 resistor value is used so the device
can reliably recognize the value of resistance
connected to the pin while eliminating the error
associated with the resistor accuracy. Up to 31 unique
selections are available using a single resistor.
I2C/SMBus Method: Almost any ZL2004 function can
be configured via the I2C/SMBus interface using
standard PMBus commands. Additionally, any value
that has been configured using the pin-strap or resistor
setting methods can also be re-configured and/or
verified via the I2C/SMBus. See Application Note
AN33 for more details.
The SMBus device address and VOUT_MAX are the
only parameters that must be set by external pins. All
other device parameters can be set via the I2C/SMBus.
The device address is set using the SA0 and SA1 pins.
VOUT_MAX is determined as 10% greater than the
voltage set by the V0 and V1 pins.
Page 11 of 42
ZL2004
5. Power Conversion Functional Description
5.1 Internal Bias Regulators and Input Supply
Connections
The ZL2004 employs two internal low dropout (LDO)
regulators to supply bias voltages for internal circuitry,
allowing it to operate from a single input supply. The
internal bias regulators are as follows:
VR: The VR LDO provides a regulated 5 V bias
supply for the MOSFET pre-driver circuits. It is
powered from the VDD pin. A 4.7 µF filter
capacitor is required at the VR pin.
V25: The V25 LDO provides a regulated 2.5 V bias
supply for the main controller circuitry. It is
powered from an internal 5 V node. A 10 µF
filter capacitor is required at the V25 pin.
When the input supply (VDD) is higher than 5.5 V, the
VR pin should not be connected to any other pins. It
should only have a filter capacitor attached as shown in
Figure 7. Due to the dropout voltage associated with
the VR bias regulator, the VDD pin must be connected
to the VR pin for designs operating from a supply
below 5.5 V. Figure 7 illustrates the required
connections for both cases.
VIN
VIN
VDD
VDD
ZL2004
ZL2004
VR
4.5V ≤VIN ≤ 5.5V
VR
5.5V fsw/10
fsw/10 > fzesr > fsw/30
fsw/30 > fzesr > fsw/60
fzesr > fsw/10
fsw/10 > fzesr > fsw/30
fsw/30 > fzesr > fsw/60
fzesr > fsw/10
fsw/10 > fzesr > fsw/30
fsw/30 > fzesr > fsw/60
fzesr > fsw/10
fsw/10 > fzesr > fsw/30
fsw/30 > fzesr > fsw/60
fzesr > fsw/10
fsw/10 > fzesr > fsw/30
fsw/30 > fzesr > fsw/60
fzesr > fsw/10
fsw/10 > fzesr > fsw/30
fsw/30 > fzesr > fsw/60
10 kΩ
11 kΩ
12.1 kΩ
13.3 kΩ
14.7 kΩ
16.2 kΩ
17.8 kΩ
19.6 kΩ
21.5 kΩ
23.7 kΩ
26.1 kΩ
28.7 kΩ
31.6 kΩ
34.8 kΩ
38.3 kΩ
42.2 kΩ
46.4 kΩ
51.1 kΩ
It is therefore advantageous to minimize this dead-time
to provide optimum circuit efficiency. In the first order
model of a buck converter, the duty cycle is
determined by the equation:
D
VOUT
VIN
However, non-idealities exist that cause the real duty
cycle to extend beyond the ideal. Dead-time is one of
those non-idealities that can be manipulated to improve
efficiency. The ZL2004 has an internal algorithm that
constantly adjusts dead-time non-overlap to minimize
duty cycle, thus maximizing efficiency.
Page 26 of 42
ZL2004
This algorithm is independent of application circuit
parameters such as MOSFET type, gate driver delays,
rise and fall times and circuit layout.
In addition, it does not require drive or MOSFET
voltage or current waveform measurements.
5.13 Adaptive Diode Emulation
Most power converters use synchronous rectification to
optimize efficiency over a wide range of input and
output conditions. However, at light loads the
synchronous MOSFET will typically sink current and
introduce additional energy losses associated with
higher peak inductor currents, resulting in reduced
efficiency. Adaptive diode emulation mode turns off
the low-side FET gate drive at low load currents to
prevent the inductor current from going negative,
reducing the energy losses and increasing overall
efficiency. Diode emulation is available to single-phase
devices only.
Note: the overall bandwidth of the device may be
reduced when in diode emulation mode. It is
recommended that diode emulation is disabled prior to
applying significant load steps.
5.14 Adaptive Frequency Control
Since switching losses contribute to the efficiency of
the power converter, reducing the switching frequency
will reduce the switching losses and increase
efficiency. The ZL2004 includes Adaptive Frequency
Control mode, which effectively reduces the observed
switching frequency as the load decreases.
Adaptive frequency mode is enabled by setting bit 0 of
MISC_CONFIG to 1 and is only available while the
device is operating within Adaptive Diode Emulation
Mode. As the load current is decreased, diode
emulation mode decreases the GL on-time to prevent
negative inductor current from flowing. As the load is
decreased further, the GH pulse width will begin to
FN6846 Rev. 3.00
February 15, 2011
decrease while
frequency, fPROG
command).
maintaining the programmed
(set by the FREQ_SWITCH
fSW(D)
Switching
Frequency
This circuit will null out dead-time differences due to
component variation, temperature, and loading effects.
fPROG
fMIN
0
D
DNOM
2
Duty Cycle
Figure 16. Adaptive Frequency
Once the GH pulse width (D) reaches 50% of the
nominal duty cycle, DNOM (determined by Vin and
Vout), the switching frequency will start to decrease
according to the following equation:
DNOM
then
2
2( fSW fMIN )
D fMIN
fSW(D) =
DNOM
If D
Otherwise fSW(D) = fPROG
This is illustrated in Figure 16. Due to quantizing
effects inside the IC, the ZL2004 will decrease its
frequency in steps between fSW and fMIN. The quantity
and magnitude of the steps will depend on the
difference between fSW and fMIN as well as the
frequency range.
It should be noted that adaptive frequency mode is not
available for current sharing groups and is not allowed
when the device is placed in auto-detect mode and a
clock source is present on the SYNC pin, or if the
device is outputting a clock signal on its SYNC pin.
Page 27 of 42
ZL2004
6. Power Management Functional Description
6.1 Input Undervoltage Lockout
The input undervoltage lockout (UVLO) prevents the
ZL2004 from operating when the input falls below a
preset threshold, indicating the input supply is out of
its specified range. The UVLO threshold (VUVLO) can
be set between 4.5V and 10.8 V using the SS pin. The
simplest implementation is to connect the SS pin as
shown in Table 11.
The UVLO voltage can also be set to any value
between 2.85 V and 16 V via the I2C/SMBus interface.
Once an input undervoltage fault condition occurs, the
device can respond in a number of ways as follows:
1. Continue operating without interruption.
2. Continue operating for a given delay period,
followed by shutdown if the fault still exists. The
device will remain in shutdown until instructed to
restart.
3. Initiate an immediate shutdown until the fault has
been cleared. The user can select a specific number
of retry attempts.
The default response from a UVLO fault is an
immediate shutdown of the device. The device will
continuously check for the presence of the fault
condition. If the fault condition is no longer present,
the ZL2004 will be re-enabled.
Please refer to Application Note AN33 for details on
how to configure the UVLO threshold or to select
specific UVLO fault response options via the
I2C/SMBus interface.
2. Turn off the high-side MOSFET and turn on the
low-side MOSFET. The low-side MOSFET
remains ON until the device attempts a restart.
The default response from an overvoltage fault is to
immediately shut down. The device will continuously
check for the presence of the fault condition, and when
the fault condition no longer exists the device will be
re-enabled.
For continuous overvoltage protection when operating
from an external clock, the only allowed response is an
immediate shutdown.
Refer to AN33 for details on how to select specific
overvoltage fault response options.
6.3 Output Pre-Bias Protection
An output pre-bias condition exists when an externally
applied voltage is present on a power supply’s output
before the power supply’s control IC is enabled.
Certain applications require that the converter not be
allowed to sink current during start up if a pre-bias
condition exists at the output. The ZL2004 provides
pre-bias protection by sampling the output voltage
prior to initiating an output ramp.
If a pre-bias voltage lower than the target voltage exists
after the pre-configured delay period has expired, the
target voltage is set to match the existing pre-bias
voltage and both drivers are enabled. The output
voltage is then ramped to the final regulation value at
the ramp rate set by the SS pin.
6.2 Output Overvoltage Protection
The ZL2004 offers an internal output overvoltage
protection circuit that can be used to protect sensitive
load circuitry from being subjected to a voltage higher
than its prescribed limits. A hardware comparator is
used to compare the actual output voltage (seen at the
VSEN pin) to a threshold set to 15% higher than the
target output voltage (the default setting). If the VSEN
voltage exceeds this threshold, the PG pin will deassert and the device can then respond in a number of
ways as follows:
1. Initiate an immediate shutdown until the fault has
been cleared. The user can select a specific number
of retry attempts.
FN6846 Rev. 3.00
February 15, 2011
Page 28 of 42
ZL2004
If a pre-bias voltage higher than the overvoltage limit
exists, the device will not initiate a turn-on sequence
and will declare an overvoltage fault condition to exist.
In this case, the device will respond based on the
output overvoltage fault response method that has been
selected. See Section 6.2 “Output Overvoltage
Protection,” for response options due to an overvoltage
condition.
Pre-bias protection is not offered for current sharing
groups that also have tracking enabled.
6.4 Output Overcurrent Protection
The ZL2004 can protect the power supply from
damage if the output is shorted to ground or if an
overload condition is imposed on the output. Once the
current limit threshold has been selected (see Section
5.8 “Current Limit Threshold Selection”), the user may
determine the desired course of action in response to
the fault condition. The following overcurrent
protection response options are available:
1. Initiate a shutdown and attempt to restart an
infinite number of times with a preset delay period
between attempts.
Figure 17. Output Responses to Pre-bias Voltages
The actual time the output will take to ramp from the
pre-bias voltage to the target voltage will vary
depending on the pre-bias voltage but the total time
elapsed from when the delay period expires and when
the output reaches its target value will match the preconfigured ramp time. See Figure 17.
If a pre-bias voltage higher than the target voltage
exists after the pre-configured delay period has
expired, the target voltage is set to match the existing
pre-bias voltage and both drivers are enabled with a
PWM duty cycle that would ideally create the pre-bias
voltage. Once the pre-configured soft-start ramp period
has expired, the PG pin will be asserted (assuming the
pre-bias voltage is not higher than the overvoltage
limit). The PWM will then adjust its duty cycle to
match the original target voltage and the output will
ramp down to the pre-configured output voltage.
FN6846 Rev. 3.00
February 15, 2011
2. Initiate a shutdown and attempt to restart a preset
number of times with a preset delay period
between attempts.
3. Continue operating for a given delay period,
followed by shutdown if the fault still exists.
4. Continue operating through the fault (this could
result in permanent damage to the power supply).
5. Initiate an immediate shutdown.
The default response from an overcurrent fault is an
immediate shutdown of the device. The device will
continuously check for the presence of the fault
condition, and if the fault condition no longer exists the
device will be re-enabled.
Refer to AN33 for details on how to select specific
overcurrent fault response options.
Page 29 of 42
ZL2004
6.5 Thermal Overload Protection
6.6 Voltage Tracking
The ZL2004 includes an on-chip thermal sensor that
continuously measures the internal temperature of the
die and shuts down the device when the temperature
exceeds the preset limit. The default temperature limit
is set to 125°C in the factory, but the user may set the
limit to a different value if desired. See Application
Note AN33 for details. Note that setting a higher
thermal limit via the I2C/SMBus interface may result in
permanent damage to the device. Once the device has
been disabled due to an internal temperature fault, the
user may select one of several fault response options as
follows:
Numerous high performance systems place stringent
demands on the order in which the power supply
voltages are turned on. This is particularly true when
powering FPGAs, ASICs, and other advanced
processor devices that require multiple supply voltages
to power a single die. In most cases, the I/O interface
operates at a higher voltage than the core and therefore
the core supply voltage must not exceed the I/O supply
voltage according to the manufacturers' specifications.
1. Initiate a shutdown and attempt to restart an
infinite number of times with a preset delay period
between attempts.
2. Initiate a shutdown and attempt to restart a preset
number of times with a preset delay period
between attempts.
3. Continue operating for a given delay period,
followed by shutdown if the fault still exists.
4. Continue operating through the fault (this could
result in permanent damage to the power supply).
5. Initiate an immediate shutdown.
If the user has configured the device to restart, the
device will wait the preset delay period (if configured
to do so) and will then check the device temperature. If
the temperature has dropped below a threshold that is
approx 15°C lower than the selected temperature fault
limit, the device will attempt to re-start. If the
temperature still exceeds the fault limit the device will
wait the preset delay period and retry again.
The default response from a temperature fault is an
immediate shutdown of the device. The device will
continuously check for the fault condition, and once
the fault has cleared the ZL2004 will be re-enabled.
FN6846 Rev. 3.00
February 15, 2011
The ZL2004 integrates a lossless tracking scheme that
allows its output to track a voltage that is applied to the
VTRK pin with no external components required. The
VTRK pin is an analog input that, when tracking mode
is enabled, configures the voltage applied to the VTRK
pin to act as a reference for the device’s output
regulation.
Figure 18 illustrates the typical connection and the two
tracking modes:
1. Coincident. This mode configures the ZL2004 to
ramp its output voltage at the same rate as the
voltage applied to the VTRK pin.
2. Ratiometric. This mode configures the ZL2004 to
ramp its output voltage at a rate that is a percentage
of the voltage applied to the VTRK pin. The
default setting is 50%, but an external resistor
string may be used to configure a different tracking
ratio.
The master ZL2004 device in a tracking group is
defined as the device that has the highest target output
voltage within the group. This master device will
control the ramp rate of all tracking devices and is not
configured for tracking mode. A delay of at least 10 ms
must be configured into the master device using the SS
pin and the user may also configure a specific ramp
rate using the SS pin.
Any device that is configured for tracking mode will
ignore its soft-start delay and ramp time settings (SS
pin) and its output will take on the turn-on/turn-off
characteristics of the reference voltage present at the
VTRK pin.
Page 30 of 42
ZL2004
The tracking mode for all other devices can be set by
connecting a resistor from the SS pin to ground
according to Table 20. All of the ENABLE pins in the
tracking group must be connected together and driven
by a single logic source. CFG pin needs also to have
been set to the appropriate value to enable tracking
mode using pin-strap.
Tracking mode can also be configured via the
I2C/SMBus interface by using the TRACK_CONFIG
command.
Note that current sharing groups that are also
configured to track another voltage do not offer prebias protection; a minimum load should therefore be
enforced to avoid the output voltage from being held
up by an outside force. Additionally, a device set up
for tracking must have both Alternate Ramp Control
and Precise Ramp-Up Delay disabled.
VIN
PWMH
ZL
Driver
MOSFET
VTRK
PWML
L1
VOUT
C1
VTRK
VOUT
VTRK
VOUT
6.7 Voltage Margining
The ZL2004 offers a simple means to vary its output
higher or lower than its nominal voltage setting in
order to determine whether the load device is capable
of operating over its specified supply voltage range.
The MGN command is set by driving the MGN pin or
through the I2C/SMBus interface. The MGN pin is a
TTL-compatible input that is continuously monitored
and can be driven directly by a processor I/O pin or
other logic-level output.
The ZL2004’s output will be forced higher than its
nominal set point when the MGN command is set
HIGH, and the output will be forced lower than its
nominal set point when the MGN command is set
LOW. Default margin limits of VNOM ±5% are preloaded in the factory, but the margin limits can be
modified through the I2C/SMBus interface to as high
as VNOM + 10% or as low as 0 V, where VNOM is the
nominal output voltage set point determined by the V0
and V1 pins. A safety feature prevents the user from
configuring the output voltage to exceed VNOM + 10%
under any conditions.
The margin limits and the MGN command can both be
set individually through the I2C/SMBus interface.
Additionally, the transition rate between the nominal
output voltage and either margin limit can be
configured through the I2C interface. Please refer to
Application Note AN33 for detailed instructions on
modifying the margining configurations.
Time
Coincident
6.8 External Voltage Monitoring
Ratiometric
The voltage monitoring (VMON) pin is available to
monitor the voltage supply for the external driver IC. If
the voltage falls below a predefined threshold value
(adjustable through a PMBus command), the device
will fault and stop sending PWM signals. A 1/16
external resistor divider is required to keep the
maximum voltage on this pin to less than 1.15 V.
VOUT
VTRK
VOUT
Time
Figure 18. Tracking Modes
FN6846 Rev. 3.00
February 15, 2011
Page 31 of 42
ZL2004
Table 20. Tracking Mode Configuration
RSS
UVLO
Tracking
Ratio
19.6 kW
21.5 kW
28.7 kW
Output not allowed to decrease before PG
Limited by VTRK
pin voltage
Output not allowed to decrease before PG
Limited by target
voltage
Output not allowed to decrease before PG
Limited by VTRK
pin voltage
Output not allowed to decrease before PG
Limited by target
voltage
Output not allowed to decrease before PG
Limited by VTRK
pin voltage
Output not allowed to decrease before PG
Limited by target
voltage
Output not allowed to decrease before PG
Limited by VTRK
pin voltage
Output not allowed to decrease before PG
50%
34.8 kW
38.3 kW
42.2 kW
46.4 kW
100%
51.1 kW
61.9 kW
Limited by target
voltage
4.5 V
31.6 kW
56.2 kW
Ramp-up / Ramp-down Behavior
100%
23.7 kW
26.1 kW
Upper Track Limit
10.8 V
68.1 kW
75 kW
50%
82.5 kW
6.9 I2C/SMBus Communications
The ZL2004 provides an I2C/SMBus digital interface
that enables the user to configure all aspects of the
device operation as well as monitor the input and
output parameters. The ZL2004 can be used with any
standard 2-wire I2C host device. In addition, the device
is compatible with SMBus version 2.0 and includes an
SALRT line to help mitigate bandwidth limitations
related to continuous fault monitoring. Pull-up resistors
are required on the I2C/SMBus. The ZL2004 accepts
most standard PMBus commands. When controlling
the device with PMBus commands, it is recommended
that the enable pin is tied to SGND.
6.10 I2C/SMBus Device Address Selection
When communicating with multiple SMBus devices
using the I2C/SMBus interface, each device must have
its own unique address so the host can distinguish
between the devices. The device address can be set
according to the pin-strap options listed in Table 21.
Address values are right-justified.
FN6846 Rev. 3.00
February 15, 2011
Output will always follow VTRK
Output will always follow VTRK
Output will always follow VTRK
Output will always follow VTRK
Output will always follow VTRK
Output will always follow VTRK
Output will always follow VTRK
Output will always follow VTRK
Table 21. SMBus Device Address Selection
SA0
LOW
OPEN
HIGH
LOW
0x20
0x21
0x22
SA1
OPEN
0x23
0x24
0x25
HIGH
0x26
0x27
Reserved
If additional device addresses are required, a resistor
can be connected to the SA0 pin according to Table 22
to provide up to 25 unique device addresses. In this
case, the SA1 pin should be tied to SGND.
If more than 25 unique device addresses are required or
if other SMBus address values are desired, both the SA0
and SA1 pins can be configured with a resistor to SGND
according to the following equation and Table 23.
SMBus address = 25 x (SA1 index) + (SA0 index)
(in decimal)
Page 32 of 42
ZL2004
Table 22. SMBus Address Values
SMBus
RSA
RSA
Address
10 kW
34.8 kW
0x00
11 kW
38.3 kW
0x01
12.1 kW
42.2 kW
0x02
13.3 kW
46.4 kW
0x03
14.7 kW
51.1 kW
0x04
16.2 kW
56.2 kW
0x05
17.8 kW
61.9 kW
0x06
19.6 kW
68.1 kW
0x07
21.5 kW
75 kW
0x08
23.7 kW
82.5
kW
0x09
26.1 kW
90.9 kW
0x0A
28.7 kW
100 kW
0x0B
31.6 kW
0x0C
6.11 Digital-DC Bus
SMBus
Address
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
Using this method, the user can theoretically configure
up to 625 unique SMBus addresses, however the
SMBus is inherently limited to 128 devices so
attempting to configure an address higher than 128
(0x80) will cause the device address to repeat (i.e,
attempting to configure a device address of 129 (0x81)
would result in a device address of 1. Therefore, the
user should use index values 0-4 on the SA1 pin and
the full range of index values on the SA0 pin, which
will provide 125 device address combinations.
Table 23. SMBus Address Index Values
SA0 or
SA0 or
RSA
SA1
RSA
SA1 Index
Index
10 kW
34.8 kW
0
13
11 kW
38.3 kW
1
14
12.1 kW
42.2 kW
2
15
13.3 kW
46.4 kW
3
16
14.7 kW
51.1 kW
4
17
16.2 kW
56.2 kW
5
18
17.8 kW
61.9 kW
6
19
19.6 kW
68.1 kW
7
20
21.5 kW
75 kW
8
21
23.7 kW
82.5 kW
9
22
26.1 kW
90.9 kW
10
23
28.7 kW
100 kW
11
24
31.6 kW
12
FN6846 Rev. 3.00
February 15, 2011
The Digital-DC Communications (DDC) bus is used to
communicate between Zilker Labs Digital-DC devices.
This dedicated bus provides the communication
channel between devices for features such as
sequencing, fault spreading, and current sharing. The
DDC pin on all Digital-DC devices in an application
should be connected together. A pull-up resistor is
required on the DDC bus in order to guarantee the rise
time as follows:
Rise time = RPU * CLOAD ≈ 1 µs,
where RPU is the DDC bus pull-up resistance and
CLOAD is the bus loading. The pull-up resistor may be
tied to VR or to an external 3.3V or 5V supply as long
as this voltage is present prior to or during device
power-up. As rules of thumb, each device connected to
the DDC bus presents approx 10 pF of capacitive
loading, and each inch of FR4 PCB trace introduces
approx 2 pF. The ideal design will use a central pull-up
resistor that is well-matched to the total load
capacitance. In power module applications, the user
should consider whether to place the pull-up resistor on
the module or on the PCB of the end application. The
minimum pull-up resistance should be limited to a
value that enables any device to assert the bus to a
voltage that will ensure a logic 0 (typically 0.8 V at the
device monitoring point) given the pull-up voltage (5
V if tied to VR) and the pull-down current capability of
the ZL2004 (nominally 4 mA).
6.12 Phase Spreading
When multiple point of load converters share a
common DC input supply, it is desirable to adjust the
clock phase offset of each device such that not all
devices start to switch simultaneously. Setting each
converter to start its switching cycle at a different point
in time can dramatically reduce input capacitance
requirements and efficiency losses. Since the peak
current drawn from the input supply is effectively
spread out over a period of time, the peak current
drawn at any given moment is reduced and the power
losses proportional to the IRMS2 are reduced
dramatically.
Page 33 of 42
ZL2004
In order to enable phase spreading, all converters must
be synchronized to the same switching clock. The CFG
pin is used to set the configuration of the SYNC pin for
each device as described in Section 5.6 “Switching
Frequency and PLL” on Page 17.
Selecting the phase offset for the device is
accomplished by selecting a device address according
to the following equation:
Phase offset = device address x 45°
For example:
A device address of 0x00 or 0x20 would
configure no phase offset
A device address of 0x01 or 0x21 would
configure 45° of phase offset
A device address of 0x02 or 0x22 would
configure 90° of phase offset
The phase offset of each device may also be set to any
value between 0° and 360° in 22.5° increments via the
I2C/SMBus interface. Refer to Application Note AN33
for further details.
6.13 Output Sequencing
A group of Zilker Labs devices may be configured to
power up in a predetermined sequence. This feature is
especially useful when powering advanced processors,
FPGAs, and ASICs that require one supply to reach its
operating voltage prior to another supply reaching its
operating voltage in order to avoid latch-up from
occurring. Multi-device sequencing can be achieved by
configuring each device through the I2C/SMBus
interface or by using Zilker Labs patented autonomous
sequencing mode.
Autonomous sequencing mode configures sequencing
by using events transmitted between devices over the
DDC bus. This mode is not available on current
sharing rails.
The sequencing order is determined using each
device’s SMBus address. Using autonomous
sequencing mode (configured using the CFG pin), the
devices must be assigned sequential SMBus addresses
with no missing addresses in the chain. This mode will
also constrain each device to have a phase offset
according to its SMBus device address as described in
Section 6.12 “Phase Spreading”.
Table 24. CFG Pin Configurations for Sequencing and Tracking
SYNC Pin
RCFG
Sequencing Configuration
Configuration
Input
10 kW
Auto detect
Sequencing is disabled, Tracking is Disabled.
11 kW
Output
12.1 kW
Input
14.7 kW
The ZL2004 is configured as the first device in a nested sequencing
group. Turn on order is based on the device SMBus address. Tracking
Auto
detect
16.2 kW
is Disabled.
Output
17.8 kW
Input
21.5 kW
The ZL2004 is configured as a last device in a nested sequencing
Auto detect
group. Turn on order is based on the device SMBus address. Tracking
23.7 kW
is Disabled.
Output
26.1 kW
Input
31.6 kW
The ZL2004 is configured as the middle device in a nested sequencing
group. Turn on order is based on the device SMBus address. Tracking
Auto detect
34.8 kW
is Disabled.
Output
38.3 kW
Input
46.4 kW
Auto detect
Sequencing is disabled, Tracking is Enabled
51.1 kW
Output
56.2 kW
FN6846 Rev. 3.00
February 15, 2011
Page 34 of 42
ZL2004
Multiple device sequencing may also be achieved by
issuing PMBus commands to assign the preceding
device in the sequencing chain as well as the device
that will follow in the sequencing chain. This method
places fewer restrictions on the device SMBus address
(no need of sequential address) and also allows the user
to assign any phase offset to any device irrespective of
its SMBus address.
Paralleling multiple ZL2004 devices can be used to
increase the output current capability of a single power
rail. By connecting the DDC pins of each device
together and configuring the devices as a current
sharing rail, the units will share the current equally
within a few percent.
Figure 19 shows a typical connection for three devices.
The ZL2004 uses a low-bandwidth, first-order digital
current sharing technique to balance the unequal device
output loading by aligning the load lines of member
devices to a reference device.
Droop resistance is used to add artificial resistance in
the output voltage path to control the slope of the load
line curve, calibrating out the physical parasitic
mismatches due to power train components and PCB
layout.
VIN
3.3V - 5V
CIN
DDC
ZL
Driver
Sequencing is configured by connecting a resistor from
the CFG pin to ground as described in Table 24. The
CFG pin is also used to set the configuration of the
SYNC pin as well as to determine the sequencing
method and order. Please refer to 5.6 “Switching
Frequency and PLL” for more details on the operating
parameters of the SYNC pin.
6.15 Active Current Sharing
COUT
The Enable pins of all devices in a sequencing group
must be tied together and driven high to initiate a
sequenced turn-on of the group. Enable must be driven
low to initiate a sequenced turnoff of the group.
CIN
DDC
ZL
Refer to Application Note AN33 for details on
sequencing via the I2C/SMBus interface.
Driver
The sequencing group will turn on in order starting
with the device with the lowest SMBus address and
will continue through to turn on each device in the
address chain until all devices connected have been
turned on. When turning off, the device with the
highest SMBus address will turn off first followed in
reverse order by the other devices in the group.
6.14 Fault Spreading
FN6846 Rev. 3.00
February 15, 2011
CIN
DDC
ZL
Driver
Digital DC devices can be configured to broadcast a
fault event over the DDC bus to the other devices in
the group. When a non-destructive fault occurs and the
device is configured to shut down on a fault, the device
will shut down and broadcast the fault event over the
DDC bus. The other devices on the DDC bus will shut
down together if configured to do so, and will attempt
to re-start in their prescribed order if configured to do
so.
VOUT
COUT
COUT
Figure 19. Current Sharing Group
Upon system start-up, the device with the lowest
member position as selected in ISHARE_CONFIG is
defined as the reference device. The remaining devices
are members. The reference device broadcasts its
current over the DDC bus. The members use the
reference current information to trim their voltages
(VMEMBER) to balance the current loading of each
device in the system.
Page 35 of 42
ZL2004
6.16 Phase Adding/Dropping
The ZL2004 allows multiple power converters to be
connected in parallel to supply higher load currents
than can be addressed using a single-phase design. In
doing so, the power converter is optimized at a load
current range that requires all phases to be operational.
During periods of light loading, it may be beneficial to
disable one or more phases in order to eliminate the
current drain and switching losses associated with
those phases, resulting in higher efficiency.
VREFERENCE
VOUT
-R
VMEMBER
-R
IMEMBER
IOUT
IREFERENCE
Figure 20. Active Current Sharing
Figure 20 shows that, for load lines with identical
slopes, the member voltage is increased towards the
reference voltage which closes the gap between the
inductor currents.
The relation between reference and member current
and voltage is given by the following equation:
Vmember VOUT R I REFERENCE I MEMBER
where R is the value of the droop resistance.
The ISHARE_CONFIG command is used to configure
the device for active current sharing. The default
setting is a stand-alone non-current sharing device. A
current sharing rail can be part of a system sequencing
group.
For fault configuration, the current share rail is
configured in a quasi-redundant mode. In this mode,
when a member device fails, the remaining members
will continue to operate and attempt to maintain
regulation. The device with the lowest member
position will become the reference. If fault spreading is
enabled, the current share rail failure is not broadcast
until the entire current share rail fails.
Up to eight (8) devices can be configured in a given
current sharing rail.
FN6846 Rev. 3.00
February 15, 2011
The ZL2004 offers the ability to add and drop phases
using a simple command in response to an observed
load current change, enabling the system to
continuously optimize overall efficiency across a wide
load range. All phases in a current share rail are
considered active prior to the current sharing rail ramp
to power-good.
Phases can be dropped after power-good is reached.
Any member of the current sharing rail can be
dropped. If the reference device is dropped, the
remaining active device with the lowest member
position will become the new reference.
Additionally, any change to the number of members of
a current sharing rail will precipitate autonomous phase
distribution within the rail where all active phases
realign their phase position based on their order within
the number of active members.
If the members of a current sharing rail are forced to
shut down due to an observed fault, all members of the
rail will attempt to re-start simultaneously after the
fault has cleared.
6.17 Monitoring via I2C/SMBus
A system controller can monitor a wide variety of
different ZL2004 system parameters through the
I2C/SMBus interface. The device can monitor for fault
conditions by monitoring the SALRT pin, which will
be asserted when any number of pre-configured fault
conditions occur.
Page 36 of 42
ZL2004
The device can also be monitored continuously for any
number of power conversion parameters including but
not limited to the following:
Input voltage
Output voltage
Output current
Internal junction temperature
Temperature of an external device
Switching frequency
Duty cycle
The PMBus Host should respond to SALRT as
follows:
1. ZL device pulls SALRT Low.
2. PMBus Host detects that SALRT is now low,
performs transmission with Alert Response
Address to find which ZL device is pulling
SALRT low
3. PMBus Host talks to the ZL device that has
pulled SALRT low. The actions that the host
performs are up to the System Designer.
If multiple devices are faulting, SALRT will still be
low after doing the above steps and will require
transmission with the Alert Response Address
repeatedly until all faults are cleared.
Please refer to Application Note AN33 for details on
how to monitor specific parameters via the I2C/SMBus
interface.
6.18 Temperature Monitoring Using the XTEMP Pin
The ZL2004 supports measurement of an external
device temperature using either a thermal diode
integrated in a processor, FPGA or ASIC, or using a
discrete diode-connected 2N3904 NPN transistor.
Figure 21 illustrates the typical connections required.
FN6846 Rev. 3.00
February 15, 2011
XTEMP
100pF
ZL
2N3904
SGND
Discrete NPN
µP
FPGA
DSP
ASIC
XTEMP
100pF
ZL
SGND
Embedded Thermal Diode
Figure 21. External Temperature Monitoring
6.19 Snapshot™ Parameter Capture
The ZL2004 offers a special mechanism that enables
the user to capture parametric data during normal
operation or following a fault.
The Snapshot
functionality is enabled by setting bit 1 of
MISC_CONFIG to 1.
The Snapshot feature enables the user to read the
parameters listed in Table 25 via a block read transfer
through the SMBus. This can be done during normal
operation, although it should be noted that reading the
22 bytes will occupy the SMBus for some time.
The SNAPSHOT_CONTROL command enables the
user to store the snapshot parameters to Flash memory
in response to a pending fault as well as to read the
stored data from Flash memory after a fault has
occurred. Table 26 describes the usage of this
command.
Automatic writes to Flash memory
following a fault are triggered when any fault threshold
level is exceeded, provided that the specific fault’s
response is to shut down (writing to Flash memory is
not allowed if the device is configured to re-try
following the specific fault condition).
Page 37 of 42
ZL2004
Table 25. Snapshot Parameters
Byte
Description
31:22
Reserved
21:20
Vin
19:18
Vout
17:16
Iout,avg
15:14
Iout,peak
13:12
Duty cycle
11:10
Internal temp
9:8
External temp
7:6
fsw
5
Vout status
4
Iout status
3
Input status
2
Temp status
1
CML status
0
Mfr specific status
Format
Linear
Linear
Vout Linear
Linear
Linear
Linear
Linear
Linear
Linear
Byte
Byte
Byte
Byte
Byte
Byte
It should also be noted that the device’s VDD voltage
must be maintained during the time when the device is
writing the data to Flash memory; a process that
requires between 700-1400 µs depending on whether
the data is set up for a block write. Undesirable results
may be observed if the device’s VDD supply drops
below 3.0 V during this process.
Table 26. SNAPSHOT_CONTROL Command
Data
Value
Description
1
Copies current SNAPSHOT values from
Flash memory to RAM for immediate access
using SNAPSHOT command.
2
Writes current SNAPSHOT values to Flash
memory. Only available when device is
disabled.
In the event that the device experiences a fault and
power is lost, the user can extract the last SNAPSHOT
parameters stored during the fault by writing a 1 to
SNAPSHOT_CONTROL (transfers data from Flash
FN6846 Rev. 3.00
February 15, 2011
memory to RAM) and then issuing a SNAPSHOT
command (reads data from RAM via SMBus).
6.20 Non-Volatile Memory and Device Security
Features
The ZL2004 has internal non-volatile memory where
user configurations are stored. Integrated security
measures ensure that the user can only restore the
device to a level that has been made available to them.
Refer to Section 5.3“Start-up Procedure,” for details on
how the device loads stored values from internal
memory during start-up. During the initialization
process, the ZL2004 checks for stored values contained
in its internal non-volatile memory. The ZL2004 offers
two internal memory storage units that are accessible
by the user as follows:
1. Default Store: A power supply module
manufacturer may want to protect the module from
damage by preventing the user from being able to
modify certain values that are related to the
physical construction of the module. In this case,
the module manufacturer would use the Default
Store and would allow the user to restore the
device to its default setting but would restrict the
user from restoring the device to the factory
settings.
2. User Store: The manufacturer of a piece of
equipment may want to provide the ability to
modify certain power supply settings while still
protecting the equipment from modifying values
that can lead to a system level fault. The equipment
manufacturer would use the User Store to achieve
this goal.
Please refer to Application Note AN33 for details on
how to set specific security measures via the
I2C/SMBus interface.
Page 38 of 42
ZL2004
7. Package Dimensions
Notes:
1.
Dim ensions a nd tolera nces conf orm to ASME
Y1 4 . 5 M – 1 9 9 4 .
2.
All dim ensions a re in m illim eters, θ is in degrees.
3.
4.
N is the tota l num ber of term ina ls.
Dim ension b a pplies to m eta liz ed term ina l a nd
is m ea sured between 0 . 1 5 a nd 0 . 3 3 m m f rom
term ina l tip. If the term ina l ha s the optiona l
ra dius on the other end of the term ina l, the
dim ension b should not be m ea sured in tha t
ra dius a rea .
ND a nd NE ref er to the num ber of term ina ls
on ea ch D a nd E side respectively.
Ma x pa ck a ge wa rpa ge is 0 . 0 5 m m .
Ma xim um a llowa ble burrs is 0 . 0 7 6 m m in a ll
directions.
Pin # 1 ID on top will be la ser m a rk ed.
Bila tera l copla na rity z one a pplies to the exposed
hea t sink slug a s well a s the term ina ls.
This dra wing conf orm s to JEDEC registered outline
MO- 2 2 0 .
5.
6.
7.
8.
9.
10.
FN6846 Rev. 3.00
February 15, 2011
S
YM
N
DIMENSIONS
BO
L
A
A1
A3
MIN.
NOM.
MAX.
k
D
E
e
N
ND
0.8 5
0.9 0
0.0 0
0.0 1
0.0 5
0 . 2 0 REF
0
12
0 . 2 0 MIN
5 . 0 BSC
5 . 0 BSC
0 . 5 0 BSC
32
8
NE
L
b
D2
E2
8
0.4 0
0.2 3
3.5 0
3.5 0
θ
0.3 0
0.1 8
3.3 5
3.3 5
O
T
E
2
3
5
5
0.5 0
0.3 0
3.7 5
3.7 5
4
Page 39 of 42
ZL2004
8. Ordering Information
ZL2004ALNNT
Shipping Option
T = Tape & Reel 100 pcs
T1 = Tape & Reel 1000 pcs
Contact factory for other options
Product Designator
Lead Finish
N = Lead-free NiPdAu
Firmware Revision
Alpha character
Ambient Temperature Range
L = - 40 to +85°C
Package Designator
A = QFN package
ZL2004ALNFT
Product Designator
Shipping Option
T = Tape & Reel 100 pcs
T1 = Tape & Reel 1000 pcs
Contact factory for other options
Lead Finish
F = (Lead-free Matte Tin)
Firmware Revision
Alpha character
Ambient Temperature Range
L = - 40 to +85°C
Package Designator
A = QFN package
9. Related Tools and Documentation
The following application support documents and tools are available to help simplify your design.
Item
Description
ZL2004EVK1
Evaluation Board – 40A single phase
AN33
Application Note: Digital-DC PMBus Command Set
AN34
Application Note: Digital-DC Current Sharing
AN35
Application Note: Digital-DC Control Loop Compensation
FN6846 Rev. 3.00
February 15, 2011
Page 40 of 42
ZL2004
10. Revision History
Rev. #
Description
Date
1.0
Data sheet initial release
March 2008
1.1
Removed DDC Address references from Section 6.11
April 2008
1.2
Updated Ordering Information
Improved readability in current sharing description
May 2008
1.3
Added comment that a device set up for tracking must have both Alternate Ramp
Control and Precise Ramp-Up Delay disabled on Page 32.
Clarified DDC pull-up voltage requirement on Page 35.
June 2008
1.4
Corrected frequency values in Table 14.
Corrected Figure 14.
Updated Adaptive Frequency Control description on Page 28.
Removed Bootstrap Capacitor Selection section.
Added Driver Selection section.
August 2008
Assigned file number FN6846 to datasheet as this will be the first release with an
Intersil file number. Replaced header and footer with Intersil header and footer.
FN6846.0
Updated disclaimer information to read “Intersil and it’s subsidiaries including
Zilker Labs, Inc.” No changes to datasheet content
FN6846.1
February 2009
Page 4, Table 3, 3rd entry, "VR reference output voltage": change Max value from
5.5 to 5.7.
April 2010
Added the following statement to disclaimer on page 42: “This product is subject to
a license from Power One, Inc. related to digital power technology as set forth in
FN6846.2 U.S. Patent No. 7,000,125 and other related patents owned by Power One, Inc. These
license rights do not extend to stand-alone POL regulators unless a royalty is paid to
Power One, Inc.”
Page 4, Table 3, added note "Compliance to datasheet limits is assured by one or
FN6846.3 more methods: production test, characterization and/or design."
Page 40, added ALNF FGs spider chart to Ordering Information
FN6846 Rev. 3.00
February 15, 2011
December 2010
January 2011
Page 41 of 42
ZL2004
© Copyright Intersil Americas LLC 2009-2011. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at http://www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that
such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that
datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by
Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
This product is subject to a license from Power One, Inc. related to digital power technology as set forth in U.S. Patent No. 7,000,125 and other related patents
owned by Power One, Inc. These license rights do not extend to stand-alone POL regulators unless a royalty is paid to Power One, Inc.
For information regarding Intersil Corporation and its products, see http://www.intersil.com
FN6846 Rev. 3.00
February 15, 2011
Page 42 of 42
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