ZL2102ALAFTK

DATASHEET ZL2102 FN8440 Rev 2.00 November 20, 2014 6A Digital Integrated Synchronous Step-Down DC/DC Regulator with Auto Compensation The ZL2102 is an integrated digital power regulator with auto compensation and power management functions in a small package, resulting in a flexible and integrated solution, which can be configured using the PowerNavigator™ graphical user interface. This synchronous buck converter operates from a 4.5V to 14V input supply and provides from 0.54V to 5.5V output voltage at up to 6A. Features The ZL2102 can be configured for most applications using only hardware pin straps to adjust switching frequency, output voltage, UVLO, soft-start ramp/delay settings, sequencing options, and SMBus address. For more advanced configurations, the ZL2102 supports over 70 PMBus commands. Output voltage/current is factory calibrated. • Up to 90% efficiency Internal synchronous power MOSFETs enable the ZL2102 to deliver continuous loads up to 6A with high efficiency. An internal Schottky bootstrap diode reduces discrete component count. The ZL2102 also supports phase spreading to reduce system input capacitance. • Small footprint QFN package (6mmx6mm) • Integrated MOSFET switches • 6A continuous output current • Adjustable 0.54V to 5.5V output range • 4.5V to 14V input range The ZL2102 uses the SMBus™ with PMBus™ protocol for communication with a host controller and the Intersil's proprietary Digital-DC™ bus for interoperability between other Intersil devices. • Auto compensation for fast transient response • SMBus compliant serial interface • Snapshot™ parametric capture • Internal nonvolatile memory Applications • Servers/storage equipment • Telecom/datacom equipment • Power supplies (memory, DSP, ASIC, FPGA) Related Literature • AN2010 "Thermal and Layout Guidelines for Digital-DC™ Products" • AN2035 "Compensation Using CompZL™" • TB389 "PCB Land Pattern and Surface Mount Guidelines for QFN Packages" DDC Bus INTERFACE SMBus DDC V2P5 10µF SCL VRA 4.7µF VR 4.7µF SDA SALRT PG HARDWARE CONTROL VDDS SYNC VSET VIN 12V VDDP CB 0.1µF MGN EN HARDWARE CONFIG ZL2102 BST CIN 100µF LOUT 2.2µH VOUT 3.3V 6A SW VSEN SA PGND FC SGND CFG DGND SS ePAD COUT 200µF FIGURE 1. TYPICAL APPLICATION DIAGRAM FN8440 Rev 2.00 November 20, 2014 Page 1 of 58 ZL2102 Table of Contents Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Digital-DC Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power Conversion Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power Management Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Functional Description and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 SMBus Device Address Selection (SA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Output Voltage and VOUT_MAX Selection (VSET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Automatic Loop Compensation (FC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Synchronization and Sequencing Configuration Settings (CFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Switching Frequency Setting (SYNC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Soft-Start and UVLO Settings (SS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Start-up Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power-Good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Power Management Function Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Overvoltage Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Prebias Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Margining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital-DC Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Phase Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fault Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitoring via SMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nonvolatile Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Snapshot™ Parametric Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Train Component Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Goal Trade-offs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inductor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 14 14 14 15 15 15 15 15 16 16 16 16 16 17 17 17 17 18 PCB Layout Recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 PMBus Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 PMBus Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 PMBus Command Detail. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 FN8440 Rev 2.00 November 20, 2014 Page 2 of 58 ZL2102 FIGURE 2. BLOCK DIAGRAM Pin Configuration 28 VDDP 29 VDDP 30 VDDS 31 VR 32 VRA 33 V2P5 34 DDC 35 MGN 36 EN ZL2102 (36 LD 6x6 QFN) TOP VIEW PG 1 27 VDDP DGND 2 26 BST SYNC 3 25 SW VSET 4 24 SW EXPOSED PADDLE SA 5 23 SW CONNECT TO SGND SCL 6 22 SW SDA 7 21 SW SALRT 8 20 SW FN8440 Rev 2.00 November 20, 2014 PGND 18 PGND 17 PGND 16 PGND 15 SGND 14 VSEN 13 DNC 12 SS 11 19 PGND CFG 10 FC 9 Page 3 of 58 ZL2102 Pin Description PIN # PIN NAME TYPE DESCRIPTION 1 PG Output Power-good indicator output pin. This pin transitions high after the output voltage stabilizes within the regulation band. Selectable open-drain or push-pull output. Default is open drain. 2 DGND Ground Digital ground. This is the common return for digital signals. Connect to low impedance ground plane. 3 SYNC Multimode Clock synchronization I/O pin. Used to set switching frequency of internal clock or for synchronization to an external clock, depending on the setting of the CFG pin. Configured during start-up by pin strap. 4 VSET Multimode Output voltage select pin. Used to set VOUT set-point and VOUT max. Configured during start-up by pin strap. 5 SA 6 SCL I/O Serial clock pin for SMBus communication. Connect to external host interface. A pull-up resistor is required for operation. 7 SDA I/O Serial data pin for SMBus communication. Connect to external host interface. A pull-up resistor is required for operation. 8 SALRT Output 9 FC Multimode Auto compensation configuration pin. Used to set up auto compensation configuration. Configured during start-up by pin strap. 10 CFG Multimode Configuration pin. Used to configure the SYNC pin and sequencing options. Configured during start-up by pin strap. 11 SS Multimode Soft-start pin. Sets the ramp delay/ramp time and UVLO. Configured during start-up by pin strap. 12 DNC 13 VSEN Multimode Serial address select pin. Used to assign a unique SMBus address to the device. Configured during start-up by pin strap. Serial alert output pin for SMBus communication. Connect to external host interface if desired. No Connect Do not connect to pin. Leave floating. Input Output voltage positive feedback sense pin. 14 SGND Ground Common return for analog signals. Connect to low impedance ground plane at one point directly at PGND pins. 15, 16, 17, 18, 19 PGND Ground Power ground. Common return for internal switching MOSFETs and external CIN/COUT. Connect to low impedance ground plane. 20, 21, 22, 23, 24, 25 SW Output Output switch node to the inductor. 26 BST Input Boosted floating driver supply pin. The bootstrap capacitor connects from the switch node to this pin. 27, 28, 29 VDDP Power Supply voltage for internal switching MOSFETs. 30 VDDS Power Supply voltage for the IC. 31 VR Power Regulated bias from internal 7V low-dropout regulator. Decouple with a 4.7μF capacitor to GND. Not for use with external circuits. 32 VRA Power Regulated bias from internal 5V low-dropout regulator for internal analog circuitry. Decouple with a 4.7μF capacitor to GND. Not for use with external circuits. 33 V2P5 Power Regulated bias from internal 2.5V low-dropout regulator for internal digital circuitry. Decouple with a 10µF capacitor to GND. Connect the device's multimode pins to this supply pin for logic HIGH pin strap settings. 34 DDC I/O Digital-DC Bus pin. Allows interoperability between other Intersil devices. A pull-up resistor is required for operation. 35 MGN Input Margin setting pin, used to enable margining of the output voltage. Logic HIGH sets the device to margin high, logic LOW sets the device to margin low, and leaving the pin floating sets the device to nominal voltage output. Enable pin, used to enable the output. Default is active high. 36 EN Input ePad SGND Ground Exposed thermal pad. Common return for analog signals. Connect to low impedance ground plane. Ordering Information PART NUMBER (Notes 1, 2, 3 ZL2102ALAFTK PART MARKING 2102 TEMP RANGE (°C) -40 to +85 PACKAGE Tape & Reel (Pb-free) 36 Ld Exposed Pad 6x6 QFN PKG. DWG. # L36.6x6A NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ZL2102. For more information on MSL, please see tech brief TB363. FN8440 Rev 2.00 November 20, 2014 Page 4 of 58 ZL2102 Absolute Maximum Ratings Thermal Information DC Supply Voltage for VDDP, VDDS Pins . . . . . . . . . . . . . . . . . . -0.3V to 17V High-Side Supply Voltage for BST Pin. . . . . . . . . . . . . . . . . . . . -0.3V to 25V High-Side Boost Voltage for BST, SW Pins. . . . . . . . . . . . . . . . . . -0.3V to 8V Internal MOSFET Reference for VR Pin . . . . . . . . . . . . . . . . . . -0.3V to 8.5V Internal Analog Reference for VRA Pin . . . . . . . . . . . . . . . . . . -0.3V to 6.5V Internal 2.5V Reference for V2P5 Pin . . . . . . . . . . . . . . . . . . . . . -0.3V to 3V Logic I/O Voltage for EN, CFG, DDC, FC, MGN, PG, SDA, SCL, SA, SALRT, SS, SYNC, VSET, VSEN Pins . . . . . . . . . . . . . . . . . . -0.3V to 6.5V Ground Differential for DGND - SGND, PGND - SGND Pins . . . . . . . . ±0.3V MOSFET Drive Reference Current for VR Pin Internal Bias Usage . . . 20mA Switch Node Current for SW Pin Peak (Sink Or Source) . . . . . . . . . . . . 10A ESD Rating Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 2kV Charged Device Model (Tested per JESD22-C101D) . . . . . . . . . . . . 750V Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . . 200V Latch-up (Tested per JESD78C; Class 2, Level A) . . . . . . . . . . . . . . . 100mA Thermal Resistance (Typical) JA (°C/W) JC (°C/W) 36 Ld QFN Package (Notes 4, 5) . . . . . . . . 28 1.7 Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C Dissipation Limits (Note 6) TA = +25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5W TA = +55°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5W TA = +85°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4W Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493 Recommended Operating Conditions Input Supply Voltage Range, VDDP, VDDS (see Figure 10 on page 10) VDDS tied to VR, VRA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V VDDS tied to VR, VRA Floating . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V to 7.5V VR, VRA Floating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7.5V to 14V Output Voltage Range, VOUT (Note 7) . . . . . . . . . . . . . . . . . . . 0.54V to 5.5V Operating Junction Temperature Range, TJ. . . . . . . . . . . .-40°C to +125°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. JA is measured in free air with the device mounted on a multi-layer FR4 test board and the exposed metal pad soldered to a low impedance ground plane using multiple vias. 5. For JC, the "case temp" location is the center of the exposed metal pad on the package underside. 6. Thermal impedance is dependent upon PCB layout. 7. Includes margin limits. Electrical Specifications VDDP = VDDS = 12V, TA = -40°C to +85°C unless otherwise noted (Note 9). Typical values are at TA = +25°C. Boldface limits apply across the operating temperature range, -40°C to +85°C. MIN (Note 8) TYP MAX (Note 8) UNIT fSW = 200kHz, no load – 15 25 mA fSW = 1MHz, no load – 15 30 mA IDD Shutdown Current EN = 0 V, no SMBus activity, low power standby mode – 0.6 1 mA VR Reference Output Voltage VDD > 8V, IVR < 10mA 6.5 7.0 7.5 V VRA Reference Output Voltage VDD > 5.5V, IVRA < 20mA 4.5 5.1 5.5 V V2P5 Reference Output Voltage IV2P5 < 20mA 2.25 2.5 2.75 V IRMS, continuous – – 6 A Peak (Note 11) – – 9 A PARAMETER TEST CONDITIONS IC INPUT AND BIAS SUPPLY CHARACTERISTICS IDD Supply Current OUTPUT CHARACTERISTICS Output Current Output Voltage Adjustment Range (Note 10) VIN > VOUT 0.6 – 5.0 V Output Voltage Set-point Accuracy Across line, load, temperature variation -1 – 1 % Output Voltage Set-point Resolution Set using PMBus command – ±2 – mV VSEN Input Bias Current VSEN = 5.5V – 110 200 µA FN8440 Rev 2.00 November 20, 2014 Page 5 of 58 ZL2102 Electrical Specifications VDDP = VDDS = 12V, TA = -40°C to +85°C unless otherwise noted (Note 9). Typical values are at TA = +25°C. Boldface limits apply across the operating temperature range, -40°C to +85°C. (Continued) PARAMETER TEST CONDITIONS MIN (Note 8) TYP MAX (Note 8) UNIT -250 – 250 nA – – 0.8 V – 1.4 – V 2.0 – – V LOGIC INPUT/OUTPUT CHARACTERISTICS Logic Input Leakage Current Logic I/O - multimode pins Logic Input Low, VIL Logic input Open (N/C) Multimode logic pins Logic Input High, VIH Logic Output Low, VOL IOL ≤ 4mA – – 0.4 V Logic Output High, VOH IOH ≥ -2mA 2.25 – – V 200 - 1000 kHz Switching Frequency Set-Point Accuracy -5 - 5 % PWM Duty Cycle 0 - 95 % 150 - - ns OSCILLATOR AND SWITCHING CHARACTERISTICS Switching Frequency Range Minimum SYNC Pulse Width Input Clock Frequency Drift Tolerance External clock source -13 - 13 % rDS(ON) of High-Side N-channel FETs ISW = 6A, VGS = 6.5V - 60 85 mΩ rDS(ON) of Low-Side N-channel FETs ISW = 6A, VGS = 12V - 43 65 mΩ SMBus Clock Rate - 100 - kHz Wait Time Between Consecutive Commands 2 - - ms SMBUS CHARACTERISTICS POWER MANAGEMENT SOFT-START RAMP CHARACTERISTICS Soft-Start Ramp Delay Range Set using PMBus command 5 - 30000 ms Soft-Start Ramp Delay Accuracy Turn-on, turn off delay -1 ±1 +5 ms Soft-Start Ramp Duration Range Set using PMBus command 5 - 200 ms Soft-Start Ramp Duration Accuracy Turn-on, turn off delay - ±1 - ms Power-Good VOUT Threshold Factory default - 90 - % VOUT Power-Good VOUT Hysteresis Factory default - 5 - % Power-Good Delay Applies to Turn-On Only (Low-to-High transition) Factory default - 1 - ms Set using PMBus command 1 30000 ms POWER-GOOD MONITORING AND FAULT MANAGEMENT INPUT VOLTAGE MONITOR AND FAULT DETECTION VIN Monitor Accuracy VIN UVLO Threshold Range Set using PMBus command UVLO Hysteresis Factory default FN8440 Rev 2.00 November 20, 2014 -150 - 150 mV 4.5 - 16 V - 3 - % Page 6 of 58 ZL2102 Electrical Specifications VDDP = VDDS = 12V, TA = -40°C to +85°C unless otherwise noted (Note 9). Typical values are at TA = +25°C. Boldface limits apply across the operating temperature range, -40°C to +85°C. (Continued) MIN (Note 8) TYP MAX (Note 8) UNIT - 5 - % VOUT - 30 - µs IOUT Monitor Accuracy - ±10 - % IOUT Threshold Accuracy - ±3 ±5 % FS IOUT Fault Response Delay - 15 - µs -55 - 125 °C PARAMETER TEST CONDITIONS OUTPUT VOLTAGE MONITOR AND FAULT DETECTION VOUT Undervoltage Hysteresis Factory default VOUT UV/OV Fault Response Delay OUTPUT CURRENT SENSE MONITOR AND FAULT DETECTION TEMPERATURE SENSE Internal Temperature Range Internal Temperature Accuracy Tested at +100°C -5 - 5 °C Thermal protection Hysteresis Factory default – 15 – °C NOTES: 8. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 9. Refer to Safe Operating Area in Figure 8 and thermal design guidelines in AN2010. 10. Does not include margin limits. 11. Switch node current should not exceed IRMS of 6A. Typical Performance Curves 1.4 1.4 1.3 1.3 NORMALIZED rDS(ON) NORMALIZED rDS(ON) For some applications, ZL2102 operating conditions (input voltage, output voltage, switching frequency, temperature) may require derating to remain within the Safe Operating Area (SOA). VIN = VDDP = VDDS, TJ = +125°C 1.2 1.1 1.0 0.9 0.8 0 25 50 75 100 TJ (°C) FIGURE 3. LOW-SIDE rDS(ON) vs TJ NORMALIZED FOR TJ = +25°C (VDDS = 12V, IDRAIN = 0.3A) FN8440 Rev 2.00 November 20, 2014 1.2 1.1 1.0 0.9 0.8 0 25 50 TJ (°C) 75 100 FIGURE 4. HIGH-SIDE rDS(ON) vs TJ NORMALIZED FOR TJ = +25°C (VDDS = 12V, BST – SW = 6.5V, IDRAIN = 0.3A) Page 7 of 58 ZL2102 Typical Performance Curves 70 6 65 5 60 VIN = 7.5V VIN = 6V 4 TJ = +110°C VOUT (V) rDS(ON) (mΩ) For some applications, ZL2102 operating conditions (input voltage, output voltage, switching frequency, temperature) may require derating to remain within the Safe Operating Area (SOA). VIN = VDDP = VDDS, TJ = +125°C (Continued) 55 TJ = +80°C 50 3 VIN = 8.6V TO 14V 2 TJ = +50°C 45 40 1 TJ = +25°C 6 7 8 9 10 11 12 0 13 0.2 0.3 0.4 VDDS (V) 0.5 0.6 0.7 0.8 0.9 1 1.0 fSW (MHz) FIGURE 6. SAFE OPERATING AREA, TJ +125°C FIGURE 5. LOW-SIDE rDS(ON) vs V DDS WITH TJ 0.95 VOUT MAY NOT EXCEED 5.5V AT ANY TIME 0.90 VOUT/VIN (V) 0.85 0.80 0.75 0.70 0.65 0.60 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 fSW (MHz) FIGURE 7. MAXIMUM CONVERSION RATIO, TJ +125°C Digital-DC Architecture Overview The ZL2102 is an innovative mixed-signal power conversion and power management IC based on Intersil patented Digital-DC technology that provides an integrated, high performance stepdown regulator for point of load applications. The ZL2102 integrates all necessary PWM control circuitry as well as low rDS(ON) synchronous power MOSFETs to provide an extremely small solution for supplying load currents up to 6A. Once enabled, the ZL2102 is immediately ready to regulate power and perform power management tasks with no programming required. Advanced configuration options and realtime configuration changes are available via the SMBus interface if desired and continuous monitoring of multiple operating parameters is possible with minimal interaction from a host controller. Integrated sub regulation circuitry enables single supply operation from any external supply between 4.5V and 14V with no additional bias supplies needed. Its unique PWM loop utilizes an ideal mix of analog and digital blocks to enable precise control of the entire power conversion process with no software required, resulting in a very flexible device that is also very easy to use. An extensive set of power management functions are fully integrated and can be configured using simple pin connections. The user configuration can be saved in an internal nonvolatile memory (NVM). Additionally, all functions can be configured and monitored via the SMBus hardware interface using standard PMBus commands, allowing ultimate flexibility. The ZL2102 can be configured by simply connecting its pins according to the tables provided in the following sections. Additionally, a comprehensive set of application notes are available to help simplify the design process. An evaluation board is also available to help the user become familiar with the device. This board can be evaluated as a standalone platform using pin configuration settings. A Windows™-based GUI is also provided to enable full configuration and monitoring capability via the SMBus interface using a computer and the included USB cable. FN8440 Rev 2.00 November 20, 2014 Page 8 of 58 ZL2102 Power Conversion Overview The ZL2102 operates as a voltage-mode, synchronous buck converter with a selectable constant frequency pulse width modulator (PWM) control scheme. The ZL2102 integrates dual low rDS(ON) synchronous MOSFETs and a high-side driver to minimize the circuit footprint. Figure 8 illustrates the basic synchronous buck converter topology showing the primary power train components. This converter is also called a step-down converter, as the output voltage must always be lower than the input voltage. VIN CIN DB LDO QH CB L1 VOUT PWM COUT QL The maximum conversion ratio is shown in Figure 7. Typically, buck converters specify a maximum duty cycle that effectively limits the maximum output voltage that can be realized for a given input voltage and switching frequency. This duty cycle limit ensures that the low-side MOSFET is allowed to turn on for a minimum amount of time during each switching cycle, which enables the bootstrap capacitor to be charged up and provide adequate gate drive voltage for the high-side MOSFET. The block diagram for the ZL2102 is illustrated in Figure 2. In this circuit, the target output voltage is regulated by connecting the VSEN pin directly to the output regulation point. The VSEN signal is then compared to an internal reference voltage that had been set to the desired output voltage level by the user. The error signal derived from this comparison is converted to a digital value with an analog-to-digital (A/D) converter. The digital signal is also applied to an adjustable digital compensation filter and the compensated signal is used to derive the appropriate PWM duty cycle for driving the internal MOSFETs in a way that produces the desired output. Power Management Overview ZL2102 FIGURE 8. STEP DOWN CONVERTER The ZL2102 integrates two N-channel power MOSFETs; QH is the top control MOSFET and QL is the bottom synchronous MOSFET. The amount of time that QH is on as a fraction of the total switching period is known as duty cycle D, which is described by Equation 1: V OUT D  ---------------V IN (EQ. 1) During time D, QH is on and VIN to VOUT is applied across the inductor. The output current ramps up as shown in Figure 9. VIN - VOUT ILPK The ZL2102 incorporates a wide range of configurable power management features that are simple to implement with no external components. Additionally, the ZL2102 includes circuit protection features that continuously safeguard the device and load from damage due to unexpected system faults. The ZL2102 can continuously monitor input voltage, output voltage/current, and internal temperature. A power-good output signal is also included to enable power-on reset functionality for an external processor. All power management functions can be configured using either pin configuration techniques described in this document or via the SMBus interface using PMBus commands. Monitoring parameters can also be preconfigured to provide alerts for specific conditions. “PMBus Command Summary” on page 19 contains a listing of all the PMBus commands supported by the ZL2102 and a detailed description of the use of each of these commands. IO 0 CURRENT (A) VOLTAGE (V) Functional Description and Configuration ILV -VOUT D 1-D TIME FIGURE 9. OUTPUT CURRENT When QH turns off (time 1-D), the current flowing in the inductor must continue to flow from the ground up through QL, during which the current ramps down. Since the output capacitor COUT exhibits low impedance at the switching frequency, the AC component of the inductor current is filtered from the output voltage so the load sees nearly a DC voltage. FN8440 Rev 2.00 November 20, 2014 INTERNAL BIAS REGULATORS AND INPUT SUPPLY CONNECTIONS The ZL2102 employs three internal LDO regulators, allowing operation from a single input supply from 4.5V to 14V. The regulators are as follows: • VR is derived from VDDS and provides a 7V bias supply for the internal high-side MOSFET driver circuit. A 4.7µF capacitor is required for the VR pin. • VRA is derived from VDDS and provides a 5V bias supply for the internal analog circuitry. A 4.7µF capacitor is required for the VR pin. • V2P5 is derived from VRA and provides a 2.5V bias supply for the digital circuitry. A 10µF capacitor is required at the V2P5 pin. Page 9 of 58 ZL2102 Input voltage ranges and connections are shown in Figure 10. V IN V IN V IN VDDS VDDS VDDS VR VR VR VRA VRA VRA V IN = 4.5V TO 5.5V V IN = 5.5V TO 7.5V MULTIMODE PIN OPEN MULTIMODE PIN LOGIC LOW V IN = 7.5V TO 14V FIGURE 10. INPUT SUPPLY CONNECTIONS The internal bias regulators, VR and VRA, are not designed to be outputs for powering other circuitry. Do not attach external loads to any of these pins. Only the multimode pins may be connected to the V2P5 pin for logic HIGH settings. MULTIMODE PINS In order to simplify circuit design, the ZL2102 incorporates patented multimode pins that allow the user to easily configure many aspects of the device with no programming. Most power management features can be configured using these pins. The multimode pins can respond to four different connections as shown in Table 1. These pins are sampled once when power is applied or by issuing a PMBus Restore command. Pin Strap Settings: This is the simplest implementation method, as no external components are required. Using this method, each pin can take on one of three possible states: LOW, OPEN, or HIGH. These pins can be connected to the V25 pin for logic HIGH settings. Using a single pin, one of three settings can be selected. Resistor Settings: This method allows a greater range of adjustability when connecting a finite value resistor (in a specified range) between the multimode pin and SGND. Standard 1% resistor values are used, and only every fourth E96 resistor value is used so the device can reliably recognize the value of resistance connected to the pin while eliminating the error associated with the resistor accuracy. Up to 31 unique selections are available using a single resistor. TABLE 1. MULTIMODE PIN CONFIGURATION PIN TIED TO VALUE LOW (Logic LOW) 2.0 VDC Resistor to SGND Set by resistor value FN8440 Rev 2.00 November 20, 2014 LOGIC HIGH PIN STRAP SETTINGS RESISTOR SETTINGS FIGURE 11. PIN STRAP AND RESISTOR SETTING EXAMPLES SMBus: Most ZL2102 functions/parameters can be configured via the SMBus interface using standard PMBus commands. “PMBus Command Summary” on page 19 explains the use of the available PMBus commands in detail. CONFIGURABLE PINS Many operating parameters can be set using the multimode pin setup method: SMBus address (SA), output voltage (VSET), clock synchronization and sequencing options (CFG), switching frequency (SYNC), soft-start delay, soft-start ramp, input undervoltage lock-out (SS), and automatic loop compensation settings (FC). These pins are checked once during start-up only. Changes to the settings of these pins will not be read until the device's power supply has been cycled off and on. The device's SMBus address is the only parameter that must be set by the multimode pins. All others are configurable using PMBus commands. SMBus Device Address Selection (SA) The ZL2102 provides an SMBus digital interface that enables the user to configure all aspects of the device operation as well as monitor the input and output parameters. The ZL2102 is compatible with SMBus version 2.0 and includes an SALRT line to help mitigate bandwidth limitations related to continuous fault monitoring. When communicating with multiple devices using the SMBus interface, each device must have its own unique address so the host can distinguish between the devices. The device address can be set according to the pin strap options listed in Table 2. The SMBus address cannot be changed with a PMBus command. Page 10 of 58 ZL2102 TABLE 3. (Continued) TABLE 2. PIN STRAP OPTIONS RSA (kΩ) SMBus ADDRESS RSA (kΩ) SMBus ADDRESS RSET (kΩ) VOUT (V) RSET (kΩ) VOUT (V) 10 or LOW 20h 42.2 2Fh 26.1 1.2 121 2.9 11 or OPEN 21h 46.4 30h 28.7 1.25 133 3 12.1 or HIGH 22h 51.1 31h 31.6 1.3 HIGH 3.3 13.3 23h 56.2 32h 34.8 1.4 147 4 14.7 24h 61.9 33h 38.3 1.5 162 4.5 16.2 25h 68.1 34h 42.2 1.6 OPEN 5 17.8 26h 75 35h 46.4 1.7 19.6 27h 82.5 36h 21.5 28h 91 37h 23.7 29h 100 38h 26.1 2Ah 110 39h 28.7 2Bh 121 3Ah 31.6 2Ch 133 3Bh 34.8 2Dh 147 3Ch 38.3 2Eh 162 3Dh Output Voltage and VOUT_MAX Selection (VSET) The output voltage may be set to any voltage between 0.6V and 5.5V provided that the input voltage is higher than the desired output voltage by an amount sufficient to prevent the device from exceeding its maximum duty cycle specification. VOUT can be set to any of the pin strap options shown in Table 3. VOUT can also be set using the VOUT_COMMAND PMBus command. The maximum accepted value of VOUT is limited by VOUT_MAX. The default value of VOUT_MAX is 110% of the VSET pin strap setting, but it can also be set using the VOUT_MAX PMBus command. TABLE 3. RSET (kΩ) VOUT (V) RSET (kΩ) VOUT (V) 10 0.6 LOW 1.8 11 0.7 51.1 1.9 12.1 0.75 56.2 2 13.3 0.8 61.9 2.1 14.7 0.9 68.1 2.2 16.2 1 75 2.4 17.8 1.05 82.5 2.5 19.6 1.1 91 2.6 21.5 1.125 100 2.7 23.7 1.15 110 2.8 FN8440 Rev 2.00 November 20, 2014 In addition to the VOUT_COMMAND and VOUT_MAX settings, this pin strap setting is also used to set several other VOUT related settings including: • VOUT_UV_FAULT_LIMIT = 85% of VSET • POWER_GOOD_ON = 90% of VSET • VOUT_MARGIN_LOW = 95% of VSET • VOUT_MARGIN_HIGH = 105% of VSET • VOUT_OV_FAULT_LIMIT = 115% of VSET The above parameters are automatically adjusted by the VSET pin strap selection. If the value of VOUT_COMMAND is adjusted via PMBus, the values of these commands may also need to be adjusted to compensate for the VOUT change. The configured voltage relationships must follow: VOUT_UV_FAULT_LIMIT < POWER_GOOD_ON < VOUT_MARGIN_LOW < VOUT_COMMAND < VOUT_MARGIN_HIGH < VOUT_OV_FAULT_LIMIT. Automatic Loop Compensation (FC) The ZL2102 has an automatic loop compensation feature that measures the characteristics of the power train and calculates the proper PID tap coefficients. Auto compensation is configured using the FC pin as shown in Table 4. TABLE 4. RFC (kΩ) LOW PG ASSERT AUTO COMP GAIN (%) Auto Comp Disabled 10 After Auto Comp 11 After PG Delay 12.1 After Auto Comp 13.3 After PG Delay 14.7 After Auto Comp 16.2 After PG Delay 17.8 After Auto Comp 19.6 After PG Delay 21.5 After Auto Comp 23.7 After PG Delay 100 90 80 70 60 Page 11 of 58 ZL2102 TABLE 4. (Continued) TABLE 5. RFC (kΩ) PG ASSERT AUTO COMP GAIN (%) RCFG (kΩ) SYNC PIN CONFIGURATION OPEN After Auto Comp 50 LOW Input HIGH After PG Delay OPEN Auto detect 26.1 After Auto Comp HIGH Output 28.7 After PG Delay 14.7 Input 31.6 After Auto Comp 16.2 Auto detect 34.8 After PG Delay 17.8 Output 38.3 After Auto Comp 21.5 Input 42.2 After PG Delay 23.7 Auto detect 46.4 After Auto Comp 26.1 Output 51.1 After PG Delay 31.6 Input 34.8 Auto detect 38.3 Output 40% 30% 20% 10% When Auto Comp is enabled, it will run once each time the part is enabled. Auto Comp runs a series of tests on the output and calculates the optimal tap coefficients immediately after the VOUT ramp completes. The calculated tap coefficients are stored in the Auto Comp Store and may be read back through the PID_TAPS PMBus command. If auto compensation is disabled, the device will use the tap coefficients that are stored in the USER_STORE. SEQUENCING CONFIGURATION Sequencing Disabled. Device is FIRST in Nested Sequence. Device is LAST in Nested Sequence. Device is MIDDLE in Nested Sequence. Switching Frequency Setting (SYNC) The ZL2102's switching frequency can be set from 200kHz to 1000kHz using the SYNC pin strap options shown in Table 6. TABLE 6. If the PG Assert parameter is set to "Use PG Delay", the PG pin will be asserted according to the POWER_GOOD_DELAY command. When Auto Comp is enabled and the "Use PG Delay" option is selected, the user must ensure that the output perturbation from the Auto Comp test cycle is acceptable before PG is asserted. If PG Assert is set to "After Auto Comp", PG will be asserted immediately after the Auto Comp cycle completes (POWER_GOOD_DELAY will be ignored in this case). RSYNC (kΩ) FREQ (kHz) RSYNC (kΩ) FREQ (kHz) LOW 200 21.5 471 10 222 23.7 500 11 242 26.1 533 12.1 267 28.7 571 The Auto Comp Gain control scales the Auto Comp results to allow a trade-off between transient response and steady-state duty cycle jitter. A setting of 100% will provide the fastest transient response while a setting of 10% will produce the lowest jitter. For best results, VIN must be stable before Auto Comp begins as shown in Equation 2: 13.3 296 31.6 615 14.7 320 34.8 667 16.2 364 38.3 727 OPEN 400 42.2 800 17.8 421 46.4 889 19.6 445 HIGH 1000 V IN 100% -----------------------  in%   ----------------------------------------VIN NOM 256  V OUT 1 + ------------------------------VINNOM (EQ. 2) The auto compensation function can also be configured via the AUTO_COMP_CONFIG PMBus command and controlled using the AUTO_COMP_CONTROL PMBus command. Compensation values can be programmed manually by disabling Auto Comp and writing preferred values to the PID_TAPS PMBus command. Synchronization and Sequencing Configuration Settings (CFG) The ZL2102 supports several options of clock synchronization and output sequencing. The ZL2102's configuration settings can be set using the CFG pin strap options shown in Table 5. The operation of these functions is covered in their respective sections of this document. FN8440 Rev 2.00 November 20, 2014 The switching frequency can also be set to any value between 200kHz and 1MHz using the FREQUENCY_SWITCH PMBus command. The available frequencies below 1MHz are defined by fSW = 8MHz/N, where 8 ≤ N ≤ 40. If a value other than fSW = 8MHz/N is entered using the PMBus command, the device will select the switching frequency value using N as a whole number to achieve a value nearest to the entered value. For example, if 810kHz is entered, the device will select 800kHz (N = 10). Note: The switching frequency read back using the appropriate PMBus command may differ slightly from the programmed value. The difference is due to hardware quantization. The SYNC pin can also be configured to perform synchronization between devices. The CFG pin is used to configure the SYNC pin Page 12 of 58 ZL2102 as an input, an output, or auto-detect mode. The ZL2102 incorporates an internal phase-locked loop (PLL) to clock the internal circuitry. The PLL can be driven by an external clock source connected to the SYNC pin, or it can be configured to drive the internal clock out of the SYNC pin to other devices. TABLE 7. RSS (kΩ) TON/TOFF DELAY TIME (ms) 10 5 11 10 12.1 20 LOW or 13.3 5 14.7 10 16.2 20 17.8 5 19.6 10 21.5 20 23.7 5 26.1 10 HIGH or 28.7 20 31.6 5 34.8 10 38.3 20 42.2 5 46.4 10 Soft-Start and UVLO Settings (SS) 51.1 20 The ZL2102 supports variable turn-on/off delay times, turn-on/off ramp rates, and input undervoltage lockout (UVLO) functions. These features may be used as part of an overall in-rush current management strategy or to precisely control how fast a load is turned on. The ZL2102 provides several options for precisely and independently controlling both the delay and ramp time periods. 56.2 5 OPEN or 61.9 10 68.1 20 75 5 82.5 10 91 20 100 5 110 10 121 20 SYNC OUTPUT: When the SYNC pin is configured as an output, the device will run from its internal oscillator and will drive the selected switching frequency onto the SYNC pin so that other devices can be synchronized to it. SYNC INPUT: When the SYNC pin is configured as an input, the device will check for an external clock signal on the SYNC pin each time the output is enabled. The internal oscillator will then synchronize with the rising edge of the external clock. The incoming clock signal must be in the range of 200kHz to 1MHz and must be stable when the enable pin is asserted. The clock signal must have a minimum width of 150ns, and it must stay within 10% of its initial value. In the event of a loss of the external clock signal, will automatically switch to its internal oscillator and switch at a frequency close to the previous incoming frequency. The output voltage may show a transient overshoot/undershoot if this occurs. SYNC AUTO DETECT: When the SYNC pin is configured in auto-detect mode, the device will check for a clock signal on the SYNC pin each time EN is asserted. If there is a valid clock, the pin will run as a sync input. If no incoming clock signal is present, the device will switch at the selected internal clock rate. The soft-start delay period begins when the EN pin is asserted and ends when the delay time expires. The soft-start ramp timer enables a precisely controlled monotonic ramp to the nominal VOUT value that begins once the delay period has expired. This process is also followed for ramp down after the EN pin has been deasserted. The input undervoltage lockout (UVLO) prevents the ZL2102 from operating when the input falls below a preset threshold, indicating the input supply is out of its specified range. The ZL2102's TON/TOFF delay time, TON/TOFF ramp time, and UVLO functions can be configured using the SS pin strap options shown in Table 7. TON/TOFF RAMP TIME (ms) UVLO (V) 5 10 4.5 20 5 10 5.5 20 5 10 7.5 20 These functions can also be set independently using TON_DELAY, TON_RISE, TOFF_DELAY, and TOFF_FALL PMBus commands. The UVLO threshold can be adjusted using the VIN_UV_FAULT_LIMIT PMBus command. The ramp down function is disabled by default, but it can be enabled using the ON_OFF_CONFIG or OPERATION PMBus commands depending on the desired device enable method. Start-up Procedure The ZL2102 follows a specific internal start-up procedure after power is applied. Figure 12 describes the start-up sequence. FN8440 Rev 2.00 November 20, 2014 Page 13 of 58 ZL2102 Input Power Applied Pre-ramp Delay ~5ms Delay between enable signal and start of output ramp. Additional delay may be added with PMBus command Internal Memory Check ~35ms Device will ignore an enable signal or PMBus commands Device Ready FIGURE 12. START-UP SEQUENCE If the device is to be synchronized to an external clock source, the clock frequency must be stable prior to asserting the EN pin. The device requires approximately 35ms to check for specific values stored in its internal memory. If the user has stored values in memory, those values will be loaded. If Auto Comp is enabled, start-up time increases to ~55ms. Once this process is completed, the device is ready to accept commands via the serial interface and the device is ready to be enabled. Once enabled, the device requires approximately 5ms before its output voltage may be allowed to start its ramp-up process. If a soft-start delay period less than 5ms has been configured (using PMBus commands), the device will default to a 5ms delay period. If a delay period greater than 5ms is configured, the device will wait for the configured delay period prior to starting to ramp its output. After the delay period has expired, the output will begin to ramp towards its target voltage according to the preconfigured soft-start ramp time. Power-Good The ZL2102 provides a Power-Good (PG) signal that indicates the output voltage is within a specified tolerance of its target level and no fault condition exists. By default, the PG pin will assert if the output reaches 90% of the target voltage. The limit and drive configuration of the pin may be changed using the POWER_GOOD_ON and MFR_CONFIG PMBus commands. A PG delay period is defined as the time from when all conditions for asserting PG are met to when the PG pin is actually asserted. This feature is commonly used instead of using an external reset controller to control external digital logic. By default, the ZL2102 PG delay is set equal to 1ms. The PG delay can be adjusted using the POWER_GOOD_DELAY PMBus command. Power Management Function Description Input Undervoltage Lockout The input undervoltage lockout feature (UVLO) prevents the ZL2102 from operating when the input falls below a preset threshold, indicating the input supply is out of its specified range. The UVLO threshold can be set to 4.5V, 5.5V, or 7.5V using the SS pin. The UVLO voltage can also be adjusted using the VIN_UV_FAULT_LIMIT PMBus command. The default response from a UVLO fault is an immediate shutdown of the device during the fault and an automatic restart when the fault condition has cleared. The UVLO fault response can be configured using the VIN_UV_FAULT_RESPONSE PMBus command. Output Overvoltage Protection The ZL2102 offers an internal output overvoltage protection circuit that can be used to protect sensitive load circuitry from being subjected to a voltage higher than its prescribed limits. A hardware comparator is used to compare the actual output voltage (seen at the VSEN pin) to a threshold set above the target output voltage. The default setting is 115% of the pin strap setting for VOUT, but this value can be adjusted using the VOUT_OV_FAULT_LIMIT PMBus command. If the VSEN voltage exceeds this threshold, the PG pin will deassert and the device response can be set using the VOUT_OV_FAULT_RESPONSE PMBus command. The default response is an immediate shutdown of the device during the fault and an automatic restart when the fault has cleared. For continuous overvoltage protection when operating from an external clock, the only allowed response is an immediate shutdown with no automatic restart. Output Prebias Protection An output prebias condition exists when an externally applied voltage is present on a power supply's output before the power supply's control IC is enabled. Certain applications require that the converter not be allowed to sink current during start-up if a prebias condition exists at the output. The ZL2102 provides prebias protection by sampling the output voltage prior to initiating an output ramp. If a prebias voltage exists after the preconfigured delay period has expired, the ramp start voltage will be set to match the existing prebias voltage and the output will be enabled. The output voltage will then ramp to the final regulation value at the ramp rate set by the SS pin strap setting or the TON_RISE PMBus command. The actual time the output will take to ramp up from the prebias voltage to the target voltage will vary depending on the prebias voltage, but the total time from enable to when the output reaches its target value will match the preconfigured delay and ramp times. When ramping down from a prebias higher than the target voltage, the device will wait until after SS ramp time is complete and will then ramp down to the target voltage at an approximate rate of 0.1V/ms (see Figure 13). FN8440 Rev 2.00 November 20, 2014 Page 14 of 58 ZL2102 an immediate shutdown of the device during the fault and an automatic restart when the fault has cleared, but the response can be adjusted using the OT_FAULT_RESPONSE PMBus command. V OUT TARGET VOLTAGE PREBIAS VOLTAGE SS DELAY SS RAMP TIME If the device is configured to restart, it will wait 250ms and will then check the device temperature. Once the temperature has dropped below the over-temperature warning limit, the device will attempt to restart. The default value of the over-temperature warning limit is +110°C, providing +15°C of hysteresis, but the value can be adjusted using the OT_WARN_LIMIT PMBus command. Voltage Margining VPREBIAS < VTARGET The ZL2102 provides a simple method to vary its output higher or lower than its nominal voltage setting in order to determine whether the load device is capable of operating over its specified supply voltage range. The voltage margin range can be set by driving the MGN pin or using the OPERATION PMBus command. The MGN pin is a tri-level input that is continuously monitored and can be driven directly by a processor I/O pin or other logic-level output. V OUT PREBIAS VOLTAGE TARGET VOLTAGE SS DELAY SS RAMP TIME VPREBIAS > VTARGET FIGURE 13. OUTPUT RESPONSES TO PREBIAS VOLTAGES If the prebias voltage is higher than the output overvoltage limit set in VOUT_OV_FAULT_LIMIT, the device will declare an overvoltage fault condition and it will respond based on the output overvoltage response method that has been selected in the VOUT_OV_FAULT_RESPONSE PMBus command. Output Overcurrent Protection The ZL2102 incorporates a patented "lossless" current sensing method across the internal low-side MOSFET that is independent of rDS(ON) variations, including temperature. This current limiting mechanism is used to protect the power supply from damage and prevent excessive current from being drawn from the input supply in the event that the output is overloaded or shorted to ground. Current limiting is accomplished by sensing the current through the circuit during a portion of the duty cycle. The current limit threshold is set to 7.2A by default, but it can be adjusted using the IOUT_AVG_OC_FAULT_LIMIT PMBus command. The default response of an overcurrent fault is an immediate shutdown of the device during the fault and an automatic restart when the fault has cleared, but it can be adjusted using the MFR_IOUT_OC_RESPONSE PMBus command. Thermal Overload Protection The ZL2102 includes an on-chip thermal sensor that continuously measures the internal temperature of the die and shuts down the device when the temperature exceeds the preset limit. The default temperature limit is set to +125°C in the factory, but it can be adjusted using the OT_FAULT_LIMIT PMBus command. The default response to an over-temperature fault is FN8440 Rev 2.00 November 20, 2014 The ZL2102's output will be forced higher than its nominal set point when the MGN command is set HIGH, and the output will be forced lower than its nominal set point when the MGN command is set LOW. The default margin settings are ±5% of the pin strapped value of VOUT, but the margin settings can be adjusted using the VOUT_MARGIN_HIGH and VOUT_MARGIN_LOW PMBus commands. The default transition rate between the nominal output voltage and either margin limit is 0.5V/ms, but it can be adjusted using the VOUT_TRANSITION_RATE PMBus command. Digital-DC Bus The Digital-DC Communications (DDC) bus is used to communicate between Intersil Digital-DC devices. This dedicated bus provides the communication channel between devices for features such as sequencing and fault spreading. The DDC pin on all Digital-DC devices in an application should be connected together. A pull-up resistor is required on the DDC bus in order to guarantee the rise time as follows: Rise time = RPU * CLOAD ≈ 1µs, where RPU is the DDC bus pull-up resistance and CLOAD is the bus loading. The pull-up resistor may be tied to VR or to an external 3.3V or 5V supply as long as this voltage is present prior to or during device power-up. As a rule of thumb, each device connected to the DDC bus presents approximately 10pF of capacitive loading, and each inch of FR4 PCB trace introduces approximately 2pF. The ideal design will use a central pull-up resistor that is well-matched to the total load capacitance. In power module applications, the user should consider whether to place the pull-up resistor on the module or on the PCB of the end application. The minimum pull-up resistance should be limited to a value that enables any device to assert the bus to a voltage that will ensure a logic 0 (typically 0.8V at the device monitoring point) given the pull-up voltage (5V if tied to VR5) and the pull-down current capability of the ZL2102 (nominally 4mA). Phase Spreading When multiple power converters share a common DC input supply, it is desirable to adjust the clock phase offset of each device, such that not all devices start to switch simultaneously. Page 15 of 58 ZL2102 Setting each converter to start its switching cycle at a different point in time can dramatically reduce input capacitance requirements and efficiency losses. Since the peak current drawn from the input supply is effectively spread out over a period of time, the peak current drawn at any given moment is reduced and the power losses proportional to the IRMS2 are reduced dramatically. In order to enable phase spreading, all converters must be synchronized to the same switching clock. This can be accomplished by setting the CFG pin strap or by using the INTERLEAVE PMBus command. Selecting the phase offset for the device is accomplished by selecting a device address according to Equation 3: Phase offset = device address  45 (EQ. 3) For example: • A device address of 0x20 would configure no phase offset • A device address of 0x21 would configure 45° of phase offset • A device address of 0x22 would configure 90° of phase offset The phase offset of each device may also be set to any value between 0° and 360° in 22.5° increments via the INTERLEAVE PMBus command. Output Sequencing Intersil devices may be configured to power-up as a group in a predetermined sequence. This feature is especially useful when powering advanced processors, FPGA’s and ASIC’s that require one supply to reach its operating voltage prior to another supply reaching its operating voltage in order to avoid latch-up from occurring. Multidevice sequencing can be achieved by configuring each device through the SEQUENCE PMBus command or by using Intersil patented autonomous sequencing mode. Autonomous sequencing mode configures sequencing by using events transmitted between devices over the DDC bus. The sequencing order is determined using each device's SMBus address. Using autonomous sequencing mode (configured using the CFG pin), the devices must be assigned sequential SMBus addresses with no missing addresses in the chain, the enable pins must be tied together, and the sync pins of all devices must be tied together. The first device in the sequence will become the clock master, and the other devices will sync to this clock. This mode will also constrain each device to have a phase offset according to its SMBus address as described in the “Phase Spreading” on page 15. The enable (EN) line is driven high to initiate a sequenced turn-on of the group. Enable is driven low to initiate a sequenced turnoff of the group. During enable, the sequencing group will enable in order starting with the device with the lowest SMBus address and will continue through to turn on each device in the address chain until all devices connected have been turned on. During disable, the device with the highest SMBus address will turn off first followed in reverse order by the other devices in the group. The PG threshold is used to determine when the following device is enabled. FN8440 Rev 2.00 November 20, 2014 Fault Spreading Digital-DC devices can be configured to broadcast a fault event over the DDC bus to the other devices in the group. When a fault occurs and the device is configured to shut down on a fault, the device will shut down and broadcast the fault event over the DDC bus. The other devices on the DDC bus can be configured to respond to the broadcast in several ways including group shutdown/restart. Fault spreading mode can be enabled through the USER_CONFIG PMBus command, and the fault spreading group can be defined through the DDC_GROUP PMBus command. Monitoring via SMBus A system controller can monitor a wide variety of different ZL2102 parameters through the SMBus interface. The device can monitor for fault conditions by monitoring the SALRT pin, which will be asserted when any number of preconfigured fault conditions occur. The device can also be monitored continuously for many power conversion parameters including input voltage, output voltage, output current, internal junction temperature, switching frequency, duty cycle, fault status information. The PMBus Host should respond to SALRT as follows: • ZL device pulls SALRT Low. • PMBus Host detects that SALRT is now low, performs transmission with Alert Response Address to find which ZL device is pulling SALRT low. • PMBus Host talks to the ZL device that has pulled SALRT low. The actions that the host performs are up to the System Designer. If multiple devices are faulting, SALRT will still be low after doing the above steps and will require transmission with the Alert Response Address repeatedly until all faults are cleared. Nonvolatile Memory The ZL2102 has internal nonvolatile memory where user settings are stored. There are two storage locations; the factory store and the user store. During the initialization process, the ZL2102 checks for any stored values in the user store. If user programmed settings are found, they will be used for those parameters. If there are no user settings stored, the factory settings and pin strap values are used for those parameters. Snapshot™ Parametric Capture The ZL2102 offers a special feature that enables the user to capture parametric data during normal operation or following a fault. The Snapshot function can be enabled through the MISC_CONFIG PMBus command, and the data can be read back as a block read transfer using the SNAPSHOT PMBus command. The SNAPSHOT_CONTROL PMBus command enables the user to store the snapshot parameters to NV memory in response to a fault as well as to read the stored data from NV memory after a fault has occurred. Automatic writes to NV memory following a fault are triggered when any fault threshold level is exceeded, provided that the Page 16 of 58 ZL2102 specific fault's response is to shut down. Writing to NV memory is not allowed if the device is configured to retry following the specific fault condition. The device's VDD voltage must remain valid during the time when the device is writing the data to NV memory; a process that requires up to 2ms. Power Train Component Selection The ZL2102 is a synchronous buck converter with MOSFETs that uses an external inductor and capacitors to perform the power conversion process. The proper selection of the external components is critical for optimized performance. To select the appropriate external components for the desired performance goals, the power supply requirements listed in Table 8 must be known. TABLE 8. TABLE SUPPLY REQUIREMENTS PARAMETER RANGE EXAMPLE VALUE Input voltage (VIN) 4.5V to 14.0V 12V Output voltage (VOUT) 0.6V to 5.0V 3.3V Output current (IOUT) 0A to 6A 4A Output voltage ripple (Vorip)