0
登录后你可以
  • 下载海量资料
  • 学习在线课程
  • 观看技术视频
  • 写文章/发帖/加入社区
会员中心
创作中心
发布
  • 发文章

  • 发资料

  • 发帖

  • 提问

  • 发视频

创作活动
ZL9024MAIRZ

ZL9024MAIRZ

  • 厂商:

    RENESAS(瑞萨)

  • 封装:

    SMD40

  • 描述:

    DC DC CONVERTER 0.6-1.5V

  • 数据手册
  • 价格&库存
ZL9024MAIRZ 数据手册
DATASHEET ZL9024M FN8837 Rev.1.00 Dec 20, 2017 Digital DC/DC PMBus 33A Module The ZL9024M is a 33A step-down DC/DC power supply module with integrated digital PWM controller, synchronous power switches, an inductor, and passives. Only bulk input and output capacitors are needed to finish the design. The 33A of continuous output current can be delivered without a need of airflow or a heatsink. The thermally enhanced HDA module is capable of dissipating heat directly into the PCB. The ZL9024M uses ChargeMode™ control architecture, which responds to a transient load within a single switching cycle. The ZL9024M comes with a preprogrammed configuration for operating in a pin-strap mode; output voltage, switching frequency, and device SMBus address can be programmed with external resistors. More configurations such as soft-start and fault limits, can be easily programmed or changed using PMBus compliant serial bus interface. PMBus can be used to monitor voltages, current, temperatures, and fault status. The ZL9024M is supported by PowerNavigator™ software, a Graphical User Interface (GUI) that can be used to configure modules to a desired solution. The ZL9024M is available in a 40 Ld compact 17mmx19mm HDA module with a very low profile height of 3.55mm, suitable for automated assembly by standard surface mount equipment. The ZL9024M is RoHS compliant by exemption. Features • Complete digital switch mode power supply • VIN range: 2.75V to 4V • Programmable VOUT range: 0.6V to 1.5V • PMBus compliant I2C communication interface • Programmable VOUT, margining, UV/OV, IOUT limit, soft-start/stop, sequencing, and external synchronization • Monitor: VIN, VOUT, IOUT, temperature, duty cycle, switching frequency, and faults • ChargeMode control architecture • ±1.2% VOUT accuracy over line, load, and temperature • Power-good indicator • Over-temperature protection • Internal non-volatile memory and fault logging • PowerNavigator supported • Patented thermally enhanced HDA package Applications • Server, telecom, storage, and datacom • Industrial/ATE and networking equipment Related Literature • For a full list of related documents, visit our website • General purpose power for ASIC, FPGA, DSP, and memory • ZL9024M product page 9,1 9287 N 96(1 96(1 9021 17mm 9287 &287 =/0 m &,1 19 m 9,1 6&/ 9'59 6'$ &9'' 6$/57 30%XV ,QWHUIDFH 9'' 9'' 3.55mm 6*1' 3*1' Note: 1. Only input and output capacitors are required to finish the design. Figure 1. Complete Digital Switch Mode Power Supply FN8837 Rev.1.00 Dec 20, 2017 Figure 2. Small Package for High Power Density Page 1 of 72 ZL9024M Contents 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 1.2 1.3 1.4 1.5 2. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 6 6 8 Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 2.2 2.3 2.4 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 10 11 11 3. Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 4.15 4.16 4.17 4.18 4.19 4.20 SMBus Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Soft-Start Delay and Ramp Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Good. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching Frequency and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loop Compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Undervoltage Lockout (UVLO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SMBus Module Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Prebias Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Overcurrent Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Overload Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital-DC Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Phase Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fault Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Monitoring Using the XTEMP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitoring Using SMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Snapshot Parameter Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Non-Volatile Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 16 17 17 17 18 18 18 19 19 20 20 20 20 21 21 21 22 22 22 5. PCB Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6. Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.1 6.2 6.3 Package Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 PCB Layout Pattern Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Thermal Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 FN8837 Rev.1.00 Dec 20, 2017 Page 2 of 72 ZL9024M 6.4 6.5 Stencil Pattern Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Reflow Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7. PMBus Command Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8. PMBus Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9. PMBus Use Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10. PMBus Commands Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 11. Firmware Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 12. Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 13. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 FN8837 Rev.1.00 Dec 20, 2017 Page 3 of 72 ZL9024M Overview 9,1 9'59 95 95 9 Block Diagram 9''& 1.1 9'' 1. 1. Overview 96(7 (1 /'2 /'2 2989 2787 2&8& 61$36+27 /'2 ,17(5/($9( 3RZHU0DQDJHPHQW )$8/7635($',1* 9,1 66 3* 0*1 ''& )% 6(48(1&( 0$5*,1,1* 615A/µs), 3.3VIN to 1.0VOUT, 533kHz Figure 10. Transient Response (0A to 16.5A, >15A/µs), 3.3VIN to 0.6VOUT, 533kHz FN8837 Rev.1.00 Dec 20, 2017 Page 14 of 72 ZL9024M 3. Typical Performance Curves VOUT (50mV/DIV) VOUT (500mV/DIV) IOUT (10A/DIV) PG (5V/DIV) 50µs/DIV 5ms/DIV Figure 11. Transient Response (0A to 16.5A, >15A/µs), 3.3VIN to 0.6VOUT, 320kHz Figure 12. Startup, 3.3VIN to 1.2VOUT, 0A VOUT (500mV/DIV) VOUT (500mV/DIV) PG (5V/DIV) PG (5V/DIV) 5ms/DIV Figure 13. Startup, 3.3VIN to 1.2VOUT, 33A 500ms/DIV Figure 14. Immediate Shutdown, 3.3VIN to 1.2VOUT, 0A VOUT (500mV/DIV) VOUT (500mV/DIV) PG (5V/DIV) PG (5V/DIV) 200µs/DIV Figure 15. Immediate Shutdown, 3.3VN to 1.2VOUT, 33A FN8837 Rev.1.00 Dec 20, 2017 5ms/DIV Figure 16. Soft-Off, 3.3VIN to 1.2VOUT, 33A Page 15 of 72 ZL9024M 4. 4. Functional Description Functional Description 4.1 SMBus Communications The ZL9024M provides an SMBus digital interface that enables the user to configure all aspects of the module operation as well as monitor the input and output parameters. The ZL9024M can be used with any SMBus host device. In addition, the module is compatible with PMBus Power System Management Protocol Specification Parts I and II version 1.2. The ZL9024M accepts most standard PMBus commands. When controlling the device with PMBus commands, it is recommended that the enable pin is tied to SGND. The SMBus device address is the only parameter that must be set by external pins. All other device parameters can be set with PMBus commands. 4.2 Output Voltage Selection The output voltage may be set to a voltage between 0.6V and 1.5V if the input voltage is higher than the desired output voltage by an amount sufficient to maintain regulation. The VSET pin is used to set the output voltage to levels as shown in Table 4. The RSET resistor is placed between the VSET pin and SGND. A standard 1% resistor is recommended. Table 4. Output Voltage Resistor Settings VOUT (V) RSET (kΩ) 0.60 10 0.65 11 0.70 12.1 0.75 13.3 0.80 14.7 0.85 16.2 0.90 17.8 0.95 19.6 1.00 21.5, or connect to SGND 1.05 23.7 1.10 26.1 1.15 28.7 1.20 31.6, or OPEN 1.25 34.8 1.30 38.3 1.40 42.2 1.50 46.4 The output voltage may also be set to any value between 0.6V and 1.5V using the PMBus command VOUT_COMMAND. By default, VOUT_MAX is set 110% higher than VOUT set by the pin-strap resistor, which can be changed to any value up to 2V with the PMBus command VOUT_MAX. FN8837 Rev.1.00 Dec 20, 2017 Page 16 of 72 ZL9024M 4.3 4. Functional Description Soft-Start Delay and Ramp Times It may be necessary to set a delay from when an enable signal is received until the output voltage starts to ramp to its target value. In addition, the designer may wish to precisely set the time required for VOUT to ramp to its target value after the delay period has expired. These features may be used as part of an overall inrush current management strategy or to precisely control how fast a load IC is turned on. The ZL9024M gives the system designer several options for precisely and independently controlling both the delay and ramp time periods. The soft-start delay period begins when the EN pin is asserted and ends when the delay time expires. The soft-start delay and ramp times can be programmed to custom values with the PMBus commands TON_DELAY and TON_RISE. When the delay time is set to 0ms, the device begins its ramp-up after the internal circuitry has initialized (approximately 2ms). When the soft-start ramp period is set to 0ms, the output ramps up as quickly as the output load capacitance and loop settings allow. It is generally recommended to set the soft-start ramp to a value greater than 500µs to prevent inadvertent fault conditions due to excessive inrush current. 4.4 Power-Good The ZL9024M provides a Power-Good (PG) signal that indicates the output voltage is within a specified tolerance of its target level and no fault condition exists. By default, the PG pin asserts if the output is within 10% of the target voltage. These limits and the polarity of the pin may be changed with the PMBus command POWER_GOOD_ON. A PG delay period is defined as the time from when all conditions within the ZL9024M for asserting PG are met to when the PG pin is actually asserted. This feature is commonly used instead of using an external reset controller to control external digital logic. A PG delay can be programmed with the PMBus command POWER_GOOD_DELAY. 4.5 Switching Frequency and PLL The device’s switching frequency is set from 296kHz to 1067kHz using the pin-strap method as shown in Table 5 on page 17, or by using the PMBus command FREQUENCY_SWITCH. The ZL9024M incorporates an internal Phase-Locked Loop (PLL) to clock the internal circuitry. The PLL can be driven by an external clock source connected to the SYNC pin. When using the internal oscillator, the SYNC pin can be configured as a clock source as a external sync to other modules. Refer to the SYNC_CONFIG command on page 60 for more information. Table 5. Switching Frequency Resistor Settings FN8837 Rev.1.00 Dec 20, 2017 fSW (kHz) RSET (kΩ) 296 14.7, or connect to SGND 320 16.2 364 17.8 400 19.6 421 21.5 471 23.7 533 26.1, or OPEN 571 28.7 615 31.6 727 34.8 800 38.3 842 42.2 889 46.4 1067 51.1, or connect to V25 Page 17 of 72 ZL9024M 4.6 4. Functional Description Loop Compensation The module is internally compensated using the PMBus command ASCR_CONFIG. The ZL9024M uses the ChargeMode control algorithm that responds to output current changes within a single PWM switching cycle, achieving a smaller total output voltage variation with less output capacitance than traditional PWM controllers. 4.7 Undervoltage Lockout (UVLO) The VDD Undervoltage Lockout (UVLO) prevents the ZL9024M from operating when the VDD falls below a preset threshold, indicating the driver voltage is out of its specified range. The input UVLO threshold prevents the ZL9024M from operating when the input supply voltage, VIN, falls below a preset threshold, which can be changed by using the PMBus command VIN_UV_FAULT_LIMIT. VDD needs to be higher than VDRV_UV_WARN_LIMIT for the module to start up. During startup, apply the VIN supply before the VDD bias voltage. Otherwise, the device may declare an input undervoltage fault condition. 4.8 SMBus Module Address Selection Each module must have its own unique serial address to distinguish between other devices on the bus. The module address is set by connecting a resistor between the SA pin and SGND. Table 6 lists the available module addresses. Table 6. SMBus Address Resistor Selection FN8837 Rev.1.00 Dec 20, 2017 RSA (kΩ) SMBus ADDRESS 10 19h 11 1Ah 12.1 1Bh 13.3 1Ch 14.7 1Dh 16.2 1Eh 17.8 1Fh 19.6 20h 21.5 21h 23.7 22h 26.1 23h 28.7 24h 31.6 25h 34.8, or connect to SGND 26h 38.3 27h 42.2, or Open 28h 46.4 29h 51.1 2Ah 56.2 2Bh 61.9 2Ch 68.1 2Dh 75 2Eh 82.5 2Fh 90.9 30h 100 31h Page 18 of 72 ZL9024M 4.9 4. Functional Description Output Overvoltage Protection The ZL9024M offers an internal output overvoltage protection circuit that can be used to protect sensitive load circuitry from being subjected to a voltage higher than its prescribed limits. A hardware comparator is used to compare the actual output voltage (seen at the VSEN+, VSEN- pins) to a threshold set to 15% higher than the target output voltage (the default setting). Fault threshold can be programmed to a desired level with the PMBus command VOUT_OV_FAULT_LIMIT. If the VSEN+ voltage exceeds this threshold, the module will initiate an immediate shutdown without retry. Retry settings can be programmed with the PMBus command VOUT_OV_FAULT_RESPONSE. Internal to the module, two 100Ω resistors are populated from VOUT to VSEN+ and SGND to VSEN- to protect from overvoltage conditions in case remote sense traces are not present or accidentally open. As long as differential remote sense traces have low resistance, VOUT regulation accuracy is not sacrificed. 4.10 Output Prebias Protection An output prebias condition exists when an externally applied voltage is present on a power supply’s output before the power supply’s control IC is enabled. Certain applications require that the converter not be allowed to sink current during start-up if a prebias condition exists at the output. The ZL9024M provides prebias protection by sampling the output voltage prior to initiating an output ramp. If a prebias voltage lower than the target voltage exists after the preconfigured delay period has expired, the target voltage is set to match the existing prebias voltage, and both drivers are enabled. The output voltage is then ramped to the final regulation value at the preconfigured ramp rate. The actual time the output takes to ramp from the prebias voltage to the target voltage varies, depending on the prebias voltage, however, the total time elapsed from when the delay period expires and when the output reaches its target value will match the preconfigured ramp time (see Figure 17). VOUT DESIRED OUTPUT VOLTAGE PREBIAS VOLTAGE TIME TONRISE TON- DELAY VPREBIAS < VTARGET VOUT PREBIAS VOLTAGE DESIRED OUTPUT VOLTAGE TIME TON- DELAY TONRISE VPREBIAS > VTARGET Figure 17. Output Responses to Prebias Voltages If a prebias voltage is higher than the target voltage after the preconfigured delay period has expired, the target voltage is set to match the existing prebias voltage, and both drivers are enabled with a PWM duty cycle that would ideally create the prebias voltage. FN8837 Rev.1.00 Dec 20, 2017 Page 19 of 72 ZL9024M 4. Functional Description Once the preconfigured soft-start ramp period has expired, the PG pin is asserted (assuming the prebias voltage is not higher than the overvoltage limit). The PWM then adjusts its duty cycle to match the original target voltage, and the output ramps down to the preconfigured output voltage. If a prebias voltage is higher than the overvoltage limit, the device does not initiate a turn-on sequence and declares an overvoltage fault condition. The device then responds based on the output overvoltage fault response setting programmed with the PMBus command VOUT_OV_FAULT_RESPONSE. 4.11 Output Overcurrent Protection The ZL9024M is protected from damage if the output is shorted to ground or if an overload condition is imposed on the output. The average output overcurrent fault threshold can be programmed by the PMBus command IOUT_AVG_OC_FAULT_LIMIT while the peak output overcurrent fault threshold can be programmed by the PMBus command IOUT_OC_FAULT_LIMIT. The default response from an average overcurrent fault is an immediate shutdown without retry. A continuous retry can be enabled using the PMBus command MFR_IOUT_OC_FAULT_RESPONSE. 4.12 Thermal Overload Protection The ZL9024M includes a thermal sensor that continuously measures the internal temperature of the module and shuts down the controller when the temperature exceeds the preset limit. The default temperature limit is set to +115°C in the factory, but can be changed with the PMBus command OT_FAULT_LIMIT. Note that the temperature reading from the PMBus command is the temperature of the internal controller, which is lower than the junction temperature of the module. The default response from an over-temperature fault is an immediate shutdown without retry. Retry settings can be programmed with the PMBus command OT_FAULT_RESPONSE. If the user has configured the module to retry, the controller waits the preset delay period (if configured to do so) and then checks the module temperature. If the temperature has dropped below a threshold that is approximately +15°C lower than the selected temperature fault limit, the controller attempts to restart. If the temperature still exceeds the fault limit, the controller waits the preset delay period and retries again. 4.13 Digital-DC Bus The Digital-DC Communications (DDC) bus is used to communicate between Intersil digital power modules and digital controllers. This dedicated bus provides the communication channel between devices for features such as sequencing and fault spreading. The DDC pin on all Digital-DC devices in an application should be connected together. A pull-up resistor is required on the DDC bus in order to guarantee the rise time, as shown in Equation 1: Rise Time = R PU C LOAD  1s (EQ. 1) Where RPU is the DDC bus pull-up resistance and CLOAD is the bus loading. The pull-up resistor may be tied to an external 3.3V or 5V supply as long as this voltage is present prior to or during device power-up. In principle, each device connected to the DDC bus presents approximately 10pF of capacitive loading, and each inch of FR4 PCB trace introduces approximately 2pF. The ideal design uses a central pull-up resistor that is well-matched to the total load capacitance. 4.14 Phase Spreading When multiple point-of-load converters share a common DC input supply, it is desirable to adjust the clock phase offset of each device, such that not all devices start to switch simultaneously. Setting each converter to start its switching cycle at a different point in time, can dramatically reduce input capacitance requirements and efficiency losses. Since the peak current drawn from the input supply is effectively spread out over a period of time, the peak current drawn at any given moment is reduced, and the power losses proportional to the IRMS2 are reduced dramatically. FN8837 Rev.1.00 Dec 20, 2017 Page 20 of 72 ZL9024M 4. Functional Description To enable phase spreading, all converters must be synchronized to the same switching clock. The phase offset of each device may also be set to any value between 0° and 360° in 22.5° increments with the PMBus command INTERLEAVE. 4.15 Output Sequencing A group of Digital-DC modules or devices may be configured to power-up in a predetermined sequence. This feature is especially useful when powering advanced processors, (FPGAs and ASICs that require one supply to reach its operating voltage) prior to another supply reaching its operating voltage in order to avoid latch-up. Multidevice sequencing can be achieved by configuring each device with the PMBus command SEQUENCE. Multiple device sequencing is configured by issuing PMBus commands to assign the preceding device in the sequencing chain as well as the device that follows in the sequencing chain. The Enable pins of all devices in a sequencing group must be tied together and driven high to initiate a sequenced turn-on of the group. Enable must be driven low to initiate a sequenced turnoff of the group. 4.16 Fault Spreading Digital DC modules and devices can be configured to broadcast a fault event over the DDC bus to the other devices in the group with the PMBus command DDC_GROUP. When a non-destructive fault occurs and the device is configured to shut down on a fault, the device shuts down and broadcasts the fault event over the DDC bus. The other devices on the DDC bus shut down simultaneously, if configured to do so, and attempt to restart in their prescribed order. 4.17 Temperature Monitoring Using the XTEMP Pin The ZL9024M supports measurement of an external device temperature using either a thermal diode integrated in a processor, FPGA or ASIC, or using a discrete diode-connected 2N3904 NPN transistor. Figure 18 illustrates the typical connections required. The external temperature sensors can be used to provide the temperature reading for over-temperature and under-temperature faults. These options for the external temperature sensors are enabled using the USER_CONFIG PMBus command. XTEMP+ ZL9024M 2N3904 XTEMP- Discrete NPN XTEMP+ ZL9024M µP FPGA DSP ASIC XTEMP- Embedded Thermal Diode Figure 18. External Temperature Monitoring FN8837 Rev.1.00 Dec 20, 2017 Page 21 of 72 ZL9024M 4.18 4. Functional Description Monitoring Using SMBus A system controller can monitor a wide variety of different ZL9024M system parameters with PMBus commands: • READ_VIN • READ_VOUT • READ_IOUT • READ_TEMPERATURE_1 • READ_TEMPERATURE_2 • READ_DUTY_CYCLE • READ_FREQEUNCY • READ_VDRV 4.19 Snapshot Parameter Capture The ZL9024M offers a special feature that enables the user to capture parametric data and some fault statuses during normal operation or following a fault. A detailed description is provided in “PMBus Commands Description” on page 33 under the PMBus command SNAPSHOT and SNAPSHOT_CONTROL. 4.20 Non-Volatile Memory The ZL9024M has internal non-volatile memory where user configurations are stored. Integrated security measures ensure that the user can only restore the module to a level that has been made available to them. During the initialization process, the ZL9024M checks for stored values contained in its internal non-volatile memory. Modules are shipped with factory defaults configuration and most settings can be overwritten with PMBus Commands and can be stored in non-volatile memory with the PMBus command STORE_USER_ALL. FN8837 Rev.1.00 Dec 20, 2017 Page 22 of 72 ZL9024M 5. 5. PCB Layout Guidelines PCB Layout Guidelines To achieve stable operation, low losses, and good thermal performance, some layout considerations are necessary. • Establish separate SGND and PGND planes, then connect SGND to the PGND plane as shown in Figure 20 on page 24 in the middle layer. For making connections between SGND/PGND on the top layer and other layers, use multiple vias for each pin to connect to the inner SGND/PGND layer. Do not connect SGND directly to PGND on a top layer. Connecting SGND directly to PGND without establishing an SGND plane will bypass the decoupling capacitor at internal reference supplies, making the controller susceptible to noise. • Place enough ceramic capacitors between VIN and PGND, VOUT and PGND, and bypass capacitors between VDD and the ground plane, as close to the module as possible to minimize high frequency noise. • Use large copper areas for the power path (VIN, PGND, VOUT) to minimize conduction loss and thermal stress. Also, use multiple vias to connect the power planes in different layers. Extra ceramic capacitors at VIN and VOUT can be placed on the bottom layer under the VIN and VOUT pads when multiple vias are used for connecting copper pads on top and bottom layers. • Connect differential remote sensing traces to the regulation point to achieve a tight output voltage regulation. Route a trace from VSEN+ to the point-of-load where the tight output voltage is desired. Avoid routing any sensitive signal traces, such as the VSENSE signal near the VSWH pads. • Connect differential remote sensing traces to the external temperature sensing point. Keep the traces as short as possible. If applicable, place the trace in the inner layer with the ground plane on the layer immediately below and on top of the traces. • For noise sensitive applications, it is recommended to connect VSWH pads only on the top layer; however, thermal performance is sacrificed. External airflow might be required to keep module heat at the desired level. For applications in which switching noise is less critical, an excellent thermal performance can be achieved in the ZL9024M module by increasing copper mass attached to the VSWH pad. To increase copper mass on the VSWH node, create copper islands in the middle and bottom layers under the VSWH pad and connect them to the top layer with multiple vias. Shield those copper islands with a PGND layer to avoid any interference to noise sensitive signals. FN8837 Rev.1.00 Dec 20, 2017 Page 23 of 72 5. PCB Layout Guidelines 3*1' 6*1' (1 6&/ 6'$ 6$/57 6$ 9021 0*1 96(7 1& 6*1' 3*1' ZL9024M 89/2 1& 1& & 6*1' 95 96(1 6*1' 3$' 96(1 9'59 $ % 95 9''& 3* ;7(03 6
ZL9024MAIRZ 价格&库存

很抱歉,暂时无法提供与“ZL9024MAIRZ”相匹配的价格&库存,您可以联系我们找货

免费人工找货