ZSPM4141AI1W33

Ultra-Low-Power Linear Regulator with Minimal Quiescent Current Technology Brief Description Benefits The ZSPM4141 is an ultra-low-power linear regulator optimized for minimal quiescent current losses via advanced, proprietary technology. It can improve energy efficiency and reduce heat due to power dissipation because it draws low nA-level quiescent current for light loads, yet it can regulate current loads as high as 200mA. The linear regulated output voltage is factory-configured to an option from 1.2V to 4.2V in 100mV steps. The ZSPM4141 also provides over-current protection. • • • • • • Features • • • Datasheet Ultra-low 100pA quiescent current in power down mode Best-in-class quiescent current of 20nA at ILOAD=0 0.5% DC line regulation (typical) Extends battery life Enables power harvesting applications High level of integration minimizes board space Related IDT Smart Power Products • • ZSPM4141 Low operating voltage range: 2.5V to 5.5V Power-Down Mode for 100pA quiescent current Over-current protection: 250mA Output voltage options of 1.2V to 4.2V in 100mV steps (programmed at manufacturing) ZSPM4121 Under-Voltage Load Switch for Smart Battery Management Available Support • • ZSPM4141W12KIT Evaluation Kit Support Documentation Physical Characteristics • Package: 8-pin DFN (2mm x2mm) Typical ZSPM4141 Application Circuits ZSPM4141 Basic (Fixed Output) Application VCC = 2.5V to 5.5V VCC VOUT ZSPM4141 CBYP EN ZSPM4141AI1W12 Variable VOUT via Resistor Divider VCC = 2.5V to 5.5V VOUT = 1.2V to 4.2V COUT 2.2µF (typical) VCC ZSPM4141 CBYP FB VOUT R1 VOUT = 1.2V to 4.2V COUT 2.2µF (typical) FB EN R2 GND © 2016 Integrated Device Technology, Inc. GND 1 January 29, 2016 ZSPM4141 Ultra-Low-Power Linear Regulator with Minimal Quiescent Current Technology Datasheet ZSPM4141 Block Diagram VOUT VCC Current Limit Typical Applications FB • Portable Electronics • Industrial • Medical • Smart Cards • RFID Energy-Harvesting Systems • Reference Voltage EN ZSPM4141 GND Ordering Information Ordering Code* Description Package ZSPM4141AI1W12 ZSPM4141 Ultra-Low Power Line Regulator —VOUT factory set to 1.2V 8-pin DFN / Reel ZSPM4141AI1W18 ZSPM4141 Ultra-Low Power Line Regulator —VOUT factory set to 1.8V 8-pin DFN / Reel ZSPM4141AI1W25 ZSPM4141 Ultra-Low Power Line Regulator —VOUT factory set to 2.5V 8-pin DFN / Reel ZSPM4141AI1W30 ZSPM4141 Ultra-Low Power Line Regulator —VOUT factory set to 3.0V 8-pin DFN / Reel ZSPM4141AI1W31 ZSPM4141 Ultra-Low Power Line Regulator —VOUT factory set to 3.1V 8-pin DFN / Reel ZSPM4141AI1W33 ZSPM4141 Ultra-Low Power Line Regulator —VOUT factory set to 3.3V 8-pin DFN / Reel ZSPM4141AI1W42 ZSPM4141 Ultra-Low Power Line Regulator —VOUT factory set to 4.2V 8-pin DFN / Reel ZSPM4141W12KIT ZSPM4141 Evaluation Kit w/Vout adjusting resistors (default 1.2 Vout) * W for 7” reel with 2500 parts. Custom VOUT values are also available: 1.2V to 4.2V (typical) in 100mV increments. Corporate Headquarters Sales 6024 Silver Creek Valley Road San Jose, CA 95138 www.IDT.com 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Tech Support www.IDT.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. All contents of this document are copyright of Integrated Device Technology, Inc. All rights reserved. © 2016 Integrated Device Technology, Inc. 2 January 29, 2016 ZSPM4141 Datasheet Contents 1 2 3 4 5 6 7 8 9 ZSPM4141 Characteristics.................................................................................................................................. 5 1.1. Absolute Maximum Ratings .......................................................................................................................... 5 1.2. Thermal Characteristics ................................................................................................................................ 5 1.3. Recommended Operating Conditions .......................................................................................................... 6 1.4. Electrical Characteristics .............................................................................................................................. 6 Typical Performance Characteristics .................................................................................................................. 7 Description of Circuit ........................................................................................................................................... 9 Application Circuits ............................................................................................................................................ 10 4.1. Selection of External Components ............................................................................................................. 10 4.1.1. Output Bypass Capacitor COUT ............................................................................................................ 10 4.1.2. Input Bypass Capacitor CBYP................................................................................................................ 10 4.1.3. Output Voltage Adjustment Resistors R1 and R2................................................................................ 10 4.2. Typical Application Circuit .......................................................................................................................... 11 Pin Configuration and Package ......................................................................................................................... 12 5.1. ZSPM4141 Package Dimensions and Marking Diagram ........................................................................... 12 5.2. Pin Assignments ......................................................................................................................................... 13 Layout and Soldering Requirements ................................................................................................................. 14 6.1. Recommended Landing Pattern for PCBs ................................................................................................. 14 6.2. Multi-Layer PCB Layout .............................................................................................................................. 15 6.3. Single-Layer PCB Layout ........................................................................................................................... 16 Ordering Information ......................................................................................................................................... 17 Related Documents ........................................................................................................................................... 17 Document Revision History ............................................................................................................................... 18 List of Figures Figure 2.1 Figure 2.2 Figure 2.3 Figure 2.4 Figure 2.5 Figure 2.6 Figure 2.7 Figure 2.8 Figure 2.9 Figure 2.10 Figure 2.11 Figure 2.12 IQQ Performance vs. VCC ........................................................................................................................ 7 IQQ Performance vs. Temperature ......................................................................................................... 7 IQQ Performance vs. Load Current ......................................................................................................... 7 IQQ Performance vs. Load Current in % ................................................................................................. 7 Line Regulation Performance ................................................................................................................ 7 VOUT Performance vs. Temperature....................................................................................................... 7 Dropout Voltage When VOUT Drops By 3% ............................................................................................ 8 Load Regulation Performance ............................................................................................................... 8 Load Step Response—IOUT = 0 to 30mA ............................................................................................... 8 Load Step Response—IOUT =30mA to 0 ................................................................................................ 8 Load Step Response—IOUT = 1mA to 30mA.......................................................................................... 8 Line Step Response .............................................................................................................................. 8 © 2016 Integrated Device Technology, Inc. 3 January 29, 2016 ZSPM4141 Datasheet Figure 2.13 Figure 3.1 Figure 4.1 Figure 4.2 Figure 5.1 Figure 5.2 Figure 6.1 Figure 6.2 Figure 6.3 Figure 6.4 Figure 6.5 Output Enable Timing ............................................................................................................................ 9 ZSPM4141 Block Diagram .................................................................................................................... 9 Basic ZSPM4141 Application Circuit—Fixed Output ........................................................................... 11 ZSPM4141AI1W12 Application Circuit—Variable Output ................................................................... 11 ZSPM4141 Package Drawing.............................................................................................................. 12 ZSPM4141 Pin Assignments (top view) .............................................................................................. 13 Recommended Landing Pattern for 8-Pin DFN ................................................................................... 14 Package and PCB Land Configuration for Multi-Layer PCB .............................................................. 15 JEDEC Standard FR4 Multi-Layer Board – Cross-Sectional View...................................................... 15 Conducting Heat Away from the Die using an Exposed Pad Package ............................................... 16 Application Using a Single-Layer PCB ................................................................................................ 16 List of Tables Table 1.1 Table 1.2 Table 1.3 Table 1.4 Table 4.1 Table 5.1 Absolute Maximum Ratings ................................................................................................................... 5 Thermal Characteristics for 8-pin DFN (2x2) Package .......................................................................... 5 Recommended Operating Conditions ................................................................................................... 6 Electrical Characteristics ....................................................................................................................... 6 Output Voltage Adjustment Resistors and Resulting IQQ Increase ...................................................... 10 Pin Description, 8-Pin DFN (2mmx2mm) ............................................................................................ 13 © 2016 Integrated Device Technology, Inc. 4 January 29, 2016 ZSPM4141 Datasheet 1 ZSPM4141 Characteristics Important: Stresses beyond those listed under “Absolute Maximum Ratings” (section 1.1) may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” (section 1.3) is not implied. Exposure to absolute–maximum–rated conditions for extended periods could affect device reliability. 1.1. Absolute Maximum Ratings Over operating free–air temperature range unless otherwise noted. All voltage values are with respect to network ground terminal. Table 1.1 Absolute Maximum Ratings Parameter Symbol Maximum input/output on VCC, VOUT, EN, and FB pins Electrostatic Discharge – Human Body Model, according to the respective JESD22 JEDEC standard Electrostatic Discharge – Charged Device Model, according to the respective JESD22-C101 JEDEC standard Value Unit -0.3 to 6.0 V 2 kV 500 V Operating Junction Temperature Range TJ -20 to 85 °C Storage Temperature Range Tstg -65 to 150 °C 260 °C Lead Temperature (soldering, 10 seconds) 1.2. Thermal Characteristics Table 1.2 Thermal Characteristics for 8-pin DFN (2x2) Package θJA (°C/W) 1) θJC (°C/W) 73.1 2) 10.7 1) This assumes a FR4 board only. 2) This assumes a 1oz. copper JEDEC standard board with thermal vias. See section 6.1 for more information. © 2016 Integrated Device Technology, Inc. 5 January 29, 2016 ZSPM4141 Datasheet 1.3. Recommended Operating Conditions Table 1.3 Recommended Operating Conditions Parameter Symbol Min Unregulated Supply Input at VCC pin VCC Enable Input (EN pin) Typical Regulated Supply Output Voltage Operating Ambient Temperature 1) Operating Junction Temperature 1) 1.4. Typ Max Unit 2.5 5.5 V VEN 0 5.0 V VOUT 1.2 4.2 V TA -20 55 °C TJ -20 85 °C Operating ambient temperature is only intended as a guideline. The operating junction temperature requirements must not be exceeded. Electrical Characteristics Electrical characteristics, VCC = 2.5V to 5V (unless otherwise noted). Minimum and maximum characteristics tested at TJ = 25°C. Table 1.4 Electrical Characteristics Parameter Symbol Condition Min Input Supply Voltage VCC Input Low Logic Level VilEN Input High Logic Level VihEN 0.7*VCC Output Bypass Capacitor COUT 1 Input Bypass Capacitor CBYP Quiescent Current: Quiescent Current: PowerDown Mode Operating Current IQQ IQQpd IOP-GND 2.5 Max Unit 5.5 V 0.3*VCC V V 2.2 4.7 µF 0.1 µF VCC = 4.2V, IOUT=0 20 nA IOUT=0, EN = 0 100 pA VCC = 2.5V, IOUT = 200mA 200 µA VCC = 3.3V, IOUT = 200mA 200 µA VCC = 5.5V, IOUT = 200mA 200 µA Load Capability IOUT DC Line Regulation VLINE VCC = 2.5V to 5V, VOUT =1.8V, IOUT = 50mA DC Load Regulation VLOAD VCC = 4.2V, IOUT = 0.02mA to 200mA, VOUT = VOUT,nominal+300mV Current Limit ILIMIT IOUT measured at VOUT = 0.9*VOUT,nominal © 2016 Integrated Device Technology, Inc. Typ 0 6 200 mA 0.5 1 % 1 2 % 250 mA January 29, 2016 ZSPM4141 Datasheet 2 Typical Performance Characteristics CIN = 10µF and T = 25°C (unless otherwise noted) Figure 2.1 IQQ Performance vs. VCC Figure 2.2 IQQ Performance vs. Temperature Figure 2.3 IQQ Performance vs. Load Current Figure 2.4 IQQ Performance vs. Load Current in % Figure 2.5 Line Regulation Performance Figure 2.6 VOUT Performance vs. Temperature © 2016 Integrated Device Technology, Inc. 7 January 29, 2016 ZSPM4141 Datasheet Figure 2.7 Dropout Voltage When VOUT Drops By 3% Figure 2.8 Load Regulation Performance Note: Dropout voltage is defined as VCC – VOUT when VOUT drops 3% below its nominal value. Figure 2.9 Load Step Response—IOUT = 0 to 30mA Figure 2.10 Load Step Response—IOUT =30mA to 0 Figure 2.11 Load Step Response—IOUT = 1mA to 30mA Figure 2.12 Line Step Response © 2016 Integrated Device Technology, Inc. 8 January 29, 2016 ZSPM4141 Datasheet Figure 2.13 3 Output Enable Timing Description of Circuit The ZSPM4141 is an ultra-low-power linear regulator optimized for minimal quiescent current losses via advanced, proprietary technology. It draws low nA-level quiescent current for light loads, yet it can regulate current loads as high as 200mA. The linear regulated output voltage is factory-configured to an option from 1.2V to 4.2V in 100mV steps. The ZSPM4141 also provides over-current protection (see Table 1.4). Figure 3.1 ZSPM4141 Block Diagram VOUT VCC Current Limit FB Reference Voltage EN ZSPM4141 GND © 2016 Integrated Device Technology, Inc. 9 January 29, 2016 ZSPM4141 Datasheet 4 4.1. 4.1.1. Application Circuits Selection of External Components Output Bypass Capacitor COUT Connect a bypass capacitor (COUT) from the VOUT pin to ground. The typical value for COUT is 2.2µF. See Table 1.4 for further specifications. 4.1.2. Input Bypass Capacitor CBYP Connect a bypass capacitor (CBYP) from the VCC pin to ground. The typical value for COUT is 0.1µF. 4.1.3. Output Voltage Adjustment Resistors R1 and R2 The ZSPM4141W12KIT includes a set of output adjustment resistors for R1 and R2 shown in the variable output circuit on page 2. Refer to Table 4.1 for the effect of different combinations of the resistors on the output voltage and the resulting increase in IQQ current. Table 4.1 Output Voltage Adjustment Resistors and Resulting IQQ Increase Vout R1 (+/-0.1%) R2 (+/-1%) IQQ increase 1.2 0 1.5 1.00MΩ 4.02MΩ 0.30µA 1.8 1.00MΩ 2MΩ 0.60µA 3 1.00MΩ 665kΩ 1.80µA 3.3 1.00MΩ 576kΩ 2.10µA 4.2 1.00MΩ 402kΩ 3.00µA © 2016 Integrated Device Technology, Inc. 10 January 29, 2016 ZSPM4141 Datasheet 4.2. Typical Application Circuit Figure 4.1 Basic ZSPM4141 Application Circuit—Fixed Output ZSPM4141 VCC = 2.5V to 5.5V VOUT = 1.2V to 4.2V VCC VOUT CBYP COUT 0.1µF (typical) 2.2µF (typical) EN Load FB GND Figure 4.2 ZSPM4141AI1W12 Application Circuit—Variable Output ZSPM4141AI1W12 VCC = 2.5V to 5.5V VOUT = 1.2V to 4.2V VCC VOUT R1 CBYP 0.1µF (typical) Load COUT 2.2µF (typical) EN FB GND R2 © 2016 Integrated Device Technology, Inc. 11 January 29, 2016 ZSPM4141 Datasheet 5 Pin Configuration and Package 5.1. ZSPM4141 Package Dimensions and Marking Diagram Figure 5.1 ZSPM4141 Package Drawing MARKING CODES: Z: P: ZMDI Product Code: 1 = ZSPM4141 V: Voltage levels: 0 = 1.2, 1 = 1.3, 2 = 1.4, 3 = 1.5, 4 = 1.6, 5 = 1.7, 6 = 1.8, 7 = 1.9, 8 = 2.0, 9 = 2.1, A = 2.2, B = 2.3, C = 2.4, D to U = 2.5 to 4.2 YM: Date Code (Year, Month) The ZSPM4141 is packaged as an 8-pin DFN (2mm x2mm). © 2016 Integrated Device Technology, Inc. 12 January 29, 2016 ZSPM4141 Datasheet 5.2. Pin Assignments Figure 5.2 ZSPM4141 Pin Assignments (top view) Table 5.1 EN 8 VCC 7 NC FB 6 NC NC 5 1 GND 2 VOUT 3 4 Pin Description, 8-Pin DFN (2mmx2mm) Pin # Name Function 1 GND Ground GND 2 VOUT Output Regulated Output Voltage 3 NC No Connection (connect to GND or float) 4 NC No Connection (connect to GND or float) 5 NC No Connection (connect to GND or float) 6 FB Input 7 VCC Supply Input Power 8 EN Input Enable Input © 2016 Integrated Device Technology, Inc. Description Feedback Input 13 January 29, 2016 ZSPM4141 Datasheet 6 Layout and Soldering Requirements To maximize the efficiency of this package for applications on a single layer or multi-layer printed circuit board (PCB), certain guidelines must be followed when laying out this part on the PCB. 6.1. Recommended Landing Pattern for PCBs Figure 6.1 Recommended Landing Pattern for 8-Pin DFN © 2016 Integrated Device Technology, Inc. 14 January 29, 2016 ZSPM4141 Datasheet 6.2. Multi-Layer PCB Layout The following are guidelines for mounting the exposed pad ZSPM4141 on a multi-layer PCB with ground a plane. In a multi-layer board application, the thermal vias are the primary method of heat transfer from the package thermal pad to the internal ground plane. The efficiency of this method depends on several factors, including die area, number of thermal vias, and thickness of copper, etc. Figure 6.2 Package and PCB Land Configuration for Multi-Layer PCB Solder Pad (Land Pattern) Package Thermal Pad Thermal Vias Package Outline Figure 6.3 JEDEC Standard FR4 Multi-Layer Board – Cross-Sectional View (square) Package Solder Pad 1.5038 - 1.5748 mm Component Trace (2oz Cu) 2 Plane 4 Plane 1.5748mm Component Traces Thermal Via Thermal Isolation Power plane only 1.0142 - 1.0502 mm Ground Plane (1oz Cu) 0.5246 - 0.5606 mm Power Plane (1oz Cu) 0.0 - 0.071 mm Board Base & Bottom Pad Package Solder Pad (bottom trace) Figure 6.4 is a representation of how the heat can be conducted away from the die using an exposed pad package. Each application will have different requirements and limitations, and therefore the user should use sufficient copper to dissipate the power in the system. The output current rating for the linear regulators might need to be de-rated for ambient temperatures above 85°C. The de-rated value will depend on calculated worstcase power dissipation and the thermal management implementation in the application. © 2016 Integrated Device Technology, Inc. 15 January 29, 2016 ZSPM4141 Datasheet Figure 6.4 Conducting Heat Away from the Die using an Exposed Pad Package Mold compound Die Epoxy Die attach Exposed pad Solder 5% - 10% Cu coverage Single Layer, 2oz Cu Ground Layer, 1oz Cu Signal Layer, 1oz Cu Thermal Vias with Cu plating 90% Cu coverage 20% Cu coverage Bottom Layer, 2oz Cu Note: NOT to scale. 6.3. Single-Layer PCB Layout Layout recommendation for a single-layer PCB: utilize as much copper area for power management as possible. In a single-layer board application, the thermal pad is attached to a heat spreader (copper areas) by using a low thermal impedance attachment method (solder paste or thermal conductive epoxy). In both of the methods mentioned above, it is advisable to use as much copper trace as possible to dissipate the heat. Figure 6.5 Application Using a Single-Layer PCB Use as much copper area as possible for heat spread Package Thermal Pad Package Outline Important: If the attachment method is NOT implemented correctly, the functionality of the product is not guaranteed. Power dissipation capability will be adversely affected if the device is incorrectly mounted onto the circuit board. © 2016 Integrated Device Technology, Inc. 16 January 29, 2016 ZSPM4141 Datasheet 7 Ordering Information Ordering Code* Description Package ZSPM4141AI1W12 ZSPM4141 Ultra-Low Power Line Regulator —VOUT factory set to 1.2V 8-pin DFN / Reel ZSPM4141AI1W18 ZSPM4141 Ultra-Low Power Line Regulator —VOUT factory set to 1.8V 8-pin DFN / Reel ZSPM4141AI1W25 ZSPM4141 Ultra-Low Power Line Regulator —VOUT factory set to 2.5V 8-pin DFN / Reel ZSPM4141AI1W30 ZSPM4141 Ultra-Low Power Line Regulator —VOUT factory set to 3.0V 8-pin DFN / Reel ZSPM4141AI1W31 ZSPM4141 Ultra-Low Power Line Regulator —VOUT factory set to 3.1V 8-pin DFN / Reel ZSPM4141AI1W33 ZSPM4141 Ultra-Low Power Line Regulator —VOUT factory set to 3.3V 8-pin DFN / Reel ZSPM4141AI1W42 ZSPM4141 Ultra-Low Power Line Regulator —VOUT factory set to 4.2V 8-pin DFN / Reel ZSPM4141W12KIT ZSPM4141 Evaluation Kit w/Vout adjusting resistors (default 1.2 Vout) Custom VOUT values are also available: 1.2V to 4.2V (typical) in 100mV increments. 8 Related Documents Document ZSPM4141 Feature Sheet ZSPM4141 Evaluation Kit Description ZSPM4141 Application Note—Low Power Battery Control and Voltage Regulator Solutions for Remote Sensor Networks Visit IDT’s website www.IDT.com or contact your nearest sales office for the latest version of these documents. © 2016 Integrated Device Technology, Inc. 17 January 29, 2016 ZSPM4141 Datasheet 9 Document Revision History Revision Date Description 1.00 August 6, 2012 First release. 2.00 January 11, 2013 Addition of variable output illustration and Table 4.1. Update for ordering codes and contact information. Update for “Electrostatic Discharge” specification in Table 1.1. January 29, 2016 Changed to IDT branding. Corporate Headquarters Sales 6024 Silver Creek Valley Road San Jose, CA 95138 www.IDT.com 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Tech Support www.IDT.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. All contents of this document are copyright of Integrated Device Technology, Inc. All rights reserved. \ © 2016 Integrated Device Technology, Inc. 18 January 29, 2016