RX5500

® · Designed for Short-Range Wireless Control Applications · 3 V, Low Current Operation plus Sleep Mode · Characterized for Automotive Applications · High EMI Rejection Capability RX5500 433.92 MHz Hybrid Receiver The RX5500 hybrid receiver is ideal for short-range wireless control applications where robust operation, small size, low power consumption and low cost are required. The RX5500 employs RFM’s amplifier-sequenced hybrid (ASH) architecture to achieve this unique blend of characteristics. All critical RF functions are contained in the hybrid, simplifying and speeding design-in. The RX5500 is sensitive and stable. A wide dynamic range log detector provides robust performance in the presence of on-channel interference or noise. Two stages of SAW filtering provide excellent receiver out-of-band rejection. The RX5500 generates virtually no RF emissions, facilitating compliance with ETSI I-ETS 300 220 and similar regulations. Absolute Maximum Ratings Rating Power Supply and All Input/Output Pins Non-Operating Case Temperature Soldering Temperature (10 seconds) Value -0.3 to +4.0 -50 to +100 250 Units V o o C C Electrical Characteristics (typical values given for 3.0 Vdc power supply, 25 oC) Characteristic Operating Frequency Modulation Type Data Rate Receiver Performance, High Sensitivity Mode Sensitivity, 1.2 kbps, 10-3 BER, AM Test Method Sensitivity, 1.2 kbps, 10-3 BER, Pulse Test Method Current, 1.2 kbps (RPR = 330 K) Sensitivity, 2.4 kbps, 10-3 BER, AM Test Method Sensitivity, 2.4 kbps, 10-3 BER, Pulse Test Method Current, 2.4 kbps (RPR = 330 K) Sensitivity, 19.2 kbps, 10-3 BER, AM Test Method Sensitivity, 19.2 kbps, 10-3 BER, Pulse Test Method Current, 19.2 kbps Receiver Performance, Low Current Mode Sensitivity, 1.2 kbps, 10-3 BER, AM Test Method Sensitivity, 1.2 kbps, 10-3 BER, Pulse Test Method Current, 1.2 kbps (RPR = 2000 K) 1 1 2 -104 -98 1.65 dBm dBm mA 1 1 2 1 1 2 1 1 -110.5 -104.5 2.9 -109 -103 3.0 -105 -99 3.1 dBm dBm mA dBm dBm mA dBm dBm mA Sym fO Notes Minimum 433.72 OOK/ASK 19.2 kbps Typical Maximum 434.12 Units MHz 1 Electrical Characteristics (typical values given for 3.0 Vdc power supply, 25 oC) Characteristic Receiver Out-of-Band Rejection, ±5% fO Receiver Ultimate Rejection Sleep Mode Current Power Supply Voltage Range Power Supply Voltage Ripple Ambient Operating Temperature TA -40 Sym R±5% RULT IS VCC 2.2 Notes 3 3 Minimum Typical 80 100 0.7 3.7 10 85 Maximum Units dB dB µA Vdc mVP-P o C Notes: 1. Typical sensitivity data is based on a 10-3 bit error rate (BER), using DC-balanced data. There are two test methods commonly used to measure OOK/ASK receiver sensitivity, the “100% AM” test method and the “Pulse” test method. Sensitivity data is given for both test methods. See Appendix 3.8 in the ASH Transceiver Designer’s Guide for the details of each test method, and for sensitivity curves for a 2.2 to 3.7 V supply voltage range at five operating temperatures. The application/test circuit and component values are shown on the next page and in the Designer’s Guide. 2. At low data rates it is possible to adjust the ASH pulse generator to trade-off some receiver sensitivity for lower operating current. Sensitivity data and receiver current are given at 1.2 kbps for both high sensitivity operation (RPR = 330 K) and low current operation (RPR = 2000 K). 3. Data is given with the ASH radio matched to a 50 ohm load. Matching component values are given on the next page. 4. See Table 1 on Page 8 for additional information on ASH radio event timing. S M -2 0 L P a c k a g e D r a w in g 0 .3 8 " (9 .6 5 ) 0 .0 8 " (2 .0 3 ) 0 .1 2 5 " (3 .2 0 ) A S H T r a n s c e iv e r P in O u t GND1 0 .0 2 " (0 .5 1 ) R F IO 1 20 19 2 3 4 5 6 7 8 9 10 11 RREF 18 17 16 15 14 13 12 GND3 CNTRL0 CNTRL1 VCC2 P W ID T H PRATE THLD 1 THLD 2 VCC1 AGCCAP 0 .4 3 " (1 0 .9 ) 0 .0 4 " (1 .0 2 ) PKDET BBOUT C M P IN 0 .0 7 5 " (1 .9 0 ) 0 .1 3 " (3 .3 0 ) RXDATA TXM OD LPFADJ GND2 2 A S H R e c e iv e r A p p lic a tio n C ir c u it O O K C o n fig u r a tio n +3 VDC C + DCB R /S R PW R R PR TH1 19 18 CNT R L0 17 CNT R L1 16 VCC 2 15 P W ID T H 14 P RATE 13 TH LD 1 NC 12 L AT 20 GND 3 R F IO GND1 VCC 1 1 2 RREF T O P V IE W RF A1 3 PK DET 4 BB OUT 5 BBO 11 R REF L ESD CMP IN 6 RX DATA 7 NC 8 GND2 LPF ADJ 9 10 R +3 VDC C RFB1 R LPF C C LPF BBO D a ta O u tp u t Receiver Set-Up, 3.0 Vdc, -40 to +85 0C Item Nominal NRZ Data Rate Minimum Signal Pulse Maximum Signal Pulse BBOUT Capacitor BBOUT Resistor LPFAUX Capacitor LPFADJ Resistor RREF Resistor THLD1 Resistor PRATE Resistor PWIDTH Resistor DC Bypass Capacitor RF Bypass Capacitor 1 Antenna Tuning Inductor Shunt Tuning/ESD Inductor Symbol DRNOM SPMIN SPMAX CBBO RBBO CLPF RLPF RREF RTH1 RPR RPW CDCB CRFB1 LAT LESD OOK 1.2 833.33 3333.33 0.2 12 0.01 330 100 0 330 270 to GND 4.7 100 56 220 OOK 2.4 416.67 1666.68 0.1 12 0.0047 300 100 0 330 270 to GND 4.7 100 56 220 OOK 19.2 52.08 208.32 0.015 0 100 100 0 330 270 to GND 4.7 100 56 220 Units kbps µs µs µF K µF K K K K K µF pF nH nH Notes see pages 1 & 2 single bit 4 bits of same value ±10% ceramic ±5% ±5% ±5% ±1% ±1%, typical values ±5% ±5% tantalum ±5% NPO 50 ohm antenna 50 ohm antenna CAUTION: Electrostatic Sensitive Device. Observe precautions when handling. 3 ASH Receiver Theory of Operation Introduction RFM’s RX5500 amplifier-sequenced hybrid (ASH) receivers are specifically designed for short-range wireless control and data communication applications. The receivers provide robust operation, very small size, low power consumption and low implementation cost. All critical RF functions are contained in the hybrid, simplifying and speeding design-in. The ASH receiver can be readily configured to support a wide range of data rates and protocol requirements. The receiver features virtually no RF emissions, making it easy to certify to short-range (unlicensed) radio regulations. Amplifier-Sequenced Receiver Operation The ASH receiver’s unique feature set is made possible by its system architecture. The heart of the receiver is the amplifiersequenced receiver section, which provides more than 100 dB of stable RF and detector gain without any special shielding or decoupling provisions. Stability is achieved by distributing the total RF gain over time. This is in contrast to a superheterodyne receiver, which achieves stability by distributing total RF gain over multiple frequencies. Figure 1 shows the basic block diagram and timing cycle for an amplifier-sequenced receiver. Note that the bias to RF amplifiers RFA1 and RFA2 are independently controlled by a pulse generator, and that the two amplifiers are coupled by a surface acoustic wave (SAW) delay line, which has a typical delay of 0.5 µs. An incoming RF signal is first filtered by a narrow-band SAW filter, and is then applied to RFA1. The pulse generator turns RFA1 ON for 0.5 µs. The amplified signal from RFA1 emerges from the SAW delay line at the input to RFA2. RFA1 is now switched OFF and RFA2 is switched ON for 0.55 µs, amplifying the RF signal further. The ON time for RFA2 is usually set at 1.1 times the ON time for RFA1, as the filtering effect of the SAW delay line stretches the signal pulse from RFA1 somewhat. As shown in the timing diagram, RFA1 and RFA2 are never on at the same time, assuring excellent receiver stability. Note that the narrow-band SAW filter eliminates sampling sideband responses outside of the receiver passband, and the SAW filter and delay line act together to provide very high receiver ultimate rejection. Amplifier-sequenced receiver operation has several interesting characteristics that can be exploited in system design. The RF amplifiers in an amplifier-sequenced receiver can be turned on and off almost instantly, allowing for very quick power-down (sleep) and wake-up times. Also, both RF amplifiers can be off between ON sequences to trade-off receiver noise figure for lower average current consumption. The effect on noise figure can be modeled as if RFA1 is on continuously, with an attenuator placed in front of it with a loss equivalent to 10*log10(RFA1 duty factor), where the duty factor is the average amount of time RFA1 is ON (up to 50%). Since an amplifier-sequenced receiver is inherently a sampling receiver, the overall cycle time between the start of one RFA1 ON sequence and A S H R e c e iv e r B lo c k D ia g r a m A n te n n a & T im in g C y c le SAW F ilte r RFA1 P1 SAW D e la y L in e RFA2 P2 D e te c to r & L o w -P a s s F ilte r D a ta O ut P u ls e G e n e ra to r R F In p u t tP P1 RFA1 O ut W1 R F D a ta P u ls e tP tP RC RI D e la y L in e O ut tP P2 W2 Figure 1 4 R X 5 5 0 0 S e r ie s A S H R e c e iv e r B lo c k D ia g r a m RFA1 C N TR L1 C N TR L0 VCC VCC GND GND GND NC: RRE CMP NC: NC: P in P in P in P in P in P in F : P in IN : P in P in P in 2: 1: 2: 3: 1: 2 1 16 19 8 11 6 4 12 BBOUT L o w -P a s s F ilte r LPFADJ 9 R LPF 17 18 B ia s C o n tr o l Power Down C o n tro l 10 A n te n n a 3 R F IO ESD C hoke 20 SAW C R F ilte r RFA1 SAW D e la y L in e RFA2 Log D e te c to r BB 5 C 6 BBO DS1 T h ld T h r e s h o ld C o n tro l 7 RXDATA Ref TH LD1 13 R P u ls e G e n e r a to r & R F A m p B ia s PRATE 14 R PR TH1 11 RREF R REF 15 P W ID T H R PW Figure 2 the start of the next RFA1 ON sequence should be set to sample the narrowest RF data pulse at least 10 times. Otherwise, significant edge jitter will be added to the detected data pulse. RX5500 Series ASH Receiver Block Diagram Figure 2 is the general block diagram of the RX5500 series ASH receiver. Please refer to Figure 2 for the following discussions. Antenna Port The only external RF components needed for the receiver are the antenna and its matching components. Antennas presenting an impedance in the range of 35 to 72 ohms resistive can be satisfactorily matched to the RFIO pin with a series matching coil and a shunt matching/ESD protection coil. Other antenna impedances can be matched using two or three components. For some impedances, two inductors and a capacitor will be required. A DC path from RFIO to ground is required for ESD protection. Receiver Chain The output of the SAW filter drives amplifier RFA1. The output of RFA1 drives the SAW delay line, which has a nominal delay of 0.5 µs. The second amplifier, RFA2, provides 51 dB of gain below saturation. The output of RFA2 drives a full-wave detector with 19 dB of threshold gain. The onset of saturation in each section of RFA2 is detected and summed to provide a logarithmic response. This is added to the output of the full-wave detector to produce an overall detector response that is square law for low signal levels, and transitions into a log response for high signal levels. This combination provides excellent threshold sensitivity and more than 70 dB of The detector output drives a gyrator filter. The filter provides a three-pole, 0.05 degree equiripple low-pass response with excellent group delay flatness and minimal pulse ringing. The 3 dB bandwidth of the filter can be set from 4.5 kHz to 1.8 MHz with an external resistor. The filter is followed by a base-band amplifier which boosts the detected signal to the BBOUT pin. When the receiver RF amplifiers are operating at a 50%-50% duty cycle, the BBOUT signal changes about 10 mV/dB, with a peak-to-peak signal level of up to 685 mV. For lower duty cycles, the mV/dB slope and peak-to-peak signal level are proportionately less. The detected signal is riding on a 1.1 Vdc level that varies somewhat with supply voltage, temperature, etc. BBOUT is coupled to the CMPIN pin or to an external data recovery process (DSP, etc.) by a series capacitor. The correct value of the series capacitor depends on data rate, data run length, and other factors as discussed in the ASH Transceiver Designer’s Guide. When the receiver is placed in the power-down (sleep) mode, the output impedance of BBOUT becomes very high. This feature helps preserve the charge on the coupling capacitor to minimize data slicer stabilization time when the receiver switches out of the sleep mode. Data Slicers The CMPIN pin drives data slicer DS1, which convert the analog signal from BBOUT back into a digital stream. Data slicer DS1 is a capacitively-coupled comparator with provisions for an adjustable threshold. The threshold, or squelch, offsets the comparator’s slicing level from 0 to 90 mV, and is set with a resistor between the RREF and THLD1 pins. This threshold allows a trade-off between receiver sensitivity and output noise density in the no-signal condition. For best sensitivity, the threshold is set to 0. In this case, noise is output continuously when no signal is present. This, in turn, requires the circuit being driven by the RXDATA pin to be able to process noise (and signals) continuously. This can be a problem if RXDATA is driving a circuit that must “sleep” when data is not present to conserve power, or when it its necessary to minimize false interrupts to a multitasking processor. In this case, noise can be greatly reduced by increasing the threshold level, but at the expense of sensitivity. The best 3 dB bandwidth 5 for the low-pass filter is also affected by the threshold level setting of DS1. The bandwidth must be increased as the threshold is increased to minimize data pulse-width variations with signal amplitude. Receiver Pulse Generator and RF Amplifier Bias The receiver amplifier-sequence operation is controlled by the Pulse Generator & RF Amplifier Bias module, which in turn is controlled by the PRATE and PWIDTH input pins, and the Power Down (sleep) Control Signal from the Bias Control function. In the low data rate mode, the interval between the falling edge of one RFA1 ON pulse to the rising edge of the next RFA1 ON pulse tPRI is set by a resistor between the PRATE pin and ground. The interval can be adjusted between 0.1 and 5 µs. In the high data rate mode (selected at the PWIDTH pin) the receiver RF amplifiers operate at a nominal 50%-50% duty cycle. In this case, the start-to-start period tPRC for ON pulses to RFA1 are controlled by the PRATE resistor over a range of 0.1 to 1.1 µs. In the low data rate mode, the PWIDTH pin sets the width of the ON pulse tPW1 to RFA1 with a resistor to ground (the ON pulse width tPW2 to RFA2 is set at 1.1 times the pulse width to RFA1 in the low data rate mode). The ON pulse width tPW1 can be adjusted between 0.55 and 1 µs. However, when the PWIDTH pin is connected to Vcc through a 1 M resistor, the RF amplifiers operate at a nominal 50%-50% duty cycle, facilitating high data rate operation. In this case, the RF amplifiers are controlled by the PRATE resistor as described above. Both receiver RF amplifiers are turned off by the Power Down Control Signal, which is invoked in the sleep mode. Receiver Mode Control The receiver operating modes – receive and power-down (sleep), are controlled by the Bias Control function, and are selected with the CNTRL1 and CNTRL0 control pins. Setting CNTRL1 and CNTRL0 both high place the unit in the receive mode. Setting CNTRL1 and CNTRL0 both low place the unit in the power-down (sleep) mode. CNTRL1 and CNTRL0 are CMOS compatible inputs. These inputs must be held at a logic level; they cannot be left unconnected. Receiver Event Timing Receiver event timing is summarized in Table 1. Please refer to this table for the following discussions. Turn-On Timing The maximum time tPR required for the receive function to become operational at turn on is influenced by two factors. All receiver circuitry will be operational 5 ms after the supply voltage reaches 2.2 Vdc. The BBOUT-CMPIN coupling-capacitor is then DC stabilized in 3 time constants (3*tBBC). The total turn-on time to stable receiver operation for a 10 ms power supply rise time is: tPR = 15 ms + 3*tBBC Sleep and Wake-Up Timing The maximum transition time from the receive mode to the power-down (sleep) mode tRS is 10 µs after CNTRL1 and CNTRL0 are both low (1 µs fall time). The maximum transition time tSR from the sleep mode to the receive mode is 3*tBBC, where tBBC is the BBOUT-CMPIN coupling-capacitor time constant. When the operating temperature is limited to 60 oC, the time required to switch from sleep to receive is dramatically less for short sleep times, as less charge leaks away from the BBOUTCMPIN coupling capacitor. Pulse Generator Timing In the low data rate mode, the interval tPRI between the falling edge of an ON pulse to the first RF amplifier and the rising edge of the next ON pulse to the first RF amplifier is set by a resistor RPR between the PRATE pin and ground. The interval can be adjusted between 0.1 and 5 µs with a resistor in the range of 51 K to 2000 K. The value of the RPR is given by: RPR = 404* tPRI + 10.5, where tPRI is in µs, and RPR is in kilohms In the high data rate mode (selected at the PWIDTH pin) the receiver RF amplifiers operate at a nominal 50%-50% duty cycle. In this case, the period tPRC from the start of an ON pulse to the first RF amplifier to the start of the next ON pulse to the first RF amplifier is controlled by the PRATE resistor over a range of 0.1 to 1.1 µs using a resistor of 11 K to 220 K. In this case RPR is given by: RPR = 198* tPRC - 8.51, where tPRC is in µs and RPR is in kilohms In the low data rate mode, the PWIDTH pin sets the width of the ON pulse to the first RF amplifier tPW1 with a resistor RPW to ground (the ON pulse width to the second RF amplifier tPW2 is set at 1.1 times the pulse width to the first RF amplifier in the low data rate mode). The ON pulse width tPW1 can be adjusted between 0.55 and 1 µs with a resistor value in the range of 200 K to 390 K. The value of RPW is given by: RPW = 404* tPW1 - 18.6, where tPW1 is in µs and RPW is in kilohms However, when the PWIDTH pin is connected to Vcc through a 1 M resistor, the RF amplifiers operate at a nominal 50%-50% duty cycle, facilitating high data rate operation. In this case, the RF amplifiers are controlled by the PRATE resistor as described above. LPF Group Delay The low-pass filter group delay is a function of the filter 3 dB bandwidth, which is set by a resistor RLPF to ground at the LPFADJ pin. The minimum 3 dB bandwidth fLPF = 1445/RLPF, where fLPF is in kHz, and RLPF is in kilohms. The maximum group delay tFGD = 1750/fLPF = 1.21*RLPF, where tFGD is in µs, fLPF in kHz, and RLPF in kilohms. 6 Receiver Event Timing, 3.0 Vdc, -40 to +85 0C Symbol tPR tSR tRS tPRI tPW1 tPW2 tPRC tPWH tFGD fLPF tBBC Table 1 0.064*CBBO min tBBC in µs, CBBO in pF 1445/RLPF min fLPF in kHz, RLPF in kilohms 1750/fLPF max tFGD in µs, fLPF in kHz 0.05 to 0.55 µs range high data rate mode 0.1 to 1.1 µs range high data rate mode 1.1*tPW1 range low data rate mode 0.55 to 1 µs range low data rate mode 0.1 to 5 µs range low data rate mode 10 µs max 1µs CNTRL0/CNTROL1 fall times user selected mode user selected mode user selected mode user selected mode user selected mode user selected user selected user selected 3*tBBC max 1µs CNTRL0/CNTROL1 rise times 3*tBBC + 15 ms max 10 ms supply voltage rise time time until receiver operational time until receiver operational time until receiver is in power-down mode Time Min/Max Test Conditions Notes Event Turn On to Receive Sleep to RX RX to Sleep PRATE Interval PWIDTH RFA1 PWIDTH RFA2 PRATE Cycle PWIDTH High (RFA1 & RFA2) LPF Group Delay LPF 3 dB Bandwidth BBOUT-CMPIN Time Constant Pin Descriptions Pin 1 2 3 4 Name GND1 VCC1 RFA1 NC Description GND1 is the RF ground pin. GND2 and GND3 should be connected to GND1 by short, low-inductance traces. VCC1 is the positive supply voltage pin for the receiver base-band circuitry. VCC1 must be bypassed by an RF capacitor, which may be shared with VCC2. See the description of VCC2 (Pin 16) for additional information. RFA1 enables the high gain mode of the first RF amplifier. This pin is normally connected to VCC1. This pin should be left unconnected. BBOUT is the receiver base-band output pin. This pin drives the CMPIN pin through a coupling capacitor CBBO for internal data slicer operation. The time constant tBBC for this connection is: tBBC = 0.064*CBBO , where tBBC is in µs and CBBO is in pF A ±10% ceramic capacitor should be used between BBOUT and CMPIN. The time constant can vary between tBBC and 1.8*tBBC with variations in supply voltage, temperature, etc. The optimum time constant in a given circumstance will depend on the data rate, data run length, and other factors as discussed in the ASH Transceiver Designer’s Guide. A common criteria is to set the time constant for no more than a 20% voltage droop during SPMAX. For this case: CBBO = 70*SPMAX, where SPMAX is the maximum signal pulse width in µs and CBBO is in pF The output from this pin can also be used to drive an external data recovery process (DSP, etc.). The nominal output impedance of this pin is 1 K. When the receiver RF amplifiers are operating at a 50%-50% duty cycle, the BBOUT signal changes about 10 mV/dB, with a peak-to-peak signal level of up to 685 mV. For lower duty cycles, the mV/dB slope and peak-to-peak signal level are proportionately less. The signal at BBOUT is riding on a 1.1 Vdc value that varies somewhat with supply voltage and temperature, so it should be coupled through a capacitor to an external load. A load impedance of 50 K to 500 K in parallel with no more than 10 pF is recommended. When an external data recovery process is used with AGC, BBOUT must be coupled to the external data recovery process and CMPIN by separate series coupling capacitors. The AGC reset function is driven by the signal applied to CMPIN. When the receiver is in power-down (sleep) mode, the output impedance of this pin becomes very high, preserving the charge on the coupling capacitor. This pin is the input to the internal data slicers. It is driven from BBOUT through a coupling capacitor. The input impedance of this pin is 70 K to 100 K. RXDATA is the receiver data output pin. This pin will drive a 10 pF, 500 K parallel load. The peak current available from this pin increases with the receiver low-pass filter cutoff frequency. In the power-down (sleep) mode, this pin becomes high impedance. If required, a 1000 K pull-up or pull-down resistor can be used to establish a definite logic state when this pin is high impedance. If a pull-up resistor is used, the positive supply end should be connected to a voltage no greater than Vcc + 200 mV. This pin may be left unconnected or may be grounded. This pin is the receiver low-pass filter bandwidth adjust. The filter bandwidth is set by a resistor RLPF between this pin and ground. The resistor value can range from 330 K to 820 ohms, providing a filter 3 dB bandwidth fLPF from 4.5 kHz to 1.8 MHz. The resistor value is determined by: RLPF = 1445/ fLPF, where RLPF is in kilohms, and fLPF is in kHz A ±5% resistor should be used to set the filter bandwidth. This will provide a 3 dB filter bandwidth between fLPF and 1.3* fLPF with variations in supply voltage, temperature, etc. The filter provides a three-pole, 0.05 degree equiripple phase response. The peak drive current available from RXDATA increases in proportion to the filter bandwidth setting. GND2 is an IC ground pin. It should be connected to GND1 by a short, low inductance trace. RREF is the external reference resistor pin. A 100 K reference resistor is connected between this pin and ground. A ±1% resistor tolerance is recommended. It is important to keep the total capacitance between ground, Vcc and this node to less than 5 pF to maintain current source stability. If THLD1 and/or THDL2 are connected to RREF through resistor values less that 1.5 K, their node capacitance must be added to the RREF node capacitance and the total should not exceed 5 pF. This pin shouild be left unconnected. The THLD1 pin sets the threshold for the standard data slicer (DS1) through a resistor RTH1 to RREF. The threshold is increased by increasing the resistor value. Connecting this pin directly to RREF provides zero threshold. The acceptable range for the resistor is 0 to 100 K, providing a THLD1 range of 0 to 90 mV. The resistor value is given by: RTH1 = 1.11*V, where RTH1 is in kilohms and the threshold V is in mV A ±1% resistor tolerance is recommended for the THLD1 resistor. 5 BBOUT 6 CMPIN 7 RXDATA 8 NC 9 LPFADJ 10 GND2 11 RREF 12 NC 13 THLD1 8 Pin Name Description The interval between the falling edge of an ON pulse to the first RF amplifier and the rising edge of the next ON pulse to the first RF amplifier tPRI is set by a resistor RPR between this pin and ground. The interval tPRI can be adjusted between 0.1 and 5 µs with a resistor in the range of 51 K to 2000 K. The value of RPR is given by: RPR = 404* tPRI + 10.5, where tPRI is in µs, and RPR is in kilohms 14 PRATE A ±5% resistor value is recommended. When the PWIDTH pin is connected to Vcc through a 1 M resistor, the RF amplifiers operate at a nominal 50%-50% duty cycle, facilitating high data rate operation. In this case, the period tPRC from start-to-start of ON pulses to the first RF amplifier is controlled by the PRATE resistor over a range of 0.1 to 1.1 µs using a resistor of 11 K to 220 K. In this case the value of RPR is given by: RPR = 198* tPRC - 8.51, where tPRC is in µs and RPR is in kilohms A ±5% resistor value should also be used in this case. Please refer to the ASH Transceiver Designer’s Guide for additional amplifier duty cycle information. It is important to keep the total capacitance between ground, Vcc and this pin to less than 5 pF to maintain stability. The PWIDTH pin sets the width of the ON pulse to the first RF amplifier tPW1 with a resistor RPW to ground (the ON pulse width to the second RF amplifier tPW2 is set at 1.1 times the pulse width to the first RF amplifier). The ON pulse width tPW1 can be adjusted between 0.55 and 1 µs with a resistor value in the range of 200 K to 390 K. The value of RPW is given by: RPW = 404* tPW1 - 18.6, where tPW1 is in µs and RPW is in kilohms A ±5% resistor value is recommended. When this pin is connected to Vcc through a 1 M resistor, the RF amplifiers operate at a nominal 50%-50% duty cycle, facilitating high data rate operation. In this case, the RF amplifier ON times are controlled by the PRATE resistor as described above. It is important to keep the total capacitance between ground, Vcc and this node to less than 5 pF to maintain stability. When using the high data rate operation with the sleep mode, connect the 1 M resistor between this pin and CNTRL1 (Pin 17), so this pin is low in the sleep mode. VCC2 is the positive supply voltage pin for the receiver RF section. This pin must be bypassed with an RF capacitor, which may be shared with VCC1. VCC2 must also be bypassed with a 1 to 10 µF tantalum or electrolytic capacitor. CNTRL1 and CNTRL0 select the receiver modes. CNTRL1 and CNTRL0 both high place the unit in the receive mode. CNTRL1 and CNTRL0 both low place the unit in the power-down (sleep) mode. CNTRL1 is a high-impedance input (CMOS compatible). An input voltage of 0 to 300 mV is interpreted as a logic low. An input voltage of Vcc - 300 mV or greater is interpreted as a logic high. An input voltage greater than Vcc + 200 mV should not be applied to this pin. A logic high requires a maximum source current of 40 µA. Sleep mode requires a maximum sink current of 1 µA. This pin must be held at a logic level; it cannot be left unconnected. CNTRL0 is used with CNTRL1 to control the receiver modes. CNTRL0 is a high-impedance input (CMOS compatible). An input voltage of 0 to 300 mV is interpreted as a logic low. An input voltage of Vcc - 300 mV or greater is interpreted as a logic high. An input voltage greater than Vcc + 200 mV should not be applied to this pin. A logic high requires a maximum source current of 40 µA. Sleep mode requires a maximum sink current of 1 µA. This pin must be held at a logic level; it cannot be left unconnected. GND3 is an IC ground pin. It should be connected to GND1 by a short, low inductance trace. RFIO is the receiver RF input pin. This pin is connected directly to the SAW filter transducer. Antennas presenting an impedance in the range of 35 to 72 ohms resistive can be satisfactorily matched to this pin with a series matching coil and a shunt matching/ESD protection coil. Other antenna impedances can be matched using two or three components. For some impedances, two inductors and a capacitor will be required. A DC path from RFIO to ground is required for ESD protection. 15 PWIDTH 16 VCC2 17 CNTRL1 18 CNTRL0 19 GND3 20 RFIO 9 .1 7 2 5 .1 9 7 5 .2 1 2 5 .4 6 0 0 .2 3 7 5 .3 8 2 5 .3 5 7 5 .3 1 7 5 .2 7 7 5 .2 3 7 5 .1 9 7 5 .1 5 7 5 .1 1 7 5 .1 0 2 5 .0 7 7 5 .1 4 0 0 .0 0 0 .2 7 0 .4 1 0 0 .0 0 0 D im e n s io n s in in c h e s S M -2 0 L P C B P a d L a y o u t Note: Specifications subject to change without notice. file: rx5500w.vp, 2003.07.20 rev 10