TR3001

® · Designed for Short-Range Wireless Data Communications · Supports RF Data Transmission Rates Up to 115.2 kbps · 3 V, Low Current Operation plus Sleep Mode · Stable, Easy to Use, Low External Parts Count The TR3001 hybrid transceiver is ideal for short-range wireless data applications where robust operation, small size, low power consumption and low cost are required. The TR3001 employs RFM’s amplifier-sequenced hybrid (ASH) architecture to achieve this unique blend of characteristics. All critical RF functions are contained in the hybrid, simplifying and speeding design-in. The receiver section of the TR3001 is sensitive and stable. A wide dynamic range log detector, in combination with digital AGC and a compound data slicer, provide robust performance in the presence of on-channel interference or noise. Two stages of SAW filtering provide excellent receiver out-of-band rejection. The transmitter includes provisions for both on-off keyed (OOK) and amplitude-shift keyed (ASK) modulation. The transmitter employs SAW filtering to suppress output harmonics, facilitating compliance with FCC Part 15 and similar regulations. TR3001 315.00 MHz Hybrid Transceiver Absolute Maximum Ratings Rating Power Supply and All Input/Output Pins Non-Operating Case Temperature Soldering Temperature (10 seconds) Value -0.3 to +4.0 -50 to +100 250 Units V o o C C Electrical Characteristics (typical values given for 3.0 Vdc power supply, 25 oC) Characteristic Operating Frequency Modulation Type OOK Data Rate ASK Data Rate Receiver Performance, High Sensitivity Mode Sensitivity, 2.4 kbps, 10-3 BER, AM Test Method Sensitivity, 2.4 kbps, 10-3 BER, Pulse Test Method Current, 2.4 kbps (RPR = 330 K) Sensitivity, 19.2 kbps, 10-3 BER, AM Test Method Sensitivity, 19.2 kbps, 10-3 BER, Pulse Test Method Current, 19.2 kbps (RPR = 330 K) Sensitivity, 115.2 kbps, 10-3 BER, AM Test Method Sensitivity, 115.2 kbps, 10-3 BER, Pulse Test Method Current, 115.2 kbps Receiver Performance, Low Current Mode Sensitivity, 2.4 kbps, 10-3 BER, AM Test Method Sensitivity, 2.4 kbps, 10-3 BER, Pulse Test Method Current, 2.4 kbps (RPR = 1100 K) Receiver Out-of-Band Rejection, ±5% fO Receiver Ultimate Rejection R±5% RULT 1 1 2 3 3 -104 -98 1.8 80 100 dBm dBm mA dB dB 1 1 2 1 1 2 1 1 -109 -103 3.0 -105 -99 3.1 -101 -95 3.8 dBm dBm mA dBm dBm mA dBm dBm mA Sym fO Notes Minimum 314.80 OOK/ASK 30 115.2 kbps kbps Typical Maximum 315.20 Units MHz 1 Electrical Characteristics (typical values given for 3.0 Vdc power supply, 25 oC) Characteristic Transmitter Performance Peak RF Output Power, 250 µA TXMOD Current Peak Current, 250 µA TXMOD Current 2nd - 4th Harmonic Output 5th - 10th Harmonic Outputs Non-harmonic Spurious Outputs OOK Turn On/Turn Off Times ASK Output Rise/Fall Times Sleep Mode Current Power Supply Voltage Range Power Supply Voltage Ripple Ambient Operating Temperature Notes: 1. Typical sensitivity data is based on a 10-3 bit error rate (BER), using DC-balanced data. There are two test methods commonly used to measure OOK/ASK receiver sensitivity, the “100% AM” test method and the “Pulse” test method. Sensitivity data is given for both test methods. See Appendix 3.8 in the ASH Transceiver Designer’s Guide for the details of each test method, and for sensitivity curves for a 2.2 to 3.7 V supply voltage range at five operating temperatures. The application/test circuit and component values are shown on the next page and in the Designer’s Guide. 2. At low data rates it is possible to adjust the ASH pulse generator to trade-off some receiver sensitivity for lower operating current. Sensitivity data and receiver current are given at 2.4 kbps for both high sensitivity operation (RPR = 330 K) and low current operation (RPR = 1100 K). 3. Data is given with the ASH radio matched to a 50 ohm load. Matching component values are given on the next page. 4. See Table 1 on Page 8 for additional information on ASH radio event timing. TA -40 tON/tOFF tTR/tTF IS VCC 2.2 PO ITP 3 3 3 3 3 4 4 0.7 3.7 10 85 1.5 9.5 -50 -55 -50 12/6 1.1/1.1 dBm mA dBm dBm dBm µs µs µA Vdc mVP-P o Sym Notes Minimum Typical Maximum Units C S M -2 0 L P a c k a g e D r a w in g 0 .3 8 " (9 .6 5 ) 0 .0 8 " (2 .0 3 ) 0 .1 2 5 " (3 .2 0 ) A S H T r a n s c e iv e r P in O u t GND1 0 .0 2 " (0 .5 1 ) R F IO 1 20 19 2 3 4 5 6 7 8 9 10 11 RREF 18 17 16 15 14 13 12 GND3 CNTRL0 CNTRL1 VCC2 P W ID T H PRATE THLD 1 THLD 2 VCC1 AGCCAP 0 .4 3 " (1 0 .9 ) 0 .0 4 " (1 .0 2 ) PKDET BBOUT C M P IN 0 .0 7 5 " (1 .9 0 ) 0 .1 3 " (3 .3 0 ) RXDATA TXM OD LPFADJ GND2 2 A S H T r a n s c e iv e r A p p lic a tio n C ir c u it O O K C o n fig u r a tio n +3 VDC C RFB2 A S H T r a n s c e iv e r A p p lic a tio n C ir c u it A S K C o n fig u r a tio n +3 VDC C RFB2 C + DCB C + DCB T /R R PW R R PR TH1 TR M ode C o n tro l R TH2 R PW R R PR TH1 19 18 CNT R L0 17 CNT R L1 16 VCC 2 15 P W ID T H 14 P RATE 13 TH LD 1 12 TH LD 2 RREF GND2 LPF ADJ 9 19 18 CNT R L0 17 CNT R L1 16 VCC 2 15 P W ID T H 14 P RATE 13 TH LD 1 12 TH LD 2 RREF GND2 LPF ADJ 9 R TH2 L AT 20 GND 3 R F IO GND1 VCC 1 1 2 L 11 AT T O P V IE W AGC CAP 3 PK DET 4 BB OUT 5 BBO R 20 REF GND 3 R F IO GND1 VCC 1 1 2 T O P V IE W AGC CAP 3 RFB 11 R REF L ESD CMP IN 6 RX DATA 7 TX MOD 8 10 L ESD PK DET 4 BB OUT 5 CMP IN 6 RX DATA 7 TX MOD 8 10 L +3 VDC RFB R C RFB1 R R C LPF BBO TXM LPF L R C BBO LPF R TXM C M o d u la tio n In p u t D a ta O u tp u t RFB1 C +3 VDC C AGC C PKD M o d u la tio n In p u t D a ta O u tp u t Transceiver Set-Up, 3.0 Vdc, -40 to +85 0C Item Encoded Data Rate Minimum Signal Pulse Maximum Signal Pulse AGCCAP Capacitor PKDET Capacitor BBOUT Capacitor BBOUT Resistor LPFAUX Capacitor TXMOD Resistor LPFADJ Resistor RREF Resistor THLD2 Resistor THLD1 Resistor PRATE Resistor PWIDTH Resistor DC Bypass Capacitor RF Bypass Capacitor 1 RF Bypass Capacitor 2 RF Bypass Bead Series Tuning Inductor Shunt Tuning/ESD Inductor Symbol DRNOM SPMIN SPMAX CAGC CPKD CBBO RBBO CLPF RTXM RLPF RREF RTH2 RTH1 RPR RPW CDCB CRFB1 CRFB2 LRFB LAT LESD OOK 2.4 416.67 1666.68 0.1 12 0.0047 8.2 330 100 0 330 270 to GND 4.7 100 100 Fair-Rite 82 33 OOK 19.2 52.08 208.32 0.015 0 8.2 100 100 0 330 270 to GND 4.7 100 100 Fair-Rite 82 33 ASK 115.2 8.68 34.72 2200 0.001 0.0027 0 8.2 15 100 100 10 160 1000 to Vcc 4.7 100 100 Fair-Rite 82 33 Units kbps µs µs pF µF µF K µF K K K K K K K µF pF pF vendor nH nH Notes see pages 1 & 2 single bit 4 bits of same value ±10% ceramic ±10% ceramic ±10% ceramic ±5% ±5% ±5%, for 1.5 dBm output ±5% ±1% ±1%, for 6 dB below peak ±1%, typical values ±5% ±5% tantalum ±5% NPO ±5% NPO 2506031217YO or equivalent 50 ohm antenna 50 ohm antenna CAUTION: Electrostatic Sensitive Device. Observe precautions when handling. 3 ASH Transceiver Theory of Operation Introduction RFM’s amplifier-sequenced hybrid (ASH) transceiver is specifically designed for short-range wireless data communication applications. The transceiver provides robust operation, very small size, low power consumption and low implementation cost. All critical RF functions are contained in the hybrid, simplifying and speeding design-in. The ASH transceiver can be readily configured to support a wide range of data rates and protocol requirements. The transceiver features excellent suppression of transmitter harmonics and virtually no RF emissions when receiving, making it easy to certify to shortrange (unlicensed) radio regulations. Amplifier-Sequenced Receiver Operation The ASH transceiver’s unique feature set is made possible by its system architecture. The heart of the transceiver is the amplifiersequenced receiver section, which provides more than 100 dB of stable RF and detector gain without any special shielding or decoupling provisions. Stability is achieved by distributing the total RF gain over time. This is in contrast to a superheterodyne receiver, which achieves stability by distributing total RF gain over multiple frequencies. Figure 1 shows the basic block diagram and timing cycle for an amplifier-sequenced receiver. Note that the bias to RF amplifiers RFA1 and RFA2 are independently controlled by a pulse generator, and that the two amplifiers are coupled by a surface acoustic wave (SAW) delay line, which has a typical delay of 0.5 µs. An incoming RF signal is first filtered by a narrow-band SAW filter, and is then applied to RFA1. The pulse generator turns RFA1 ON for 0.5 µs. The amplified signal from RFA1 emerges from the SAW delay line at the input to RFA2. RFA1 is now switched OFF and RFA2 is switched ON for 0.55 µs, amplifying the RF signal further. The ON time for RFA2 is usually set at 1.1 times the ON time for RFA1, as the filtering effect of the SAW delay line stretches the signal pulse from RFA1 somewhat. As shown in the timing diagram, RFA1 and RFA2 are never on at the same time, assuring excellent receiver stability. Note that the narrow-band SAW filter eliminates sampling sideband responses outside of the receiver passband, and the SAW filter and delay line act together to provide very high receiver ultimate rejection. Amplifier-sequenced receiver operation has several interesting characteristics that can be exploited in system design. The RF amplifiers in an amplifier-sequenced receiver can be turned on and off almost instantly, allowing for very quick power-down (sleep) and wake-up times. Also, both RF amplifiers can be off between ON sequences to trade-off receiver noise figure for lower average current consumption. The effect on noise figure can be modeled as if RFA1 is on continuously, with an attenuator placed in front of it with a loss equivalent to 10*log10(RFA1 duty factor), where the duty factor is the average amount of time RFA1 is ON (up to 50%). Since an amplifier-sequenced receiver is inherently a sampling receiver, the overall cycle time between the start of one RFA1 ON sequence and A S H R e c e iv e r B lo c k D ia g r a m A n te n n a & T im in g C y c le SAW F ilte r RFA1 P1 SAW D e la y L in e RFA2 P2 D e te c to r & L o w -P a s s F ilte r D a ta O ut P u ls e G e n e ra to r R F In p u t tP P1 RFA1 O ut W1 R F D a ta P u ls e tP tP RC RI D e la y L in e O ut tP P2 W2 Figure 1 4 A S H T r a n s c e iv e r B lo c k D ia g r a m TX IN R TXM OD 8 CN CN TR L1 TR L0 TXM 17 18 Pow erD ow n C o n tro l M o d u la tio n & B ia s C o n tr o l VCC VCC GND GND GND RRE CMP 1: 2: 1: 2: 3: F: IN : P in P in P in P in P in P in P in 2 16 1 10 19 11 6 BBOUT A n te n n a R F IO 20 T u n in g T u n in g /E S D TXA2 TXA1 Log SAW C R F ilte r RFA1 SAW D e la y L in e RFA2 D e te c to r L o w -P a s s F ilte r LPFADJ 9 R LPF BB 5 C 6 BBO Peak D e te c to r PKDET 4 C PKD Ref DS2 d B B e lo w P e a k T h ld AND 7 RXDATA AG C Set G a in S e le c t P u ls e G e n e r a to r & R F A m p B ia s PRATE 14 R PR AGC Ref AGC C o n tro l AGCCAP 3 C A G C R eset 13 R TH1 DS1 T h ld T h r e s h o ld C o n tro l 15 R P W ID T H PW AGC TH LD1 11 R R REF TH2 12 TH LD2 Figure 2 the start of the next RFA1 ON sequence should be set to sample the narrowest RF data pulse at least 10 times. Otherwise, significant edge jitter will be added to the detected data pulse. ASH Transceiver Block Diagram Figure 2 is the general block diagram of the ASH transceiver. Please refer to Figure 2 for the following discussions. Antenna Port The only external RF components needed for the transceiver are the antenna and its matching components. Antennas presenting an impedance in the range of 35 to 72 ohms resistive can be satisfactorily matched to the RFIO pin with a series matching coil and a shunt matching/ESD protection coil. Other antenna impedances can be matched using two or three components. For some impedances, two inductors and a capacitor will be required. A DC path from RFIO to ground is required for ESD protection. Receiver Chain The output of the SAW filter drives amplifier RFA1. This amplifier includes provisions for detecting the onset of saturation (AGC Set), and for switching between 35 dB of gain and 5 dB of gain (Gain Select). AGC Set is an input to the AGC Control function, and Gain Select is the AGC Control function output. ON/OFF control to RFA1 (and RFA2) is generated by the Pulse Generator & RF Amp Bias function. The output of RFA1 drives the SAW delay line, which has a nominal delay of 0.5 µs. The second amplifier, RFA2, provides 51 dB of gain below saturation. The output of RFA2 drives a full-wave detector with 19 dB of threshold gain. The onset of saturation in each section of RFA2 is detected and summed to provide a logarithmic response. This is added to the output of the full-wave detector to produce an overall detector response that is square law for low signal levels, and transitions into a log response for high signal levels. This combination provides excellent threshold sensitivity and more than 70 dB of detector dynamic range. In combination with the 30 dB of AGC range in RFA1, more than 100 dB of receiver dynamic range is achieved. The detector output drives a gyrator filter. The filter provides a three-pole, 0.05 degree equiripple low-pass response with excellent group delay flatness and minimal pulse ringing. The 3 dB bandwidth of the filter can be set from 4.5 kHz to 1.8 MHz with an external resistor. The filter is followed by a base-band amplifier which boosts the detected signal to the BBOUT pin. When the receiver RF amplifiers are operating at a 50%-50% duty cycle, the BBOUT signal changes about 10 mV/dB, with a peak-to-peak signal level of up to 685 mV. For lower duty cycles, the mV/dB slope and peak-to-peak signal level are proportionately less. The detected signal is riding on a 1.1 Vdc level that varies somewhat with supply voltage, temperature, etc. BBOUT is coupled to the CMPIN pin or to an external data recovery process (DSP, etc.) by a series capacitor. The correct value of the series capacitor depends on data rate, data run length, and other factors as discussed in the ASH Transceiver Designer’s Guide. When an external data recovery process is used with AGC, BBOUT must be coupled to the external data recovery process and CMPIN by separate series coupling capacitors. The AGC reset function is driven by the signal applied to CMPIN. When the transceiver is placed in power-down (sleep) or in a transmit mode, the output impedance of BBOUT becomes very high. This feature helps preserve the charge on the coupling capacitor to minimize data slicer stabilization time when the transceiver switches back to the receive mode. Data Slicers The CMPIN pin drives two data slicers, which convert the analog signal from BBOUT back into a digital stream. The best data slicer choice depends on the system operating parameters. Data slicer DS1 is a capacitively-coupled comparator with provisions for an adjustable threshold. DS1 provides the best performance at low 5 signal-to-noise conditions. The threshold, or squelch, offsets the comparator’s slicing level from 0 to 90 mV, and is set with a resistor between the RREF and THLD1 pins. This threshold allows a tradeoff between receiver sensitivity and output noise density in the no-signal condition. For best sensitivity, the threshold is set to 0. In this case, noise is output continuously when no signal is present. This, in turn, requires the circuit being driven by the RXDATA pin to be able to process noise (and signals) continuously. This can be a problem if RXDATA is driving a circuit that must “sleep” when data is not present to conserve power, or when it its necessary to minimize false interrupts to a multitasking processor. In this case, noise can be greatly reduced by increasing the threshold level, but at the expense of sensitivity. The best 3 dB bandwidth for the low-pass filter is also affected by the threshold level setting of DS1. The bandwidth must be increased as the threshold is increased to minimize data pulse-width variations with signal amplitude. Data slicer DS2 can overcome this compromise once the signal level is high enough to enable its operation. DS2 is a “dB-belowpeak” slicer. The peak detector charges rapidly to the peak value of each data pulse, and decays slowly in between data pulses (1:1000 ratio). The slicer trip point can be set from 0 to 120 mV below this peak value with a resistor between RREF and THLD2. A threshold of 60 mV is the most common setting, which equates to “6 dB below peak” when RFA1 and RFA2 are running a 50%-50% duty cycle. Slicing at the “6 dB-below-peak” point reduces the signal amplitude to data pulse-width variation, allowing a lower 3 dB filter bandwidth to be used for improved sensitivity. DS2 is best for ASK modulation where the transmitted waveform has been shaped to minimize signal bandwidth. However, DS2 is subject to being temporarily “blinded” by strong noise pulses, which can cause burst data errors. Note that DS1 is active when DS2 is used, as RXDATA is the logical AND of the DS1 and DS2 outputs. DS2 can be disabled by leaving THLD2 disconnected. A non-zero DS1 threshold is required for proper AGC operation. AGC Control The output of the Peak Detector also provides an AGC Reset signal to the AGC Control function through the AGC comparator. The purpose of the AGC function is to extend the dynamic range of the receiver, so that two transceivers can operate close together when running ASK and/or high data rate modulation. The onset of saturation in the output stage of RFA1 is detected and generates the AGC Set signal to the AGC Control function. The AGC Control function then selects the 5 dB gain mode for RFA1. The AGC Comparator will send a reset signal when the Peak Detector output (multiplied by 0.8) falls below the threshold voltage for DS1. A capacitor at the AGCCAP pin avoids AGC “chattering” during the time it takes for the signal to propagate through the low-pass filter and charge the peak detector. The AGC capacitor also allows the hold-in time to be set longer than the peak detector decay time to avoid AGC chattering during runs of “0” bits in the received data stream. Note that AGC operation requires the peak detector to be functioning, even if DS2 is not being used. AGC operation can be defeated by connecting the AGCCAP pin to Vcc. The AGC can be latched ON once engaged by connecting a 150 kilohm resistor between the AGCCAP pin and ground in lieu of a capacitor. Receiver Pulse Generator and RF Amplifier Bias The receiver amplifier-sequence operation is controlled by the Pulse Generator & RF Amplifier Bias module, which in turn is controlled by the PRATE and PWIDTH input pins, and the Power Down (sleep) Control Signal from the Modulation & Bias Control function. In the low data rate mode, the interval between the falling edge of one RFA1 ON pulse to the rising edge of the next RFA1 ON pulse tPRI is set by a resistor between the PRATE pin and ground. The interval can be adjusted between 0.1 and 5 µs. In the high data rate mode (selected at the PWIDTH pin) the receiver RF amplifiers operate at a nominal 50%-50% duty cycle. In this case, the start-to-start period tPRC for ON pulses to RFA1 are controlled by the PRATE resistor over a range of 0.1 to 1.1 µs. In the low data rate mode, the PWIDTH pin sets the width of the ON pulse tPW1 to RFA1 with a resistor to ground (the ON pulse width tPW2 to RFA2 is set at 1.1 times the pulse width to RFA1 in the low data rate mode). The ON pulse width tPW1 can be adjusted between 0.55 and 1 µs. However, when the PWIDTH pin is connected to Vcc through a 1 M resistor, the RF amplifiers operate at a nominal 50%-50% duty cycle, facilitating high data rate operation. In this case, the RF amplifiers are controlled by the PRATE resistor as described above. Both receiver RF amplifiers are turned off by the Power Down Control Signal, which is invoked in the sleep and transmit modes. Transmitter Chain The transmitter chain consists of a SAW delay line oscillator followed by a modulated buffer amplifier. The SAW filter suppresses transmitter harmonics to the antenna. Note that the same SAW devices used in the amplifier-sequenced receiver are reused in the transmit modes. Transmitter operation supports two modulation formats, on-off keyed (OOK) modulation, and amplitude-shift keyed (ASK) modulation. When OOK modulation is chosen, the transmitter output turns completely off between “1” data pulses. When ASK modulation is chosen, a “1” pulse is represented by a higher transmitted power level, and a “0” is represented by a lower transmitted power level. OOK modulation provides compatibility with first-generation ASH technology, and provides for power conservation. ASK modulation must be used for high data rates (data pulses less than 30 µs). ASK modulation also reduces the effects of some types of interference and allows the transmitted pulses to be shaped to control modulation bandwidth. The modulation format is chosen by the state of the CNTRL0 and the CNTRL1 mode control pins, as discussed below. When either modulation format is chosen, the receiver RF amplifiers are turned off. In the OOK mode, the delay line oscillator amplifier TXA1 and buffer amplifier TXA2 are turned off when the voltage to the TXMOD input falls below 220 mV. In the OOK mode, the data rate is limited by the turn-on and turn-off times of the delay line oscillator, which are 12 and 6 µs respectively. In the ASK mode TXA1 is biased ON continuously, and the output of TXA2 is modulated by the TXMOD input current. Minimum output power occurs in the ASK mode when the modulation driver sinks about 10 µA of current from the TXMOD pin. The transmitter RF output power is proportional to the input current to the TXMOD pin. A series resistor is used to adjust the peak transmitter output power. 1.5 dBm output power requires about 250 µA of input current. Transceiver Mode Control The four transceiver operating modes – receive, transmit ASK, transmit OOK, and power-down (sleep), are controlled by the Modulation & Bias Control function, and are selected with the CNTRL1 6 and CNTRL0 control pins. Setting CNTRL1 and CNTRL0 both high place the unit in the receive mode. Setting CNTRL1 high and CNTRL0 low place the unit in the ASK transmit mode. Setting CNTRL1 low and CNTRL0 high place the unit in the OOK transmit mode. Setting CNTRL1 and CNTRL0 both low place the unit in the power-down (sleep) mode. Note that the resistor driving TXMOD must be low in the receive and power-down modes. The PWIDTH resistor must also be low in the power down mode to minimize current. CNTRL1 and CNTRL0 are CMOS compatible inputs. These inputs must be held at a logic level; they cannot be left unconnected. Transceiver Event Timing Transceiver event timing is summarized in Table 1. Please refer to this table for the following discussions. Turn-On Timing The maximum time tPR required for the receive function to become operational at turn on is influenced by two factors. All receiver circuitry will be operational 5 ms after the supply voltage reaches 2.2 Vdc. The BBOUT-CMPIN coupling-capacitor is then DC stabilized in 3 time constants (3*tBBC). The total turn-on time to stable receiver operation for a 10 ms power supply rise time is: tPR = 15 ms + 3*tBBC The maximum time required for either the OOK or ASK transmitter mode to become operational is 5 ms after the supply voltage reaches 2.2 Vdc. Receive-to-Transmit Timing After turn on, the maximum time required to switch from receive to either transmit mode is 12 µs. Most of this time is due to the start-up of the transmitter oscillator. Transmit-to-Receive Timing The maximum time required to switch from the OOK or ASK transmit mode to the receive mode is 3*tBBC, where tBBC is the BBOUTCMPIN coupling-capacitor time constant. When the operating temperature is limited to 60 oC, the time required to switch from transmit to receive is dramatically less for short transmissions, as less charge leaks away from the BBOUT-CMPIN coupling capacitor. Sleep and Wake-Up Timing The maximum transition time from the receive mode to the power-down (sleep) mode tRS is 10 µs after CNTRL1 and CNTRL0 are both low (1 µs fall time). The maximum transition time from either transmit mode to the sleep mode (tTOS and tTAS) is 10 µs after CNTRL1 and CNTRL0 are both low (1 µs fall time). The maximum transition time tSR from the sleep mode to the receive mode is 3*tBBC, where tBBC is the BBOUT-CMPIN coupling-capacitor time constant. When the operating temperature is limited to 60 oC, the time required to switch from sleep to receive is dramatically less for short sleep times, as less charge leaks away from the BBOUTCMPIN coupling capacitor. The maximum time required to switch from the sleep mode to either transmit mode (tSTO and tSTA) is 16 µs. Most of this time is due to the start-up of the transmitter oscillator. AGC Timing The maximum AGC engage time tAGC is 5 µs after the reception of a -30 dBm RF signal with a 1 µs envelope rise time. The minimum AGC hold-in time is set by the value of the capacitor at the AGCCAP pin. The hold-in time tAGH = CAGC/19.1, where tAGH is in µs and CAGC is in pF. Peak Detector Timing The Peak Detector attack time constant is set by the value of the capacitor at the PKDET pin. The attack time tPKA = CPKD/4167, where tPKA is in µs and CPKD is in pF. The Peak Detector decay time constant tPKD = 1000*tPKA. Pulse Generator Timing In the low data rate mode, the interval tPRI between the falling edge of an ON pulse to the first RF amplifier and the rising edge of the next ON pulse to the first RF amplifier is set by a resistor RPR between the PRATE pin and ground. The interval can be adjusted between 0.1 and 5 µs with a resistor in the range of 51 K to 2000 K. The value of the RPR is given by: RPR = 404* tPRI + 10.5, where tPRI is in µs, and RPR is in kilohms In the high data rate mode (selected at the PWIDTH pin) the receiver RF amplifiers operate at a nominal 50%-50% duty cycle. In this case, the period tPRC from the start of an ON pulse to the first RF amplifier to the start of the next ON pulse to the first RF amplifier is controlled by the PRATE resistor over a range of 0.1 to 1.1 µs using a resistor of 11 K to 220 K. In this case RPR is given by: RPR = 198* tPRC - 8.51, where tPRC is in µs and RPR is in kilohms In the low data rate mode, the PWIDTH pin sets the width of the ON pulse to the first RF amplifier tPW1 with a resistor RPW to ground (the ON pulse width to the second RF amplifier tPW2 is set at 1.1 times the pulse width to the first RF amplifier in the low data rate mode). The ON pulse width tPW1 can be adjusted between 0.55 and 1 µs with a resistor value in the range of 200 K to 390 K. The value of RPW is given by: RPW = 404* tPW1 - 18.6, where tPW1 is in µs and RPW is in kilohms However, when the PWIDTH pin is connected to Vcc through a 1 M resistor, the RF amplifiers operate at a nominal 50%-50% duty cycle, facilitating high data rate operation. In this case, the RF amplifiers are controlled by the PRATE resistor as described above. LPF Group Delay The low-pass filter group delay is a function of the filter 3 dB bandwidth, which is set by a resistor RLPF to ground at the LPFADJ pin. The minimum 3 dB bandwidth fLPF = 1445/RLPF, where fLPF is in kHz, and RLPF is in kilohms. The maximum group delay tFGD = 1750/fLPF = 1.21*RLPF, where tFGD is in µs, fLPF in kHz, and RLPF in kilohms. 7 Transceiver Event Timing, 3.0 Vdc, -40 to +85 0C Symbol tPR tPTO tPTA tRTO tRTA tTOR tTAR tSR tSTO tSTA tRS tTOS tTAS tAGC tAGH tPKA tPKD tPRI tPW1 tPW2 tPRC tPWH tFGD fLPF tBBC 0.064*CBBO min 1445/RLPF min 1750/fLPF max 0.05 to 0.55 µs range 0.1 to 1.1 µs range 1.1*tPW1 range 0.55 to 1 µs range 0.1 to 5 µs range 1000*tPKA min CPKD/4167 min tPKD and tPKA in µs low data rate mode low data rate mode low data rate mode high data rate mode high data rate mode tFGD in µs, fLPF in kHz fLPF in kHz, RLPF in kilohms tBBC in µs, CBBO in pF CAGC/19.1 min CAGC in pF, tAGH in µs CPKD in pF, tPKA in µs 5 µs max 1 µs rise time, -30 dBm signal 10 µs max 1 µs CNTRL1 fall time 10 µs max 1 µs CNTRL0 fall time 10 µs max 1µs CNTRL0/CNTROL1 fall times 16 µs max 1 µs CNTRL1 rise time 16 µs max 1 µs CNTRL0 rise time 3*tBBC max 1µs CNTRL0/CNTROL1 rise times 3*tBBC max 1 µs CNTRL0 rise time 3*tBBC max 1 µs CNTRL1 rise time 12 µs max 1 µs CNTRL0 fall time 12 µs max 1 µs CNTRL1 fall time 15 ms max 10 ms supply voltage rise time 15 ms max 10 ms supply voltage rise time 3*tBBC + 15 ms max 10 ms supply voltage rise time time until receiver operational time until TXMOD can modulate transmitter time until TXMOD can modulate transmitter TXMOD low 1 µs before CNTRL1 falls TXMOD low 1 µs before CNTRL0 falls time until receiver operational time until receiver operational time until receiver operational time until TXMOD can modulate transmitter time until TXMOD can modulate transmitter time until transceiver is in power-down mode time until transceiver is in power-down mode time until transceiver is in power-down mode RFA1 switches from 35 to 5 dB gain user selected; longer than tPKD user selected slaved to attack time user selected mode user selected mode user selected mode user selected mode user selected mode user selected user selected user selected Time Min/Max Test Conditions Notes Event Turn On to Receive Turn On to TXOOK Turn On to TXASK RX to TXOOK RX to TXASK TXOOK to RX TXASK to RX Sleep to RX Sleep to TXOOK Sleep to TXASK RX to Sleep TXOOK to Sleep TXASK to Sleep AGC Engage AGC Hold-In PKDET Attack Time Constant PKDET Decay Time Constant PRATE Interval PWIDTH RFA1 PWIDTH RFA2 PRATE Cycle PWIDTH High (RFA1 & RFA2) LPF Group Delay LPF 3 dB Bandwidth BBOUT-CMPIN Time Constant Table 1 Pin Descriptions Pin 1 2 Name GND1 VCC1 Description GND1 is the RF ground pin. GND2 and GND3 should be connected to GND1 by short, low-inductance traces. VCC1 is the positive supply voltage pin for the transmitter output amplifier and the receiver base-band circuitry. VCC1 is usually connected to the positive supply through a ferrite RF decoupling bead, which is bypassed by an RF capacitor on the supply side. See the ASH Transceiver Designer’s Guide for additional information. This pin controls the AGC reset operation. A capacitor between this pin and ground sets the minimum time the AGC will hold-in once it is engaged. The hold-in time is set to avoid AGC chattering. For a given hold-in time tAGH, the capacitor value CAGC is: CAGC = 19.1* tAGH, where tAGH is in µs and CAGC is in pF A ±10% ceramic capacitor should be used at this pin. The value of CAGC given above provides a hold-in time between tAGH and 2.65* tAGH, depending on operating voltage, temperature, etc. The hold-in time is chosen to allow the AGC to ride through the longest run of zero bits that can occur in a received data stream. The AGC hold-in time can be greater than the peak detector decay time, as discussed below. However, the AGC hold-in time should not be set too long, or the receiver will be slow in returning to full sensitivity once the AGC is engaged by noise or interference. The use of AGC is optional when using OOK modulation with data pulses of at least 30 µs. AGC operation can be defeated by connecting this pin to Vcc. Active or latched AGC operation is required for ASK modulation and/or for data pulses of less than 30 µs. The AGC can be latched on once engaged by connecting a 150 K resistor between this pin and ground, instead of a capacitor. AGC operation depends on a functioning peak detector, as discussed below. The AGC capacitor is discharged in the receiver power-down (sleep) mode and in the transmit modes. This pin controls the peak detector operation. A capacitor between this pin and ground sets the peak detector attack and decay times, which have a fixed 1:1000 ratio. For most applications, these time constants should be coordinated with the base-band time constant. For a given base-band capacitor CBBO, the capacitor value CPKD is: CPKD = 0.33* CBBO , where CBBO and CPKD are in pF 4 PKDET A ±10% ceramic capacitor should be used at this pin. This time constant will vary between tPKA and 1.5* tPKA with variations in supply voltage, temperature, etc. The capacitor is driven from a 200 ohm “attack” source, and decays through a 200 K load. The peak detector is used to drive the “dB-below-peak” data slicer and the AGC release function. The AGC hold-in time can be extended beyond the peak detector decay time with the AGC capacitor, as discussed above. Where low data rates and OOK modulation are used, the “dB-below-peak” data slicer and the AGC are optional. In this case, the PKDET pin and the THLD2 pin can be left unconnected, and the AGC pin can be connected to Vcc to reduce the number of external components needed. The peak detector capacitor is discharged in the receiver power-down (sleep) mode and in the transmit modes. BBOUT is the receiver base-band output pin. This pin drives the CMPIN pin through a coupling capacitor CBBO for internal data slicer operation. The time constant tBBC for this connection is: tBBC = 0.064*CBBO , where tBBC is in µs and CBBO is in pF A ±10% ceramic capacitor should be used between BBOUT and CMPIN. The time constant can vary between tBBC and 1.8*tBBC with variations in supply voltage, temperature, etc. The optimum time constant in a given circumstance will depend on the data rate, data run length, and other factors as discussed in the ASH Transceiver Designer’s Guide. A common criteria is to set the time constant for no more than a 20% voltage droop during SPMAX. For this case: CBBO = 70*SPMAX, where SPMAX is the maximum signal pulse width in µs and CBBO is in pF The output from this pin can also be used to drive an external data recovery process (DSP, etc.). The nominal output impedance of this pin is 1 K. When the receiver RF amplifiers are operating at a 50%-50% duty cycle, the BBOUT signal changes about 10 mV/dB, with a peak-to-peak signal level of up to 685 mV. For lower duty cycles, the mV/dB slope and peak-to-peak signal level are proportionately less. The signal at BBOUT is riding on a 1.1 Vdc value that varies somewhat with supply voltage and temperature, so it should be coupled through a capacitor to an external load. A load impedance of 50 K to 500 K in parallel with no more than 10 pF is recommended. When an external data recovery process is used with AGC, BBOUT must be coupled to the external data recovery process and CMPIN by separate series coupling capacitors. The AGC reset function is driven by the signal applied to CMPIN. When the transceiver is in power-down (sleep) or in a transmit mode, the output impedance of this pin becomes very high, preserving the charge on the coupling capacitor. This pin is the input to the internal data slicers. It is driven from BBOUT through a coupling capacitor. The input impedance of this pin is 70 K to 100 K. RXDATA is the receiver data output pin. This pin will drive a 10 pF, 500 K parallel load. The peak current available from this pin increases with the receiver low-pass filter cutoff frequency. In the power-down (sleep) or transmit modes, this pin becomes high impedance. If required, a 1000 K pull-up or pull-down resistor can be used to establish a definite logic state when this pin is high impedance. If a pull-up resistor is used, the positive supply end should be connected to a voltage no greater than Vcc + 200 mV. 3 AGCCAP 5 BBOUT 6 CMPIN 7 RXDATA 9 Pin Name Description The transmitter RF output voltage is proportional to the input current to this pin. A series resistor is used to adjust the peak transmitter output voltage. 1.5 dBm output power requires about 250 µA of input current. In the ASK mode, minimum output power occurs when the modulation driver sinks about 10 µA of current from this pin. In the OOK mode, input signals less than 220 mV completely turn the transmitter oscillator off. Internally, this pin appears to be a diode in series with a small resistor. Peak transmitter output power PO for a 3 Vdc supply voltage is approximately: PO = 24*(ITXM)2, where PO is in mW, and the peak modulation current ITXM is in mA A ±5% resistor value is recommended. In the OOK mode, this pin is usually driven with a logic-level data input (unshaped data pulses). OOK modulation is practical for data pulses of 30 µs or longer. In the ASK mode, this pin accepts analog modulation (shaped or unshaped data pulses). ASK modulation is practical for data pulses 8.7 µs or longer. The resistor driving this pin must be low in the receive and power-down (sleep) modes. Please refer to the ASH Transceiver Designer’s Guide for additional information on modulation techniques. This pin is the receiver low-pass filter bandwidth adjust. The filter bandwidth is set by a resistor RLPF between this pin and ground. The resistor value can range from 330 K to 820 ohms, providing a filter 3 dB bandwidth fLPF from 4.5 kHz to 1.8 MHz. The resistor value is determined by: RLPF = 1445/ fLPF, where RLPF is in kilohms, and fLPF is in kHz A ±5% resistor should be used to set the filter bandwidth. This will provide a 3 dB filter bandwidth between fLPF and 1.3* fLPF with variations in supply voltage, temperature, etc. The filter provides a three-pole, 0.05 degree equiripple phase response. The peak drive current available from RXDATA increases in proportion to the filter bandwidth setting. GND2 is an IC ground pin. It should be connected to GND1 by a short, low inductance trace. RREF is the external reference resistor pin. A 100 K reference resistor is connected between this pin and ground. A ±1% resistor tolerance is recommended. It is important to keep the total capacitance between ground, Vcc and this node to less than 5 pF to maintain current source stability. If THLD1 and/or THDL2 are connected to RREF through resistor values less that 1.5 K, their node capacitance must be added to the RREF node capacitance and the total should not exceed 5 pF. THLD2 is the “dB-below-peak” data slicer (DS2) threshold adjust pin. The threshold is set by a 0 to 200 K resistor RTH2 between this pin and RREF. Increasing the value of the resistor decreases the threshold below the peak detector value (increases difference) from 0 to 120 mV. For most applications, this threshold should be set at 6 dB below peak, or 60 mV for a 50%-50% RF amplifier duty cycle. The value of the THLD2 resistor is given by: RTH2 = 1.67*V, where RTH2 is in kilohms and the threshold V is in mV A ±1% resistor tolerance is recommended for the THLD2 resistor. Leaving the THLD2 pin open disables the dB-below-peak data slicer operation. The THLD1 pin sets the threshold for the standard data slicer (DS1) through a resistor RTH1 to RREF. The threshold is increased by increasing the resistor value. Connecting this pin directly to RREF provides zero threshold. The value of the resistor depends on whether THLD2 is used. For the case that THLD2 is not used, the acceptable range for the resistor is 0 to 100 K, providing a THLD1 range of 0 to 90 mV. The resistor value is given by: RTH1 = 1.11*V, where RTH1 is in kilohms and the threshold V is in mV For the case that THLD2 is used, the acceptable range for the THLD1 resistor is 0 to 200 K, again providing a THLD1 range of 0 to 90 mV. The resistor value is given by: RTH1 = 2.22*V, where RTH1 is in kilohms and the threshold V is in mV A ±1% resistor tolerance is recommended for the THLD1 resistor. Note that a non-zero DS1 threshold is required for proper AGC operation. The interval between the falling edge of an ON pulse to the first RF amplifier and the rising edge of the next ON pulse to the first RF amplifier tPRI is set by a resistor RPR between this pin and ground. The interval tPRI can be adjusted between 0.1 and 5 µs with a resistor in the range of 51 K to 2000 K. The value of RPR is given by: RPR = 404* tPRI + 10.5, where tPRI is in µs, and RPR is in kilohms 8 TXMOD 9 LPFADJ 10 GND2 11 RREF 12 THLD2 13 THLD1 14 PRATE A ±5% resistor value is recommended. When the PWIDTH pin is connected to Vcc through a 1 M resistor, the RF amplifiers operate at a nominal 50%-50% duty cycle, facilitating high data rate operation. In this case, the period tPRC from start-to-start of ON pulses to the first RF amplifier is controlled by the PRATE resistor over a range of 0.1 to 1.1 µs using a resistor of 11 K to 220 K. In this case the value of RPR is given by: RPR = 198* tPRC - 8.51, where tPRC is in µs and RPR is in kilohms A ±5% resistor value should also be used in this case. Please refer to the ASH Transceiver Designer’s Guide for additional amplifier duty cycle information. It is important to keep the total capacitance between ground, Vcc and this pin to less than 5 pF to maintain stability. 10 Pin Name Description The PWIDTH pin sets the width of the ON pulse to the first RF amplifier tPW1 with a resistor RPW to ground (the ON pulse width to the second RF amplifier tPW2 is set at 1.1 times the pulse width to the first RF amplifier). The ON pulse width tPW1 can be adjusted between 0.55 and 1 µs with a resistor value in the range of 200 K to 390 K. The value of RPW is given by: RPW = 404* tPW1 - 18.6, where tPW1 is in µs and RPW is in kilohms A ±5% resistor value is recommended. When this pin is connected to Vcc through a 1 M resistor, the RF amplifiers operate at a nominal 50%-50% duty cycle, facilitating high data rate operation. In this case, the RF amplifier ON times are controlled by the PRATE resistor as described above. It is important to keep the total capacitance between ground, Vcc and this node to less than 5 pF to maintain stability. When using the high data rate operation with the sleep mode, connect the 1 M resistor between this pin and CNTRL1 (Pin 17), so this pin is low in the sleep mode. VCC2 is the positive supply voltage pin for the receiver RF section and transmitter oscillator. Pin 16 must be bypassed with an RF capacitor, and must also be bypassed with a 1 to 10 µF tantalum or electrolytic capacitor. See the ASH Transceiver Designer’s Guide for additional information. CNTRL1 and CNTRL0 select the receive and transmit modes. CNTRL1 and CNTRL0 both high place the unit in the receive mode. CNTRL1 high and CNTRL0 low place the unit in the ASK transmit mode. CNTRL1 low and CNTRL0 high place the unit in the OOK transmit mode. CNTRL1 and CNTRL0 both low place the unit in the power-down (sleep) mode. CNTRL1 is a high-impedance input (CMOS compatible). An input voltage of 0 to 300 mV is interpreted as a logic low. An input voltage of Vcc - 300 mV or greater is interpreted as a logic high. An input voltage greater than Vcc + 200 mV should not be applied to this pin. A logic high requires a maximum source current of 40 µA. A logic low requires a maximum sink current of 25 µA (1 µA in sleep mode). This pin must be held at a logic level; it cannot be left unconnected. CNTRL0 is used with CNTRL1 to control the receive and transmit modes of the transceiver. CNTRL0 is a high-impedance input (CMOS compatible). An input voltage of 0 to 300 mV is interpreted as a logic low. An input voltage of Vcc - 300 mV or greater is interpreted as a logic high. An input voltage greater than Vcc + 200 mV should not be applied to this pin. A logic high requires a maximum source current of 40 µA. A logic low requires a maximum sink current of 25 µA (1 µA in sleep mode). This pin must be held at a logic level; it cannot be left unconnected. GND3 is an IC ground pin. It should be connected to GND1 by a short, low inductance trace. RFIO is the RF input/output pin. This pin is connected directly to the SAW filter transducer. Antennas presenting an impedance in the range of 35 to 72 ohms resistive can be satisfactorily matched to this pin with a series matching coil and a shunt matching/ESD protection coil. Other antenna impedances can be matched using two or three components. For some impedances, two inductors and a capacitor will be required. A DC path from RFIO to ground is required for ESD protection. 15 PWIDTH 16 VCC2 17 CNTRL1 18 CNTRL0 19 GND3 20 RFIO .1 7 2 5 .1 9 7 5 .2 1 2 5 .4 6 0 0 .2 3 7 5 .3 8 2 5 .3 5 7 5 .3 1 7 5 .2 7 7 5 .2 3 7 5 .1 9 7 5 .1 5 7 5 .1 1 7 5 .1 0 2 5 .0 7 7 5 .1 4 0 0 .0 0 0 .2 7 0 .4 1 0 0 .0 0 0 D im e n s io n s in in c h e s S M -2 0 L P C B P a d L a y o u t 11 R F O u tp u t P o w e r v s IT 2 .4 0 2 .1 0 1 .8 0 1 .5 0 1 .2 0 0 .9 0 0 .6 0 0 .3 0 XM 3V O u tp u t P o w e r in m W 0 0 .0 4 0 .0 8 0 .1 2 0 .1 6 IT XM 0 .2 0 in m A 0 .2 4 0 .2 8 0 .3 2 0 .3 6 0 .4 0 V 1 .0 0 0 .9 8 0 .9 6 0 .9 4 in V TXM v s IT XM V TXM 0 .9 2 0 .9 0 0 .8 8 0 .8 6 0 0 .0 4 0 .0 8 0 .1 2 0 .1 6 IT XM 0 .2 0 in m A 0 .2 4 0 .2 8 0 .3 2 0 .3 6 0 .4 0 Note: Specifications subject to change without notice. file: tr3001v.vp, 2003.07.17 rev 12