ML6652
10/100Mbps Ethernet Fiber and Copper
Media Converter with Auto-Negotiation
GENERAL DESCRIPTION
FEATURES
The ML6652 is a low cost multi-function / multi-standard
single chip Media Converter that provides 10Mbps and
100Mbps signal conversion between twisted pair and fiber
optic Ethernet technologies. The device supports
conversion between:
• Complete implementation of fiber optic and twisted pair
media interface
• Supports ISO/IEC 8802.3, IEEE 802.3 and TIA/EIA-785
Industry Standards, including full Auto-Negotiation for
twisted pair and fiber optic media
• 850nm, 1300nm miniature fiber optic components and
PMD modules
10BASE-T and 10BASE-FL
100BASE-TX and 100BASE-FX/SX
100BASE-FX and 100BASE-SX
FLP Bursts and FLNP Bursts
• Supports 1:1 receiver/transmitter transformer ratio for
twisted pair
The device supports 10Mbps and 100Mbps operating data
rates with Auto-Negotiation using 850nm or 1300nm
optics. One or both of the fiber optic and twisted pair
interfaces can be interfaced to industry standard miniature
fiber optic components or Physical Media Dependent
(PMD) modules using Positive Emitter Coupled Logic/Low
Voltage Positive Emitter Coupled Logic (PECL/LVPECL)
compatible modes. Support of other wavelengths is
possible using the PECL/LVPECL interface.
• Low latency
• Integrated voltage and current references
• Integrated twisted pair output wave shaping eliminates
external filtering
• Integrated twisted pair 10BASE-T input filter and
100BASE-TX equalizer with baseline wander correction
circuit
• Serial Management Interface
• Full and Half Duplex with Auto-Negotiation
• Integrated LED Driver
APPLICATIONS
• Integrated Data Quantizer
• Single/Multi Port 10/100 Auto-Negotiating Media
Converters
• Small 44-Pin TQFP and LPCC/QFN
• Single/Multi Port 100BASE-FX/SX to100BASE-TX
Media Converters
• Low 3.3V power supply
• Integrated Link Integrity Warning (LIW)
• Single/Multi Port 10BASE-FL to 10BASE-T Media
Converters
• Single/Multi Mode Fiber Converters
• Fiber Optic Front-End for Network Interface Cards
(NICs), Repeaters, Bridges, Hubs and Switches
• Fiber-To-The-Desk/Building/Factory Floor as well as
Home Connectivity Gateway/Demarcation Products
• Redundant Link Converters and Wavelength Converters
Final Datasheet
DS110415
ML6652
TABLE OF CONTENTS
General Description ......................................................................................................................................................... 1
Features ......................................................................................................................................................................... 1
Applications ..................................................................................................................................................................... 1
Warranty Information ....................................................................................................................................................... 2
Block Diagram ................................................................................................................................................................. 3
Pin Configuration ............................................................................................................................................................. 4
Pin Descriptions ............................................................................................................................................................... 4
General Description ....................................................................................................................................................... 13
Functional Description ................................................................................................................................................... 14
Device Configuration ..................................................................................................................................................... 14
Default Power Configuration .......................................................................................................................................... 14
Serial Management Interface ......................................................................................................................................... 14
Speed Selection ............................................................................................................................................................. 15
Operating Modes ........................................................................................................................................................... 16
Transparent Mode ........................................................................................................................................................... 18
Fiber Optic Input/Output Interface ................................................................................................................................. 18
Power Down Mode ......................................................................................................................................................... 19
Loopback Mode ............................................................................................................................................................. 19
Scrambler/Descrambler .................................................................................................................................................. 19
Output Off Mode ........................................................................................................................................................... 19
Backup Link Mode ......................................................................................................................................................... 19
LED Interface ................................................................................................................................................................. 20
Control Registers ........................................................................................................................................................... 21
Status Registers ............................................................................................................................................................ 23
Electrical Characteristics ............................................................................................................................................... 24
Physical Dimensions ...................................................................................................................................................... 28
Order Information .......................................................................................................................................................... 28
WARRANTY
Micro Linear makes no represent ations or warranties with respect to the accuracy , utility, or completeness of the content s of t his
publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No
license, express or implied, by estoppel or otherwise, to any patents or other intellectual property rights is granted by this
document. The circuit s contained in this document are offered as possible applications only . Particular uses or applications ma y
invalidate some of the specifications and/or product descriptions contained herein. The customer is urged to perform its own
engineering review before deciding on a p articular application. Micro Linear assumes no liability what soever, and disclaims any
express or implied warranty , relating to sale and/or use of Micro Linear product
s including liability or warranties relating to
merchantability, fitness for a p articular purpose, or infringement of any intellectual property right. Micro Linear product s are not
designed for use in medical, life saving, or life sustaining applications. If this document is "Advance", its contents describ
e a
Micro Linear product that is currently under development. All detailed specifications including pinouts and electrical specific ations
may be changed without notice. If this document is "Preliminary", it s contents are based on early silicon measurement s. Typical
data is representative of the product but is subject to change without notice. Pinout and mechanical dimensions are final.
Preliminary documents supersede all Advance documents and all previous Preliminary versions. If this document is "Final", its
contents are based on a characterized product, and it is believed to be accurate at the time of publication. Final Data Sheets
supersede all previously published versions. This document is Final.
© 2004 Micro Linear Corporation. All rights reserved. All other trademarks are the property of their respective owners.
Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862;
5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; 5,652,479;
5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897; 5,717,798; 5,742,151; 5,747,977; 5,754,012; 5,757,174; 5,767,653;
5,777,514; 5,793,168; 5,798,635; 5,804,950; 5,808,455; 5,811,999; 5,818,207; 5,818,669; 5,825,165; 5,825,223; 5,838,723;
5.844,378; 5,844,941. Japan: 2,598,946; 2,619,299; 2,704,176; 2,821,714. Other patents are pending.
2
Final Datasheet
DS110415
REFCLK 18
40 24
41
43
TPANDT
42
FOINSPD
44
FOANDT
2
16
17
6 27 25
5
8 4
14 13 7
Management
Interface
PECLTP
Configuration
and Control Logic
Auto Negotiation Processing
10Mbps Processing
PECLQU
AD4LIW
AD10
TPOUTOFF#
FOOUTOFF#
LED STATUS &
Backup Link
TPINSPD
BCKLINK
100Base-TX
Descrambler
AD32
SPEED
REQSD 37
PWRDWN#
100Mbps Clock and
Data Recovery
DUPLEX
Twisted Pair
or
PECL/LVPECL
Input
MDC
TPINN 11
MDIO
TPINP 10
Fiber Optic
or
PECL/LVPECL
Output
30 CQOS
32 FOINN
33 FOINP
36 RTOP
22 IOUT#
21 IOUT
39 SDTH
29 SDFO
9 12 15 19 20 23 26 28 31 34 35
VCCE
100Mbps Clock and Data
Recovery
GNDE
100Base-TX
Scrambler
GNDD
RTTP 38
GNDT
Fiber Optic
or
PECL/LVPECL
Input
VCCD
10Mbps Processing
GNDL
Twisted Pair
or
PECL/LVPECL
Output
VCCL
TPOUTN 3
VCCFC
Auto Negotiation Processing
GNDFC
Final Datasheet
VCCQ
J
GNDQ
3
GNDB
TPOUTP 1
ML6652
BLOCK DIAGRAM
DS110415
ML6652
PIN CONFIGURA TION
PIN DESCRIPTIONS
Signal names followed by "#" indicate active low input.
Pin No. Signal Name
CONFIGURATION
4
AD4LIW
5
4
AD32
I/O
I
I
Description
Sets the value of the Physical Layer (PHY) address bit 4 for accessing the Serial
Management Interface, and determines if the Link Integrity Warning (LIW)
function is enabled or disabled.
The Link Integrity Warning (LIW) function can only be enabled when only one
SPEED is available through setting of SPEED ( pin 27) and/or management
registers. When LIW is enabled and the input link is down at one interface to
the Media Converter, the transmitter output on that interface is turned off for
about 425ms every 3.8 seconds. It applies to both network interfaces and both
data rates. If the link at the other interface to the Media Converter is also
down, there is no output. The LIW function causes the Link Up indicator of the
link partner to blink.
Note: this pin is typically read a few microseconds after power-up, if it is tied
to supplies that do not track the ML6652 power improper results will occur.
Use VCCD (pin 19) as the pull up point, do not add decoupling capacitors to
this input pin (without thoroughly understanding your PCB layout dynamics the
safest course is to make short connections and do not add decoupling
capacitors to this input pin).
Sets the value of the PHY address bits 3 and 2 for accessing the Serial
Management Interface.
Note: this pin is typically read a few microseconds after power-up, if it is tied
to supplies that do not track the ML6652 power improper results will occur.
Use VCCD (pin 19) as the pull up point, do not add decoupling capacitors to
this input pin (without thoroughly understanding your PCB layout dynamics the
safest course is to make short connections and do not add decoupling
capacitors to this input pin).
Final Datasheet
DS110415
ML6652
PIN DESCRIPTIONS (continued)
Pin No. Signal Name
6
AD10
Pin Name
Input Level
0
1/3 of VCC
2/3 of VCC
VCC
I/O
Description
I
Sets the value of the PHY address bits 1 and 0 for accessing the Serial
Management Interface.
Note: this pin is typically read a few microseconds after power-up, if it is tied
to supplies that do not track the ML6652 power improper results will occur.
Use VCCD (pin 19) as the pull up point, do not add decoupling capacitors to
this input pin (without thoroughly understanding your PCB layout dynamics the
safest course is to make short connections and do not add decoupling
capacitors to this input pin).
AD4LIW
LIW Function
PHYAD4 Bit
Disabled
0
Enabled
0
Enabled
1
Disabled
1
AD32
PHYAD3 Bit
PHYAD2 Bit
0
0
1
0
1
1
0
1
AD10
PHYAD1 Bit
PHYAD0 Bit
0
0
1
0
1
1
0
1
Table 1.
7
PECLTP
PECLTP
Voltage
0
1/3 of VCC
2/3 of VCC
VCC
I
The copper interface is selected as shown in Table 2. When twisted pair
interface is selected, the scrambler and descrambler are enabled by default
and can be disabled with a management register bit.
When using twisted pair interface, this pin also defines the maximum
supported link distance. When the 10 meters maximum link length is selected,
the input is not equalized before being sliced.
Note: this pin is typically read a few microseconds after power-up, if it is tied
to supplies that do not track the ML6652 power improper results will occur.
Use VCCD (pin 19) as the pull up point, do not add decoupling capacitors to
this input pin (without thoroughly understanding your PCB layout dynamics the
safest course is to make short connections and do not add decoupling
capacitors to this input pin).
Interfaces at
PECLTP
TPINP/TPINN and
TPOUTP/TPOUTN Default
Twisted Pair
0
PECL/LVPECL
Twisted Pair
Twisted Pair
1
0
0
Copper
Length
100BASE-TX
Standard
PCB Traces
PCB Traces
10m
SHORTTP
Default
0
Output
Current
LOWITPOUT
Default
Standard
0
0
1
1
NA
Low
Standard
0
1
0
Table 2.
5
J
Final Datasheet
DS110415
ML6652
PIN DESCRIPTIONS (continued)
Pin No. Signal Name
8
PECLQU
PECLQU
Voltage
0
1/3 of VCC
2/3 of VCC
VCC
I/O
I
Description
The fiber interface is selected as shown in Table 3.
When using an LED driver and fiber optic receiver, this pin also defines the
maximum supported link distance.
When the 300m maximum link length is selected, the voltage thresholds for
Signal Detect are increased.
Interfaces at
PECLQU
FOINP/FOINN and
IOUT/IOUT#
Default
Quantizer andLED
0
Driver
PECL/LVPECL
1
Quantizer and LED
0
Driver
Quantizer and LED
0
Driver
Fiber Optic
Link Length
10BASE/100BASE
2Km/300m
SHORTFO Wavelength LONGWL
Default
Default
0
850nm
0
PCB Traces
2Km/2Km
0
0
NA
1300nm
0
1
300m/300m
1
850/1300nm
0
Table 3.
intensity.
25
DUPLEX
I
DUPLEX Voltage
0
VCC/2
VCC
This input can have one of three levels: VCC, VCC/2 or 0 Volts. This input has
80kΩ resistors internally connected to both VCC and Ground, generating VCC/
2 at the input if left unconnected. Settings defined by the DUPLEX power up
preset pin can be over written by the management interface. At power up the
DUPLEX pin causes the following default values to be written to management
register 30.
Note: this pin is typically read a few microseconds after power-up, if it is tied
to supplies that do not track the ML6652 power improper results will occur.
Use VCCD (pin 19) as the pull up point, do not add decoupling capacitors to
this input pin (without thoroughly understanding your PCB layout dynamics the
safest course is to make short connections and do not add decoupling
capacitors to this input pin).
TRANSPARENT#
Default
1
0
1
ADVERTFD#
Default
1
0
0
ADVERTHD#
Default
0
0
0
Table 4.
6
Final Datasheet
DS110415
ML6652
PIN DESCRIPTIONS (continued)
Pin No. Signal Name
I/O
Description
DUPLEX and SPEED can be used concurrently to set the power up mode of
the ML6652 see Tables 4 and 6. For Mode details see the General Description
section of this data sheet.
27
SPEED
I
This input can have one of three levels: VCC, VCC/2, and 0Volts. The input
has 80kΩ resistors internally connected to both VCC and Ground generating
VCC/2 at the input, if left unconnected. Settings defined by the SPEED power
up preset pin can be over written by the management interface. At power up
the SPEED pin causes the following default values to be written to
management register 30.
Note: this pin is typically read a few microseconds after power-up. If it is tied
to supplies that do not track the ML6652 power, improper results will occur.
Use VCCD (pin 19) as the pull up point, do not add decoupling capacitors to
this input pin (without thoroughly understanding your PCB layout dynamics the
safest course is to make short connections and do not add decoupling
capacitors to this input pin).
SPEED Voltage
DSBLAN
Default
1
0
1
0
VCC/2
VCC
SINGLESPEED
Default
1
0
1
SEL10Mbps
Default
1
0
0
Table 5.
Mode
Forced 10
Forced 100
Non-Transparent
Half-Duplex
Non-Transparent
Transparent
Operating Summary
SPEED Voltage
10Mbps data rate only available. The Duplex mode
0
is selected by the link partner.
100Mbps data rate only available. The Duplex mode
VCC
is selected by the link partner.
Only the Half-Duplex mode is advertised. Both 10
VCC/2
and 100Mbps data rates are available. Only the data
rate equivalent to the technology present at the fiber
optic input interface is advertised.
FLP Bursts are generated. Both Half-Duplex and
VCC/2
Full-Duplex modes are advertised. Both 10 and
100Mbps data rates are available. Only the data rate
equivalent to the technology present at the fiber optic
input interface is advertised.
Standard Auto-Negotiation sub-layer 10Mbps,
VCC/2
100Mbps and Auto-Negotiation far end link partner
signaling available.
DUPLEX Voltage
N/A
N/A
0
VCC
VCC/2
Table 6.
7
J
Final Datasheet
DS110415
ML6652
PIN DESCRIPTIONS (continued)
Pin No. Signal Name
I/O
CONTROL
13
TPOUTOFF#
I (CMOS)
Active low, the output stage of the twisted pair output is turned off. Contains
an on-chip 80kΩ pull-up resister.
14
FOOUTOFF#
I (CMOS)
Active low, the output stage of the fiber optic output is turned off. Contains an
on-chip 80kΩ pull-up resister.
24
PWRDWN#
I (CMOS)
Active low, all the circuits are powered down. Configuration pins are read and
register bits are initialized 5µs (typ) after a rising edge of PWRDWN#.
Contains an on-chip 80kΩ pull-up resister.
DATA SIGNAL INPUT/OUTPUT
1
TPOUTP
O
8
Description
The two operating modes available for these pins are selected with the
configuration pin PECLTP (pin 7) or the configuration bit PECLTP
Twisted Pair Interface Mode:
Transmit twisted pair positive and complementary outputs. These outputs form
a differential current output pair that drives Multi Level Transition (MLT-3)
waveforms into the network coupling transformer during 100Mbps mode,
Manchester encoded 10BASE-T data or Normal Link Pulses (NLPs) during
10Mbps mode, and Fast Link Pulse (FLP) Bursts during Auto-Negotiation.
TPOUTP and TPOUTN must have external pull up resistors to VCC (refer to
description of RTTP pin)
PECL/LVPECL Compatible Interface Mode:
PECL/LVPECL interface positive and complementary outputs. These outputs
form a differential current output pair that drives Non Return to Zero Inverted
(NRZI) encoded 100BASE-FX or 100BASE-SX symbols during 100Mbps mode,
Manchester encoded 10BASE-FL data or OPT_IDL during 10Mbps mode, and
Fiber Link Negotiation Pulse (FLNP) Bursts during Auto-Negotiation. TPOUTP
and TPOUTN must have external pull up resistors to VCC and be AC coupled
to the inputs of a fiber optic PMD module (refer to description of RTTP pin). A
resistor network may be needed to setup the common mode voltage at the
input pins of the PMD module
3
TPOUTN
O
38
RTTP
I
Twisted pair PECL/LVPECL compatible driver bias resistor. An external resistor
connected between RTTP and ground sets a constant bias current for the
differential output driver circuitry TPOUTP/TPOUTN.
These output currents depend on the operating mode.
The recommended external component values are:
Twisted Pair Mode:
2kΩ, 1%, between RTTP and ground
50Ω, 1%, between TPOUTP and VCC
50Ω, 1%, between TPOUTN and VCC
PECL Compatible mode:
2kΩ, 1%, between RTTP and ground
Equivalent 62Ω between TPOUTP and VCC
Equivalent 62Ω between TPOUTN and VCC
Also AC coupled to the PMD inputs
10
TPINP
I
11
TPINN
I
The two operating modes available for these pins are selected with the
configuration pin PECLTP (Pin 7) or the configuration bit PECLTP .
Twisted Pair Interface Mode:
Receive twisted pair positive and complementary inputs. These inputs form a
differential input pair that receives 100BASE-TX, FLP Burst, or 10BASE-T
signal from the network. The common mode voltage is set internally and the
differential input resistance is about 2kΩ.
The network termination must be added externally. It should contain a 100Ω
resister between pin 10 and 11 as shown in Figure 1.
Final Datasheet
DS110415
ML6652
PIN DESCRIPTIONS (continued)
Pin No. Signal Name
I/O
Description
ML6652
Input from
transformer
circuit Pulse
H1019 or
equiv.
10
100Ω
11
Figure 1. Twisted Pair Interface Mode Input Networks
PECL/LVPECL Compatible Interface Mode:
PECL/LVPECL compatible interface positive and complementary inputs. These
inputs form a differential input pair that receives 100BASE-FX, 100BASE-SX,
FLNP Bursts, or 10BASE-FL signal from a fiber optic PMD. The PMD outputs
should be AC coupled to these inputs with .1µF capacitors. The common mode
voltage is set internally with ~1kΩ or so resistors from each input pin to an onchip voltage reference. The positive output of the PMD (high during the highlight state) must connect to TPINP and the complementary output of the PMD
must connect to TPINN
9
37
REQSD
I
The two operating modes available for this pin are selected with the
configuration pin PECLTP or the configuration bit PECLTP
Twisted Pair Interface Mode:
Equalizer bias resistor pin. An external resistor connected between this pin and
ground sets internal currents that control the receiver’s adaptive equalizer
transfer function. The recommended resistor value is 5kΩ, 1%
PECL/LVPECL Compatible Interface Mode:
This input pin is connected to the Signal Detect (SD) output of a fiber optic
PMD module. The voltage level at this pin is compared to the voltage level at
pin SDTH to determine the logic value. If it is lower, then the input at TPINP/
TPINN is rejected. If it is higher, then the input at TPINP/TPINN is passed to the
internal circuits
39
SDTH
I
The voltage at this pin is a single ended PECL/LVPECL reference. Refer to
description of SDFO and REQSD pins. This pin is not used if the TPINP/TPINN
interface and the FOINP/FOINN are not setup for PECL/LVPECL compatible
mode. In such a case, the SDTH pin should be set to VCC
21
IOUT
O
22
IOUT#
O
The two operating modes available for these pins are selected with the
configuration pin PECLQU or the configuration bit PECLQU
Fiber Optic Interface Mode:
IOUT (pin 21) becomes the output connection to the cathode of an external
fiber optic LED. The output data is NRZI encoded 100BASE-FX or 100BASESX symbols during 100Mbps mode, Manchester encoded 10BASE-FL data or
OPT_IDL (10BASE-FL idle signal) during 10Mbps mode, and FLNP Bursts
during Auto-Negotiation.
IOUT# (pin 22) is optionally used to provide current peaking. If peaking is
J
Final Datasheet
DS110415
ML6652
PIN DESCRIPTIONS (continued)
Pin No. Signal Name
I/O
Description
voltage at the input pins of the PMD module
10
36
RTOP
O
Fiber optic LED or PECL/LVPECL driver bias resistor. An external resistor
connected between RTOP and ground sets a constant bias current for the single
ended LED driver or differential PECL/LVPECL driver circuitry. These output
currents depend on the operating mode.
The recommended external component values are:
Fiber Optic Interface mode: (1% resistors, +/- 10% currents)
Indicated is the current into pin IOUT during the High-Light state.
2.8kΩ between RTOP and ground for 50mA.
2kΩ between RTOP and ground for 70mA.
1.4kΩ between RTOP and ground for 100mA.
PECL/LVPECL Interface mode:
1.4kΩ, 1%, between RTOP and ground for 10mA current.
Equivalent 62Ω between IOUT and VCC.
Equivalent 62Ω between IOUT# and VCC.
Also AC coupled to PMD inputs
33
FOINP
I
32
FOINN
I
The two operating modes available for these pins and are selected with the
configuration pin PECLQU or the configuration bit PECLQU
Fiber Optic Interface Mode:
Fiber optic quantizer positive and complementary inputs. FOINP is
capacitively coupled to the output of a fiber optic receiver, while FOINN is
capacitively coupled to the VCC of the fiber optic receiver. Recommended
capacitor values: 10nF, 5%. FOINP voltage must be higher during the “high
light” state than during the low-light state
PECL/LVPECL Compatible Interface Mode:
PECL/LVPECL interface positive and complementary inputs. These inputs form
a differential input pair that receives 100BASE-FX, 100BASE-SX, FLNP Bursts,
or 10BASE-FL signal from a fiber optic PMD. The PMD outputs are AC coupled
to these inputs with 10nF, 5% capacitors. The common mode voltage is set
internally with ~900Ω (or so) resistors from each input pin to an on-chip
voltage reference. FOINP voltage must be higher during the “high light” state
than during the "low light" state
30
CQOS
29
SDFO
Data quantizer offset cancellation loop capacitor. An external capacitor
between this pin and VCC determines the dominant pole of the offset
cancellation feedback loop. The recommended value is .1µF, 10%. It is only
required in "Fiber Optic Interface" mode.
I
The two operating modes available for this pin are selected with the
configuration pin PECLQU or the configuration bit PECLQU
Fiber Optic Interface Mode:
This pin is not used and should be connected to VCC.
Final Datasheet
DS110415
ML6652
PIN DESCRIPTIONS (continued)
Pin No. Signal Name
I/O
Description
PECL/LVPECL Compatible Interface Mode:
This input pin is connected to the Signal Detect (SD) output of a fiber optic
PMD. The voltage level at this pin is compared to the voltage level at pin
SDTH to determine the logic value. If it is lower than the input at FOINP/
FOINN is rejected. If it is higher than the input at FOINP/FOINN is passed to
the internal circuits.
BACKUP LINK FUNCTION
40
BCKPLINK
I/O
INPUT MODE:
At power up, pin 40 (BCKPLINK) is read and the BCKPDIS register is set
appropriately. A high (VCC) at power up causes Register 28, Bit 1 (BCKPDIS)
to be set high (1) disabling the Back-up link function. BCKPDIS can
subsequently be over written by the management interface at any time.
Note: This pin is typically read a few microseconds after power-up, if it is tied
to supplies that do not track the ML6652 power, improper results may occur.
For BCKPLINK, use VCCD (pin 19) as the pull up point, do not add decoupling
capacitors to Pin 40 (without thoroughly understanding your PCB layout power
up dynamics the safest course is to make short connections and do not add
decoupling capacitors to this pin).
OUTPUT MODE:
After power-up, BCKPLINK is used as an output. It is Active high to enable a
secondary fiber link via a second ML6652 device (see Functional Description,
Backup Link Mode in this data sheet for details).
Use this function in forced 100Mbps mode, non loopback only
LED STATUS
41
TPINSPD
O
This output goes high to indicate that a 100Mbps signal is present at the TPINP/
TPINN interface, and it goes low to indicate that a 10Mbps signal is present at
the TPINP/TPINN interface. The signal can be idle or packets. This pin is set to
high impedance otherwise.
11
42
FOINSPD
O
This output goes high to indicate that a 100Mbps signal is present at the
FOINP/FOINN interface, and it goes low to indicate that a 10Mbps signal is
present at the FOINP/FOINN interface. The signal can be idle or packets. This
pin is set to high impedance otherwise.
43
TPANDT
O
When TPINSPD is in the high impedance state, no 10 or 100Mbps signal at
TPINP/TPINN, the TPANDT LED pulls low while receiving Auto-Negotiation
signal at the TPINP/TPINN interface. When TPINSPD is not in the high
impedance state, the TPANDT pin pulls low to indicate that a data packet is
being detected at the TPINP/TPINN interface. When a data packet is indicated,
the pulse width at TPANDT is stretched to a minimum of 1.3 to 2.7ms to
improve visibility. In any other case this pin is in high impedance state.
J
Final Datasheet
DS110415
ML6652
PIN DESCRIPTIONS (continued)
Pin No. Signal Name
LED STATUS (CONTINUED)
44
FOANDT
MANAGEMENT INTERFACE
16
MDIO
17
MDC
REFERENCE CLOCK
18
REFCLK
POWER AND GROUND
2
GNDT
12
I/O
O
Description
When FOINSPD is in the high impedance state, no 10 or 100Mbps signal at
FOINP/FOINN, the FOANDT LED pulls low while receiving Auto-Negotiation
signal at the FOINP/FOINN interface. When FOINSPD is not in the high
impedance state, the FOANDT pin pulls low to indicate that a data packet is
being detected at the FOINP/FOINN interface. When a data packet is
indicated, the pulse width at FOANDT is stretched to a minimum of 1.3 to
2.7ms to improve visibility. In any other case this pin is in high impedance
state.
Management data TTL compatible input/output pin. Connect to ground if
unused
Management clock TTL input. The maximum frequency can be 12.5MHz
instead of the 2.5MHz limit of IEEE 802.3. Connect to ground if unused
25MHz Reference Clock CMOS input. This clock is used for internal digital
logic, and as a reference for the PLLs.
Ground for the twisted pair driver output stage.
12
GNDE
Ground for the equalizer, one PLL and part of the descrambler and twisted pair
driver.
15
GNDD
Ground for CMOS noisy circuits.
20
GNDL
Ground for the fiber optic LED driver output stage.
28
GNDFC
Ground for one PLL, part of the scrambler, fiber optic LED driver, and
quantizer.
34
GNDQ
Ground for the quantizer and central bias.
35
GNDB
Ground for part of the central biasing.
9
VCCE
Power supply for the equalizer, one PLL and part of the descrambler and
twisted pair driver.
19
VCCD
Power supply for CMOS noisy circuits.
23
VCCL
Power supply for the fiber optic LED driver output stage.
26
VCCFC
Power supply for one PLL, part of the scrambler, fiber optic LED driver, and
quantizer.
31
VCCQ
Power supply for the quantizer and central bias.
Final Datasheet
DS110415
ML6652
GENERAL DESCRIPTION
The ML6652 Fast Ethernet Media Converter provides
signal conversion between the following standards:
Interface Modes
1) Twisted pair interface
• 10BASE-T to 10BASE-FL; (10Mbps twisted pair copper
media and 10Mbps 850nm fiber media)
• Proprietary 10BASE-T to 10BASE-1300nm Fiber;
(10Mbps twisted pair copper media and 10Mbps
1300nm fiber media).
a)
Twisted Pair (Transformer input) Mode or
b)
PECL/LVPECLMode
b) Fiber Optic Interface
i)
• 100BASE-TX to 100BASE-SX/FX (100Mbps twisted pair
copper media and 1300nm or 850nm fiber media).
• 100BASE-FX to 100BASE-SX (100Mbps 850nm fiber
media and 100Mbps 1300nm fiber media).
Quantizer/Fiber Optic LED Driver Mode or
ii) PECL/LVPECLMode
Special Modes
1) Power Down Mode
The ML6652 supports conversion between Twisted Pair
Side, Fast Link Pulses (FLP) and Fiber Side, Fiber Link
Negotiation Pulses (FLNP). It supports ISO/IEC 8802.3,
IEEE 802.3, and TIA/EIA-785 including Auto-Negotiation
on both twisted pair and fiber optics.
The ML6652 data interfaces can all be configured in a
number of ways. The twisted pair inputs and outputs can
be configured in Twisted Pair Mode to interface with a 1:1
transformer for transmit and receive or in PECL/LVPECL
Mode to interface a PMD module. The fiber optic inputs
and outputs can be configured in Quantizer/Fiber Optic
Mode with an LED driver or in PECL/LVPECL Mode. LED
status outputs identify internal operational status.
The ML6652 operating modes are configurable through
control input pins (at power up) or through management
control registers that are programmable through an
interface protocol compatible with MII Serial
Management Interface as defined in IEEE 802.3-1998
standards.
a)
Configurable through:
(i) Control pin 24 or
(ii) Management control register
2) Loopback Test Modes
a)
For the fiber optic interface or
b)
The twisted pair interface
c)
Both are configurable through the Management
control register and include bypassing clock and
data recovery blocks.
3) Transmitter Output Off Mode:
a)
Twisted Pair or
b)
Fiber Optic
c)
Both are configurable through the Management
control registers or control pins TPOUTOFF# (pin
13) and FOOUTOFF# (pin 14).
CONFIGURABLE MODES
4) Backup Link Mode
Operating Modes (Forced, Transparent And Nontransparent)
a)
Configurable through Management control
register or via BCKPLINK (Pin 40).
1) FORCED 10Mbps only mode,
2) FORCED 100Mbps only mode,
3) NON-TRANSPARENT Half Duplex only, with AutoNegotiation
4) NON-TRANSPARENT Full and Half Duplex with AutoNegotiation
5) TRANSPARENT 10/100Mbps with Auto-Negotiation
6) NON-TRANSPARENT Special case
13
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Final Datasheet
DS110415
ML6652
FUNCTIONAL DESCRIPTION
DEVICE CONFIGURATION
Configuring the ML6652 Media Converter is
accomplished through input configuration pins or bits in
management control register 30. Configuration pins
AD4LIW, AD32 and AD10 determine the PHY address
used with the serial management interface consisting of
MDIO (pin 16) and MDC (pin 17). The setting of any R/W
bit in the control management registers can be modified
by writing data to the register through the serial
management interface. The control management registers
27, 28, 30, and 31 always indicate the current operating
mode of the ML6652.
The PHY address settings defined by AD4LIW (pin 4),
AD32 (pin 5), and AD10 (pin 6) are latched and must
remain stable during any serial management interface
read or write operation. The PHY address pins each have
four (4) distinct input levels and together encode the
required five (5) bit PHY addresses. Nominal values of
VCC and 0V are obtained with directions to VCCD or
GNDD. Nominal values of 2/3 VCC and 1/3 VCC must be
developed with external resistor dividers.
Input pins SPEED (pin 27) and DUPLEX (pin 25) are three
level inputs having internal 80kΩ resistors connected to
both VCC and Ground. Nominal input voltage levels are
VCC, VCC/2, when input is left floating, and Ground. The
state of configuration pins DUPLEX, SPEED, PECLTP (pin
7) PECLQU (pin 8), and AD4LIW (pin 4) are latched 3µ to
8µs after:
tCPER
MDC
tCPW
tCPW
MDIO
tSPWS
tSPWH
Figure 2. Write
tCPER
MDC
tSPRS
tSPRH
tCPW
tCPW
MDIO
1) system power up (internal signal POR going low)
2) trailing edge of PWRDWN# (pin 24) Ground to VCC
Figure 3. Read
3) reset is cleared.
Input pins PECLTP (pin 7) and PECLQU (pin 8) are 4 level
input pins with no internal pull-up or pull-down resistors
connected. Nominal values of VCC and 0V are obtained
with directions to VCC or Ground. Nominal values of 2/3
VCC and 1/3 VCC must be developed with external
resistor dividers.
DEFAULT POWER ON CONFIGURATION
This configuration method can be used to set the device
whenever the MII serial management interface is not
available. The logic levels at configuration pins DUPLEX,
SPEED, PECLTP, PECLQU and AD4LIW are decoded and
latched in management control registers 28, 30 and 31
after system power up or after a (low) to (high) transition
at PWRDWN#.
14
Final Datasheet
DS110415
ML6652
FUNCTIONAL DESCRIPTION
SPEED SELECTION
The Operating modes, FORCED, TRANSPARENT and
NON-TRANSPARENT are chosen at power up by setting of
the DUPLEX and SPEED pins. Thereafter the operating
modes may be set by toggling bits in management register
30.
DUPLEX and SPEED must be used concurrently to set the
mode of the ML6652 see Tables 6 and 7.
Management
Interface Operating
Modes
Bit
TRANSPARENT#
Bit
ADVERTHD#
Bit
DSBLAN
Bit
ADVERTFD#
Bit
SINGLESPEED
Bit
SEL10Mbps
Forced 10
N/A
N/A
1
N/A
1
1
Forced 100
N/A
N/A
1
N/A
1
0
Non-Transparent
Half-DUPLEX
1
0
0
1
0
0
Non-Transparent
1
0
0
0
0
0
Transparent
0
0
0
0
0
0
Table 7.
15
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Final Datasheet
DS110415
ML6652
OPERATING MODES
Operating Modes are:
1) Forced 10
0 (zero) Volt input on SPEED (or the equivalent Reg.
30 settings) enables only FORCED 10Mbps operation.
100Mbps and Auto-Negotiation are disabled. Link
Integrity Warning (LIW) can also be enabled.
2) Forced 100
VCC input on SPEED (or the equivalent Reg. 30
settings) enables FORCED 100Mbps operation only.
10Mbps and Auto-Negotiation are disabled. Link
Integrity Warning (LIW) can also be enabled.
3) Non-Transparent Half-DUPLEX
VCC/2 (input floating) input on SPEED (or the
equivalent Reg. 30 settings) enables Transparent or
non-transparent 10Mbps and 100Mbps operation.
DUPLEX input (0 Volts at power up) or management
register 30 select NON-TRANSPARENT Mode of
operation and force Half-DUPLEX. Non-transparent
mode was designed for networks that have AutoNegotiation capabilities only on the copper side. The
ML6652 operates in Non-Transparent Mode when all
of the following four conditions are met:
Note 2: SPEED and DUPLEX modes are the only abilities
advertised in this mode by the ML6652
Note 3: Link Integrity Warning (LIW) can not be enabled
in this mode.
4) Non-Transparent
VCC/2 (input floating) input on SPEED (or the
equivalent Reg. 30 settings) enables Transparent or
non-transparent 10Mbps and 100Mbps operation.
DUPLEX input (VCC at power up) or management
register 30 select NON-TRANSPARENT Mode of
operation. Non-transparent mode was designed for
networks that have Auto-Negotiation capabilities only
on the copper side. The ML6652 operates in NonTransparent Mode when all of the following four
conditions are met:
a)
Duplex input is a VCC or a 0 Volts (or the
equivalent Reg. 30 settings) AND
b)
Twisted Pair Link is Auto-Negotiation capable
AND
a)
Duplex input is a VCC or a 0 Volts (or the
equivalent Reg. 30 settings) AND
c)
Fiber Optic Link Partner is not Auto-Negotiation
capable AND
b)
Twisted Pair Link is Auto-Negotiation capable
AND
d)
c)
Fiber Optic Link Partner is not Auto-Negotiation
capable AND
Both 10Mbps and 100Mbps operation are enabled
by SPEED input at VCC/2 or by bits in
management register 30.
d)
Both 10Mbps and 100Mbps operation are enabled
by SPEED input at VCC/2 or by bits in
management register 30.
In this mode, the twisted pair output is disabled until
signal is detected at both the twisted pair and the fiber
optic inputs. The fiber optic output is not disabled, and it
shows the input signal from the twisted pair interface
converted to the equivalent fiber optic technology.
When the TP link partner negotiates the link through the
Auto-Negotiation protocol and FLP bursts reach the
ML6652 operating in the Non-Transparent mode, the
ML6652 will start generating its own FLP Bursts
advertising the speed detected at the FO input and the
DUPLEX mode selected through the DUPLEX pin or
through the management interface bits 30.15 and 30.10
The ML6652 will transmit FLP Bursts as long as it receives
FLP Bursts from the TP link partner. (The decision that the
link is settled will be made by the TP link partner.)
Note 1: In Non-Transparent Half Duplex Mode, only the
Half Duplex mode of operation is advertised through the
Auto-Negotiation protocol. However nothing changes
inside the ML6652, the transmit and receive paths are
16
completely separate and are always capable of
simultaneous or full duplex use.
In this mode, the twisted pair output is disabled until
signal is detected at both the twisted pair and the fiber
optic inputs. The fiber optic output is not disabled, and it
shows the input signal from the twisted pair interface
converted to the equivalent fiber optic technology.
When the TP link partner negotiates the link through the
Auto-Negotiation protocol and FLP bursts reach the
ML6652 operating in the Non-Transparent mode, the
ML6652 will start generating its own FLP Bursts
advertising the speed detected at the FO input and the
DUPLEX mode selected through the DUPLEX pin or
through the management interface bits 30.15 and 30.10
The ML6652 will transmit FLP Bursts as long as it receives
FLP Bursts from the TP link partner. (The decision that the
link is settled will be made by the TP link partner.)
Note 1: SPEED and DUPLEX modes are the only abilities
advertised in this mode by the ML6652
Note 2: Link Integrity Warning (LIW) can not be enabled
in this mode.
5) Transparent
VCC/2 (input floating) input on SPEED (or the
equivalent Reg. 30 settings) enables Transparent or
non-transparent 10Mbps and 100Mbps operation.
DUPLEX input and management register 30 select
Final Datasheet
DS110415
ML6652
OPERATING MODES
TRANSPARENT or NON-TRANSPARENT Mode of
operation. Transparent Mode is the default mode of
operation for the ML6652 when DUPLEX input is VCC/
2. In this mode, the control circuit implements the
state diagrams of the Auto-Negotiation sub-layer
defined in clause 5 of TIA/EIA-785 standard. In general
the enabled Physical Media Attachment (PMA) at the
fiber optic output is the equivalent to the technology
detected at the twisted pair input and the enabled
PMA at the twisted pair output is the equivalent to the
technology detected at the fiber optic input. Of
course system Auto-Negotiation causes both paths to
the greatest common denominator. The system
chooses the greatest common denominator in the
following order least to greatest:
a)
a)
Half DUPLEX, 10Mbs
iii) Special modes
b)
Full DUPLEX, 10Mbs
(1) Power Down Mode
c)
Half DUPLEX, 100Mbs
(2) Loopback Test Modes
d)
Full DUPLEX, 100Mbs
i)
Set operating modes,
(1) FORCED 10Mbps only mode,
(2) FORCED 100Mbps only mode,
(3) NON-TRANSPARENT Half Duplex only
(4) NON-TRANSPARENT Full and Half
Duplex with Auto-Negotiation
(5) TRANSPARENT 10/100Mbps with AutoNegotiation
ii) Select interface configurations
(1) Both fiber and copper
(3) Transmitter Output Off Mode:
Note: In transparent mode the ML6652 does not generate
information. It only takes the information from the link
partner on one side (without adding or remove any
information) and it translates it to the language of the link
partner of other side.
This mode is for use in networks that have AutoNegotiation capabilities on both copper and fiber sides.
The ML6652 follows the demands of the far end link
partners during the network Auto-Negotiation. Link
Integrity Warning (LIW) cannot be enabled in this mode.
6) Special case for the Non-T
ransparent Mode:
The ML6652 operates in this mode when all of the
following three conditions are met:
a)
Duplex input is a VCC or a 0 Volts (or the
equivalent Reg. 30 settings) AND
b)
Twisted Pair Link is Auto-Negotiation capable
AND
c)
Both 10Mbps and 100Mbps operation are enabled
by SPEED input at VCC/2 or by bits in
management register 30.
The ML6652 can be configured in two general ways:
1) Through the management interface, pins 16 (MDIO)
and 17 (MDC), all of the registers can be changed
after power-up. The management interface settings
override any power-up register settings.
J
(4) Backup Link Mode (Pin 40)
iv) And read control information
2) Through configuration and control pins
Note: Pins 4 AD4LIW and 40 BCKPLINK are both
shared between a power-up read and a later control
function and thus appear in both lists. Pin 4 AD4LIW
is read and the condition latched to set register 30 bit
12 subsequently it is used as an unlatched address
pin. Pin 40 BCKPLINK is read and the condition
latched to set register 28 bit 1, subsequently it is used
as an output to drive a second ML6652 to provide
back up link.
a)
If the Fiber Optic Link Partner is Auto-Negotiation capable
the ML6652 will allow the fiber optic link partner to AutoNegotiate through the ML6652 to the twisted pair link
partner. In this special case the non-transparent mode acts
in the same way as the transparent mode. This is because
the self-generation of FLP bursts is suppressed by the
presence of the FLP bursts from the fiber link partner.
17
All internal registers may be used to:
At power up the following pins are read and the
appropriate registers are set: (but with a limited
sub-set of the control afforded by the
management control registers.)
i)
Pin 7 (PECLTP)
ii) Pin 8 (PECLQU)
iii) Pin 25 (DUPLEX)
iv) Pin 27 (SPEED)
v)
Pin 4 (AD4LIW)
vi) Pin 40 (BCKLINK)
Note: These pins are typically read a few microseconds
after power-up, if they are tied to supplies that do not
track the ML6652 power improper results may occur. To
reduce the parts count, pins Pin 7 (PECLTP), Pin 8
(PECLQU), Pin 4 (AD4LIW), Pin 5 (AD 32) and Pin 6
(AD10) may be supplies from a common 20kΩ resistor
tree as shown on our evaluation boards schematics
Final Datasheet
DS110415
ML6652
OPERATING MODES
(without thoroughly understanding your PCB layout power
up dynamics the safest course is to make short
connections and do not to add decoupling capacitors to
these pins).
When Pin 7 (PECLTP) and Pin 8 (PECLQU) are connected
to 1/3 VCC and 2/3 VCC use >20kΩ resistors and
connect to the proper decoupled VCCD and GNDD. For
Pin 7 (PECLTP) use Pin 19 VCCD and Pin 15 GNDD, do
not add decoupling capacitors to Pin 7. For Pin 8
(PECLQU use Pin 19 VCCD and Pin15 GNDD, do not add
decoupling capacitors to Pin 8. When Pin 25 (DUPLEX)
and Pin 27 (SPEED) are connected to VCC/2 use the
internal 80kΩ resistor pair by leaving the pin open. Do not
add external resistors or decoupling capacitors these
pins.
When Pin 4 AD4LIW is connected to 1/3 and 2/3 VCC use
>20kΩ resistors and connect to the proper decoupled
VCCD and GNDD. When Pin 4 AD4LIW is connected to
ground use Pin 15 GNDD. When Pin 4 AD4LIW is
connected to VCC use Pin 19 VCCD and do not add
decoupling capacitors to pin 4 AD4LIW. Pull Pin 40
BCKPLINK up and down (One and Zero) through a 10K
resistor connected to either Pin 19 VCCD or Pin 15
GNDD.
b)
The following pins are available at all times for
control: (Note: When Pin 4 (AD4LIW) Pin 5 (AD
32) and Pin 6 (AD10) are connected to 1/3 VCC
and 2/3 VCC use >20K ohm resistors and connect
to the proper decoupled Pin 19 VCCD and Pin 15
GNDD do not add decoupling capacitors to Pin 4,
5 or 6.)
i)
Pin 4 (AD4LIW)
ii)
Pin 5 (AD 32)
iv) Pin 13 (TPOUTOFF#)
Pin 14 (FOOUTOFF#)
vi) Pin 24 (PWRDWN#)
vii) Pin 40 (BCKPLINK)
c)
LED Status indicators are available:
i)
Pin 41 (TPINSPD)
ii)
Pin 42 (FOINSPD)
iii) Pin 43 (TPANDT)
iv) Pin 44 (FOANDT)
Thus the ML6652 is designed to self-configure in stand
alone applications as well as act under the control of a
microprocessor or other control device in a managed
setting.
18
Twisted Pair Input/Output Interface
Two operating modes are available for the twisted pair
differential inputs TPINP (pin 10)/TPINN (pin 11) and the
differential output pair TPOUTP (pin 1)/TPOUTN (pin 3)
selected by the input configuration pin PECLTP (pin 7) or
by the setting of bit in management register 30.
In twisted pair interface mode, the inputs form a
differential pair that receives twisted pair positive and
complementary signals and the outputs form a differential
current output pair that drives MLT-3 encoded 100BASE
data, Manchester encoded 10BASE-T data or NLPs
during 10Mbps mode, and FLP bursts during AutoNegotiation into a network coupling 1:1 transformer.
To communicate between two fiber optic sources, the
twisted pair input and output can be configured as PECL/
LVPECL interface compatible with the configuration pin
PECLTP or by setting bit high. In this mode, both
the input differential pair and the output differential pair
provide PECL/LVPECL compatible interface positive and
complementary levels.
The preferred mode of operation is twisted pair compatible
signal levels. The default mode of operation is set by
PECLTP (pin 7).
Fiber Optic input/Output Interface
Two modes of operation are available for the fiber optic
inputs FOINP (pin 33), FOINN (pin 32) and the fiber optic
outputs IOUT (pin 21) and IOUT# (pin 22) selected by
input control pin PECLQU (pin 8) or by the setting of bit
in management register 30.
PECLQU is a four level input and when set at VCC/3 by
an external resistor network the two outputs IOUT/IOUT#
form a differential output pair that are AC coupled to a
fiber optic PMD module. The differential current output
pair output NRZI encoded 100BASE-FX or 100BASE-SX
symbols in 100Mbps mode. They output Manchester
encoded 10BASE-FL data or Optical Idle (OPT_IDL) in
10Mbps mode and FLNP bursts during Auto-Negotiation.
IOUT and IOUT# require external pull-up resistors to VCC
and must be AC coupled to a fiber optic PMD module. A
resistor network is required to establish the common mode
voltage at the inputs to the PMD module.
iii) Pin 6 (AD10)
v)
TRANSPARENT MODE
With PECLQU input level of VCC, 2VCC/3, or 0Volts, the
two outputs become independent and are defined as the
Fiber Optic Interface Mode. In this mode, IOUT becomes
a data output to a fiber optic LED driver connecting to the
cathode. The data is NRZI encoded 100BASE-FX or
100BASE-SX symbols in 100Mbps mode. The data is
Manchester encoded 10BASE-FL or OPT_IDL in 10Mbps
mode and FLNP Bursts during Auto-Negotiation.
IOUT# is optionally used to provide current peaking. If
current peaking is implemented, typically a 1kΩ off-chip
Final Datasheet
DS110415
ML6652
OPERATING MODES
resistor is connected to ground and a 1nf capacitor is
connected to IOUT to determine the peaking current
waveform. If peaking is not implemented, IOUT# should
be connected directly to VCC.
The preferred mode of operation is PECL/LVPECL
differential outputs. The default mode of operation is set
by PECLQU (pin 8).
POWER DOWN MODE
Enabled by setting PWRDWN# (pin 24) all circuits are
powered down, all internal control logic is reset, and
output currents are turned off. 3µs to 8µs after the low to
high transition (trailing edge) of PWRDWN# the logic
levels at configuration input pins DUPLEX (pin 25), SPEED
(pin 27), PECLTP (pin 7), PECLQU (pin 8), AD4LIW (pin
4), and BCKLINK (Pin 40) are latched in the ML6652 and
all management control register bits are reset.
Enabled by setting management register bit high,
all circuits are powered down, (except the management
interface) all internal control logic is reset and output
currents are turned off. Control input pins DUPLEX,
SPEED, PECLTP, PECLQU, and AD4LIW are not relatched
and management control register bits are not reset.
LOOPBACK MODE
Loopback of both the twisted pair inputs and fiber optic
inputs to their respective differential outputs is possible
with the ML6652.
Enabled by setting management register bit , the
twisted pair input signal at TPINP (pin 10) and TPINN (pin
11) are looped back to TPOUTP (pin 1) and TPOUTN (pin
3). The clock/data PLL is normally included in the
loopback path. Setting management register bit
PLLPBK# active (low) removes the PLL from the loopback
path.
Enabled by setting management register bit , the
fiber input signal at FOINP (pin 33) and FOINN (pin 32)
are looped back to IOUT (pin 21) and IOUT# (pin 22).
The clock/data PLL is normally included in the loopback
path. Setting management register bit
PLLLPBK# active (low) removes the PLL from the
loopback path.
SCRAMBLER/DESCRAMBLER
The scrambler and descrambler functions are enabled in
the 100Mbps signal paths by setting the management
register bit . The scrambler and descrambler are
compliant with the Fiber Distributed Data Interface
Twisted Pair-Physical Media Dependent (FDDI TP-PMD)
standard ANSI X3T9.5 PMD/312. Setting management
register bit forces the 11-bit scrambler register
state to 00000000011(bin). Clearing returns the
scrambler register to normal operation.
19
J
The default state for is logic 0 or normal scrambler
operation.
OUTPUT OFF MODE
Either the twisted pair outputs or the fiber optic outputs
can be turned off by a control input pin or a management
register bit. Disabling either differential output results in
the output pair being turned off and the data output pins
entering a high impedance state.
The twisted pair differential output TPOUTP and TPOUTN
is turned off by setting TPOUTOFF# low or management
register bit high. The fiber optic differential
output IOUT and IOUT# is turned off by setting
FOOUTOFF# low or management register bit
high.
BACKUP LINK MODE
A backup link mode of operation is available when the
primary fiber optic link is down. It can only be enabled
in the 100Mbps only, non-loopback mode of operation
configured by SPEED (pin 27) input level set to VCC. Two
ML6652 devices are required to implement the backup
link mode of operation with one driving the primary fiber
optic link and the second driving the backup or secondary
fiber optic link.
If a backup fiber optic link mode of operation is not
implemented, BCKPLNK (pin 40) is connected to VCC.
Backup Link Mode is enabled in the primary ML6652 by
connecting a 10kΩ resister in series with an LED from
BCKPLNK (pin 40) with the LED cathode to ground.
Configuring the two ML6652 media converters simply
requires BCKPLNK (pin 40) of the primary device to be
connected to TPOUTOFF# of the secondary device.
A second configuration is suggested to avoid confusion;
that is Pin 40 (BCKPLINK) of the primary ML6652 is
connected to both pin 13 (TPOUTOFF#) and 14
(FOOUTOFF#) of the secondary ML6652, disabling both
copper and fiber outputs. A third configuration, if Pin 24
(PWRDWN#) of the secondary ML6652 is not being used
to control power usage by the system (for example in a
stand alone configuration without system microprocessor
control) Pin 40 (BCKPLINK) of the primary ML6652 can be
connected to Pin 24 (PWRDWN#) of the secondary
ML6652, powering down the secondary ML6652 to save
power.
The primary link is not functioning if a Far End Fault (FEF)
signal is received on the fiber optic differential input pair
FOINP and FOINN as defined in clause 24 of IEEE Std.
802.3-1998, or when the fiber optic signal does not meet
the 100Mbps signal detection constraints.
When Backup Link Mode is enabled, the input and output
signal dependencies are related as shown in Table 8.
Final Datasheet
DS110415
ML6652
OPERATING MODES
Input Signal at pins Input Signal at pins
FOINP/FOINN
TPINP/TPINN
FOINSPD Output:
Input Speed Indicator
Output Level
BCKPLINK Output:
Enabler of Secondary Link
LED Cathode
LED Cathode
Output Level
to Ground
to Ground
Secondary
Twisted Pair
Output
Output Signal at
pins
IOUT/IOUT#
Good 100Mbps
signal and not FEF
NA
High
On
Low
Off
High
Impedance
TPINP/TPINN
Equivalent
FEF Pattern
NA
High
On
High
On
Enabled
TPINP/TPINN
Equivalent
Not good
100Mbps signal
Good
100Mbps signal
Low or High-Z
Off
High
On
Enabled
FEF Pattern
Not good
100Mbps signal
Not good
100Mbps signal
Low or High-Z
Off
High
On
Enabled
High Impedance
LED Interface
The recommended LED configuration for Pins 41
(TPINSPD) and 42 (FOINSPD) is shown in Figure 4 and
Table 9. Note: R2 may be as low as 511Ω to insure only
one LED at a time will be on.
VCC
LED's Von
R1
R2
R3
2.1-2.2V
100
1.2K
100
1.8-1.9V
150
1.2K
150
1.7V
200
1K
200
R1
To pin 41 or 42
R2
R3
Figure 4.
20
Table 9. LED Colors vs. Resistor Values for Figure 4
Final Datasheet
DS110415
ML6652
CONTROL REGISTERS
Control Registers
Register 31 ADDR 11111 (bin) 1F (hex) All bits are R/W All bits default to 0
Bit
15
Name
Power Down
Description
R/W
Setting bit to 1 powers down all circuits and resets all
R/W
control logic. Register bits are not reset (except the management interface)
and new configuration data is not loaded
Default
0
14
FOOUTOFF
Setting bit to 1 turns off the output stage of the Fiber Optic
R/W
driver leaving the output pins in a high impedance state.
Setting bit to 1 creates the exact same results as a 0 input on FOUTOFF#
0
13
TPOUTOFF
Setting bit to 1 turns off the output stage of the twisted pair
R/W
line driver leaving the output pins in a high impedance state. Setting bit
to 1 creates exact same result as 0 input on TPOUTOFF#
0
12
LPBKTOTP
Setting bit to 1 directs TPINP (pin 10) and TPINN (pin 11)
to loop back to TPOUTP (pin 1) and TPOUTN (pin 3). Including
the PLL in the 100Mbps signal path is controlled by ,
PLLLPBK#
R/W
0
11
LPBKTOFO
Setting bit to 1 directs FOINP (pin 33) and FOINN (pin 32)
to loop back to IOUT (pin 21) and IOUT# (pin 22). Including the
PLL in the 100Mbps signal path is controlled by PLLLPBK#.
R/W
0
10
PLLLPBK#
Setting bit to 1 removes the clock/data recovery PLL from
the signal path during 100Mbps loop back modes
R/W
0
7-4
Reserved
3-0
Reserved
R/W
R/W
Default
0
Setting bit to 1 disables detection of FLNP and FLP bursts
R/W
Set by
SPEED
(pin 27)
Setting this bit to 1 causes all configuration pins to be read
and all register bits to be initialized 3 to 8µs after the bit is
returned to a 0. The bit is self clearing
R/W
0
Register 30 ADDR 11110 (bin) 1E (hex) All bits are R/W
Bit
15
Name
ADVERTHD#
14
DSBLAN
13
RESET
12
LIW
Setting this bit to 1 enables the Link Integrity Warning function
R/W
Set by
AD4LIW
(pin 4)
11
TRANSPARENT#
Setting bit to 1 enables NON-TRANSPARENT Mode of operation
Setting bit to 0 enables TRANSPARENT Mode of operation
R/W
Set by
DUPLEX
(pin 25)
10
ADVERTFD#
Setting bit to 0 and TRANSPARENT# set to 1
causes Full Duplex capability to be advertised in FLP bursts
Setting bits to 1 and TRANSPARENT# set to 0
causes Full Duplex capability to not be advertised in FLP bursts
Setting TRANSPARENT# to 0 causes ADVERFTD#
to be ignored
R/W
Set by
DUPLEX
(pin 25)
21
Description
Setting bit to 1 AND TRANSPARENT# set to 1
causes Half Duplex capability to be advertised in FLP bursts
Setting bit to 0 AND TRANSPARENT# set to 1
causes Half Duplex capability to not be advertised in FLP bursts
Setting TRANSPARENT# to 0 causes ADVERTHD#
to be ignored
Final Datasheet
DS110415
ML6652
CONTROL REGISTERS
Control Registers
Register 30 Continued
Bit
9
Name
SINGLESPEED
Description
Setting this bit to 1 enables only a single data rate
R/W
R/W
Default
Set by
SPEED
(pin 27)
8
SEL 10Mbps
7
PECLQU
Setting bit to 1 causes the interface at FOINP (pin 33),
FOINN (pin 32), IOUT (pin 21), and IOUT# (pin 22) to be PECL/LVPECL
compatible
6
LONGWL
Setting bit to 1 assumes optical wavelength to be 1300nm
R/W Set by
Setting this bit to 0 assumes optical wavelength to be 850nm when the
PECLQU
quantizer/fiber optic LED driver are used.
(pin 8)
If PECLQU is set to 1 or SHORTFO is set to 1 LONGWL is ignored
5
SHORTFO
Setting bit 1 sets up the signal detection circuit for a
R/W Set by
fiber maximum link distance of 300 meters in both 10Mbps and
PECLQU
100Mbps modes when the quantizer/fiber optic LED driver is used.
(pin 8)
Setting bit to 0 sets up the signal detection circuit for a maximum
link distance of 2Km, when the quantizer/fiber optic LED driver are used.
If PECLQU is set to 1 SHORTFO is ignored
4
LOWITPOUT
Setting bit to 1 causes TPOUTP (pin 1) and TPOUTN (pin 3)
R/W Set by
output current to be reduced to 25% of the standard twisted pair
PECLTP
output current. The output remains 100BASE-TX, 10BASE-T, or FLP Bursts.
(pin 7)
If PECLTP is set to 1, LOWITPOUT is ignored
3
PECLTP
2
SHORTTP
1
0
Setting bit to 1 and SINGLESPEED is 1
R/W Set by
enables only 10Mbps data rate
SPEED
Setting bit to 0 and SINGLESPEED enables only 100Mbps data rate
(pin 27)
R/W
Set by
(pin 8)
Setting bit to 1 causes the interface at TPINP (pin 10), TPINN
(pin 11), TPOUTP (pin 1), and TPOUTN (pin 3) to be PECL or
PECL compatible
R/W
Set by
PECLTP
(pin 7)
Setting bit to 1 sets up the twisted pair interface receiver
circuit for a maximum link distance of 10 meters, bypassing the
Unshielded Twisted Pair (UTP-5) equalizer. Setting bit to 0 maintains
the equalizer in the signal path.
If PECLTP is set to 1, SHORTTP is ignored
R/W
Set by
PECLTP
(pin 7)
SCRON
Setting bit to 1 enables scrambler/descrambler function.
Setting bit to 0 disables both functions
R/W
Set by
PECLTP
(pin 7)
RSTSCR
Setting bit to 1 forces the scrambler register state to 00000000011 (binary) R/W
Setting bit to 0 releases logic in the scrambler block
REGISTER 28
ADDR 11100 (bin)
Bit
15-5
Name
Reserved
4
SLOWMLT3
3
FSENSEDIS
2
0
1C (hex) All bits are Read Write
R/W
R/W
Default
0
Set high (1) reduces rise and fall times of MLT-3 outputs on pins
TPOUTP (1) and TPOUTN(3)
R/W
R/W
0
0
Set high (1) disables 100 Mbps PLL frequency sensing circuits
R/W
0
FEFDSBL
Set high (1) disables Far-End-Fault pattern generation and detection.
R/W
0
1
BCKPDIS
Set high (1) disables Backup Link function and overwrites
BCKPLINK (40) configuration setting.
R/W
0
0
Reserved
R/W
0
22
Description
Final Datasheet
DS110415
ML6652
STATUS REGISTERS
Status Registers
Register 27 ADDR 11011 (bin) 1B (hex)All bits are Read Only
Bit
15
Name
FOFORCELO
Description
This bit set high when the fiber optic input PLL follows the local oscillator
14
FOBADFREQ
This bit set high when there is a large difference between the frequency of the reference
clock and the frequency of the VCO of the fiber optic input PLL. The low frequency
threshold is between 121 and 123MHz, and the high frequency threshold is between 127
and 129MHz. This indicator is disabled when "FSENSEDIS" bit is 1 or when the
filter of the PLL is being reset.
13
FEFDETECT
This bit set high when the Far End Fault (FEF) pattern is detected at the fiber optic input
interface
12
TPFORCELO
This bit set high when the twisted pair input PLL follows the local oscillator
11
TPBADFREQ
This bit set high when there is a large difference between the frequency of the reference
clock and the frequency of the VCO of the twisted pair input PLL. The low frequency
threshold is between 121 and 123MHz, and the high frequency threshold is between 127
and 129MHz. This indicator is disabled when "FSENSEDIS" bit is 1 or when the
filter of the PLL is being reset.
10
NOSEED
This bit set high when the descrambler is enabled and the seed is not updated for 1.3ms
to 2ms. This bit set low when the seed is updated. The high value is latched until it’s
read. Default is 0
9
TPLINKSTATUS
This bit set high when the twisted pair link is up. This bit is latched low until read. It only
applies to NON-TRANSPARENT Mode. It is always low in TRANSPARENT Mode
8
ANCOMPL
Auto-Negotiation Complete. This bit set high indicates that the Auto-Negotiation process
on the twisted pair link is completed. It only applies to NON-TRANSPARENT Mode. It is
always low in TRANSPARENT Mode
7
TPIN100
This bit set high indicates that 100Mbps signal is being detected at the twisted pair input
interface
6
TPIN10
This bit set high indicates that 10Mbps signal is being detected at the twisted pair input
interface
5
DATACTOF
This bit set high indicates that a data packet has been detected at the twisted pair input.
This bit is latched high until it’s read. This bit is always low if both TPIN10 and TPIN100
are low
4
FLP
3
FOIN100
This bit set high when 100BASE-FX or 100BASE-SX signal is being detected at the fiber
optic input interface
2
FOIN10
This bit set high when 10BASE-FL signal is being detected at the fiber optic input
interface
1
DATAFTOC
0
FLNP
23
This bit set high, when FLP Bursts are detected at the twisted pair input interface. It is
also set high when FLNP Bursts are detected at the twisted pair interface when PECL
mode is selected for it
This bit set high when a data packet has been detected at the fiber optic input. This bit is
latched high until it’s read. This bit is always low if both FOIN10 and FOIN100 are off
This bit set high when FLNP Bursts are detected at the fiber optic input interface
Final Datasheet
DS110415
ML6652
ELECTRICALCHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
OPERATING CONDITIONS
Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional
device operation is not implied.
Power Supply Voltage Range ............................ 3.3V ±5%
All VCC supply pins must be within 0.1V of each other
Operating Temperature Range .........................................
ML6652CH/ML6652CM ............................... 0°C to 70°C
ML6652EH/ML6652EM ............................ -20°C to 85°C
Junction Temperature ............................................. 150°C
Storage Temperature Range ..................... -65°C to 150°C
Lead Temperature (Soldering, 10s) ......................... 240°C
Thermal Resistance (θJA) ......................... 56°C/W(TQPF)
Thermal Resistance (θJA) ................ 33°C/W(LPCC/QFN)
Input Voltage Range ............ Ground - 0.3V to VCC +0.3V
Output Current
TPOUTP/TPOUTN ............................................... 80mA
IOUT ................................................................ 120mA
IOUT# ............................................................. -100mA
All other inputs ................................................... 10mA
ELECTRICAL TABLES
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Supply current transmitting
RTTP= 2KΩ
100BASE-TX and 100BASE-SX data packets
RTOP=1.4KΩ
Current into all VCC pins
150
200
mA
Supply current transmitting 10BASE-T and RTTP= 2KΩ
10BASE-FL data packets
RTOP=1.4KΩ
Current into all VCC pins
100
120
mA
POWER SUPPLY CURRENT
Power Down mode current
RTTP= 2KΩ
RTOP=1.4KΩ
Current into all VCC pins
2
mA
Supply current transmitting 100Mbps signal RTTP= 2KΩ
with 2 PECL interfaces
RTOP=1.4KΩ
Current into all VCC pins
120
150
mA
Supply current transmitting 10Mbps signal
with 2 PECL interfaces
60
100
mA
RTTP= 2KΩ
RTOP=1.4KΩ
Current into all VCC pins
TTL INPUTS: MDC AND MDIO
Input High Voltage
2
Input Low Voltage
V
0.8
V
Input High Leakage Current
VIN = 2.4V
-10
10
µA
Input Low Leakage Current
VIN = .4V
-10
10
µA
TTL OUTPUTS: MDIO, FOINSPD, TPINSPD, AND BCKPLINK#
Output High Voltage
Sourcing 2mA
Output Low Voltage
Sinking 2mA
2.4
V
0.4
V
CMOS INPUTS: REFCLK, PWRDWN#, TPOUTOFF#, AND FOUTOFF#
Input High Voltage
2
Input Low Voltage
24
V
0.8
V
Input High Leakage Current
VIN = 2.4V
-10
10
µA
Input Low Leakage Current
VIN = 0.4V
-10
10
µA
Final Datasheet
DS110415
ML6652
ELECTRICALTABLES (CONTINUED)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
3-LEVEL CONFIGURATION INPUTS: SPEED AND DUPLEX
High Input Level
0.9 x VCCD
VCCD
V
Middle Input Level
0.4 x VCCD
0.6 x VCCD
V
0 (GNDD)
0.1 x VCCD
V
High Input Level
0.9 x VCCD
VCCD
V
Middle High Input Level
0.6 x VCCD
0.8 x VCCD
V
Middle Low Input Level
0.2 x VCCD
0.4 x VCCD
V
0 (GNDD)
0.1 x VCCD
V
4.1
mA
10
µA
4.1
mA
-10
10
µA
Input High Voltage
VCC-1.225
VCC
V
Input Low Voltage
1.5
VCC-1.3
V
Differential Input High Voltage
200
Low Input Level
4-LEVEL CONFIGURATION INPUTS: PECLTP, PECLQU, AF4LIW, AD32, AD10
Low Input Level
STATUS LED OUTPUTS PIN 43 AND PIN 44
Output “On” Current (Voltage at pin = 0.7V & VCC-0.7V)
Output “Off” Current (Voltage at pin = 0.7V & VCC-0.7V)
3
-10
STATUS LED OUTPUTS PIN 41 AND PIN 42
Output “On” Current (Voltage at pin = 0.7V & VCC-0.7V)
Output “Off” Current (Voltage at pin = 0.7V & VCC-0.7V)
3
PECL/LVPECL COMPATIBLE INPUTS: TPINP, TPINN, FOINP, FOINN
Differential Input Low Voltage
mV
-200
mV
Input High Current
0
100
mA
Input Low Current
-100
0
µA
Input High Voltage
VCC-1.225
VCC
V
Input Low Voltage
1.5
VCC-1.3
V
Differential Input High Voltage
250
PECL/LVPECL COMPATIBLE INPUTS: REQSD, SDFO, SDTH
Differential Input Low Voltage
mV
-250
mV
Input High Current
0
100
mA
Input Low Current
-100
0
µA
PECL/LVPECL COMPATIBLE OUTPUTS: TPOUTP, TPOUTN, IOUT, IOUT#
25
Output High Voltage
With recommended resistor
network. Refer to pin description
VCC-0.96
5.3
V
Output Low Voltage
With recommended resistor
network. Refer to pin description
1.3
VCC-1.73
V
Differential Output Current
With recommended resistor
network. Refer to pin description
9.5
11.5
mA
Differential Output Current Imbalance
With recommended resistor
network. Refer to pin description
-0.1
0.1
mA
Final Datasheet
DS110415
ML6652
ELECTRICALTABLES (CONTINUED)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCC-1.0
VCC-0.4
V
TWISTED PAIR RECEIVER: TPINP, TPINN, REQSD
Common-Mode Voltage
Differential Input Resistance
Between TPINP and TPINN
1.8
2.8
KΩ
REQSD Input Current
5KΩ to ground, 25°C
110
330
µA
19
23
mA
TWISTED PAIR TRANSMITTER: TPOUTP, TPOUTN, RTTP
Differential Peak Output Current
100BASE-TX, RTTP = 2KΩ
Differential Current Error
100BASE-TX, RTTP = 2KΩ
Differential Peak Output Current
Transmitting 10BASE-T Packets,
RTTP = 2KΩ
35
55
mA
Average Total Output Current
[I(TPoutP)+I(TPoutN)]/2
Transmitting 10BASE-T Packets,
RTTP = 2KΩ
65
140
mA
Off State Output Current
Twisted Pair Transmitter Turned Off
10
µA
RTTP Input Current
RTTP=2KΩ
0.6
mA
±1
mA
FIBER OPTIC RECEIVER: FOINP, FOINN, CQOS
Common-Mode Voltage
Differential Input Resistance
VCC-1.35
V
900
Ω
FIBER OPTIC TRANSMITTER: IOUT, IOUT#, RTOP
High Light State Output Current
RTOP = 1.4KΩ
100
mA
Low Light State Output Current
RTOP = 1.4KΩ
10
mA
Off-State Output Current
Fiber Optic Transmitter Turned Off
±10
µA
MANAGEMENT INTERFACE
tCPER
Period of clock at MDC
1.4V Crossing
80
ns
tCPW
Pulse Width of clock at MDC
1.4V Crossing
30
ns
MDIO Data Valid Before MDC
Rising Edge Write Setup Time
1.4V Crossing
10
ns
tSPWH
MDIO Data Valid After MDC
Rising Edge Write Hold Time
1.4V Crossing
10
ns
tSPRS
MDIO Data Valid Before MDC
Rising Edge Read Setup Time
1.4V Crossing
30
ns
tSPRH
MDIO Data Valid After MDC Rising
Edge Read Hold Time
1.4V Crossing
0
ns
TSPWS
DESCRAMBLER
Synchronization update timer
100Mbps
1.3
2
ms
Twisted Pair Input to Fiber Optic Output
10Mbps
100
ns
Twisted Pair Input to Fiber Optic Output
100Mbps
100
ns
Fiber Optic Input to Twisted Pair Output
10Mbps
100
ns
Fiber Optic Input to Twisted Pair Output
100Mbps
100
ns
LATENCY
REFERENCE CLOCK: REFCLK
Frequency Tolerance
25MHz Nominal
-100
+100
ppm
PECL/LVPECL COMPATIBLE OUTPUTS: TPOUTP, TPOUTN, IOUT, IOUT#
Differential Rise and Fall Time
26
10 to 90%, 5pF at each pin 100BASE-SX
Final Datasheet
3
ns
DS110415
ML6652
ELECTRICALTABLES (CONTINUED)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
TWISTED PAIR RECEIVER: TPINP AND TPINN
Signal Detect Assertion Threshold
100BASE-TX
0.8
Vp-p
Signal Detect De-assertion Threshold
100BASE-TX
0.4
Vp-p
Amplitude Sensitivity Threshold
Link pulses
0.52
Vp
Packet Activity Assertion Threshold
10BASE-T
0.55
Vp
Packet Activity De-assertion Threshold
10BASE-T
0.42
Vp
3
ns
Low bandwidth, 10Mbps, Short Wave Length
6
mV
Low bandwidth, 10Mbps, Long Wave Length
10
mV
High bandwidth, 100Mbps, Short Wave Length
15
mV
High bandwidth, 100Mbps, Long Wave Length
10
mV
Short link distance (300m, High
bandwidth path, 10 or 100Mbps)
15
mV
10Mbps or Auto-Negotiation
20
%
100Mbps
35
%
0.1
mV
10BASE-FL
50
µV
100BASE-SX
150
µV
10BASE-FL
35
MHz
100BASE-SX
180
MHz
TWISTED PAIR TRANSMITTER: TPOUTP AND TPOUTN
Differential Rise and Fall Time 10 to 90% 100BASE-TX, 50Ω resistors to VCC
Transmitting unscrambled “H” symbols
FIBER OPTIC RECEIVER: FOINP AND FOINN
Signal Detect Assertion Threshold
Signal Detect Assertion Threshold (continued)
Voltage Threshold Hysteresis
Input Referred Offset
Input Referred Noise
FIBER OPTIC RECEIVER: FOINP AND FOINN
Input Amplifier –3 dB Bandwidth
27
Final Datasheet
DS110415
ML6652
PHYSICAL DIMENSIONS
inches
(millimeters)
Package: H44-10
44-Pin (10 x 10 x 1mm) TQFP
0.472 BSC
(12.00 BSC)
0.394 BSC
(10.00 BSC)
0º - 8º
0.003 - 0.008
(0.09 - 0.20)
34
1
PIN 1 ID
0.394 BSC
(10.00 BSC)
0.472 BSC
(12.00 BSC)
0.018 - 0.030
(0.45 - 0.75)
23
12
0.032 BSC
(0.80 BSC)
0.012 - 0.018
(0.29 - 0.45)
SEATING PLANE
0.048 MAX
(1.20 MAX)
0.037 - 0.041
(0.95 - 1.05)
44-PIN (7 x 7 x 1mm) LPCC
5.00 BSC
7.00 ± 0.10
0.50 BSC
44
1
0.30-0.5
PIN 1 ID
33
EXPOSED PAD
5.8 x 5.8 BSC
7.00 ± .010
11
TOP VIEW
22
0.18-0.30
BOTTOM VIEW
SIDE VIEW
ORDERING INFORMATION
PART NUMBER
TEMPERATURERANGE
PACKAGE
DATASHEET
PUBLICATION DATE
ML6652CH
0°C to 70°C
44 Pin TQFP
DS110415
JApril, 2011
ML6652EH
-20°C to 85°C
44 Pin TQFP
DS110415
JApril, 2011
ML6652CM
0°C to 70°C
44 Pin LPCC/QFN
DS110415
J April, 2011
ML6652EM
-20°C to 85°C
44 Pin LPCC/QFN
DS110415
J April, 2011
Headquarters: 2050 Concourse Drive, San Jose, CA 95131 (408) 433-5200 www.microlinear.com
28
Final Datasheet
DS110415
工商网监
湘ICP备2023018690号
