RF2051TR13

RF2051 RF2051 HIGH PERFORMANCE WIDEBAND RF PLL/VCO WITH INTEGRATED RF MIXERS Package: QFN, 32-Pin, 5mmx5mm   VCO 30MHz to 2.5GHz Frequency Range Fractional-N Synthesizer Synth Very Fine Frequency Resolution 1.5Hz for 26MHz Reference Mux Frac-N sequence generator N divider On-Chip Crystal-Sustaining Circuit With Programmable Loading Capacitors Charge pump Phase / freq detector  Two High-Linearity RF Mixers Ref divider  Integrated LO Buffers  Mixer Input IP3 +18dBm     Low Phase Noise VCO Mixer Bias Adjustable for Low Power Operation Full Duplex Mode  2.7V to 3.6V Power Supply  LO divider Functional Block Diagram   LO divider Mixers Features Low Current Consumption 55mA to 75mA at 3V 3-Wire Serial Interface Applications  CATV Head-Ends  Digital TV Up/Down Converters  Digital TV Repeaters  Multi-Dwelling Units  Cellular Repeaters  Frequency Band Shifters  UHF/VHF Radios  Diversity Receivers  Software Defined Radios  Satellite Communications  Super-Heterodyne Radios Product Description The RF2051 is a low power, high performance, wideband RF frequency conversion chip with integrated local oscillator (LO) generation and a pair of RF mixers. The RF synthesizer includes an integrated fractional-N phase locked loop with voltage controlled oscillators (VCOs) and dividers to produce a low-phase noise LO signal with a very fine frequency resolution. The buffered LO output drives the built-in RF mixers which convert the signal into the required frequency band. The mixer bias current can be programmed dependent on the required performance and available supply current. The LO generation blocks have been designed to continuously cover the frequency range from 300MHz to 2400MHz. The RF mixers are very broad band and operate from 30MHz to 2500MHz at the input and output, enabling both up and down conversion. An external crystal of between 10MHz and 52MHz or an external reference source of between 10MHz and 104MHz can be used with the RF2051 to accommodate a variety of reference frequency options. All on-chip registers are controlled through a simple three-wire serial interface. The RF2051 is designed for 2.7V to 3.6V operation for compatibility with portable, battery powered devices. It is available in a plastic 32-pin, 5mmx5mm QFN package. Optimum Technology Matching® Applied GaAs HBT GaAs MESFET InGaP HBT SiGe BiCMOS Si BiCMOS SiGe HBT GaAs pHEMT Si CMOS GaN HEMT RF MEMS Si BJT RF MICRO DEVICES®, RFMD®, Optimum Technology Matching®, Enabling Wireless Connectivity™, PowerStar®, POLARIS™ TOTAL RADIO™ and UltimateBlue™ are trademarks of RFMD, LLC. BLUETOOTH is a trademark owned by Bluetooth SIG, Inc., U.S.A. and licensed for use by RFMD. All other trade names, trademarks and registered trademarks are the property of their respective owners. ©2006, RF Micro Devices, Inc. DS140110 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. 1 of 39 RF2051 Detailed Functional Block Diagram CONTROL ANA_VDD ENBL MODE RESETB DIG_VDD IP1 RFIP1N RFIP1P ANA_DEC 1:1 ANA_VDD SERIAL BUS SDATA SCLK ENX RFOP1P Analog Regulator Serial Data Interface, Control and Biasing RFOP1N Mixer 1 REXT INDN VCO 3 OP1 Digital Regulator 4:1 LO Divider 1 /1, /2, or /4 Voltage Controlled Oscillators INDP LO Buffer 1 LFILT3 Vtune VCO 2 VCO 1 Mux Synthesizer LFILT2 Frac-N Sequence Generator N Divider Charge Pump Phase / Freq Detector Vref - + LFILT1 LO Buffer 2 LO Divider 2 /1, /2, or /4 ANA_VDD Mixer 2 RFOP2P XTALIPP Reference Oscillator Circuitry and Crystal Tuning OP2 Reference Divider /1 to /7 RFOP2N 4:1 XTALIPN RFIP2P IP2 RFIP2N 1:1 Pin Out SDATA SCLK ENX RESETB RFOP2P RFOP2N NC NC 2 of 39 32 31 30 29 28 27 26 25 ENBL 1 24 RFIP2P INDP 2 23 RFIP2N INDN 3 22 ANA_VDD REXT 4 ANA_DEC 5 20 NC LFILT1 6 19 DIG_VDD LFILT2 7 18 RFOP1P LFILT3 8 17 RFOP1N 21 NC 9 10 11 12 13 14 15 16 MODE XTALIPP XTALIPN GND RFIP1P RFIP1N NC NC EP 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. DS140110 RF2051 Pin 1 Function ENBL 2 INDP 3 INDN 4 REXT 5 6 7 8 9 10 11 ANA_DEC LFILT1 LFILT2 LFILT3 MODE XTALIPP XTALIPN 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 EP GND RFIP1P RFIP1N NC NC RFOP1N RFOP1P DIG_VDD NC NC ANA_VDD RFIP2N RFIP2P NC NC RFOP2N RFOP2P RESETB ENX SCLK SDATA Exposed pad Description Ensure that the ENBL high voltage level is not greater than VDD. An RC low-pass filter could be used to reduce digital noise. VCO 3 differential inductor. Normally a micro-strip inductor is used to set the VCO 3 frequency range 1200MHz to 1600MHz. VCO 3 differential inductor. Normally a micro-strip inductor is used to set the VCO 3 frequency range 1200MHz to 1600MHz. External bandgap bias resistor. Connect a 51k resistor from this pin to ground to set the bandgap reference bias current. This could be a sensitive low frequency noise injection point. Analog supply decoupling capacitor. Connect to analog supply and decouple as close to the pin as possible. Phase detector output. Low-frequency noise-sensitive node. Loop filter op-amp output. Low-frequency noise-sensitive node. VCO control input. Low-frequency noise-sensitive node. Mode select pin. An RC low-pass filter can be used to reduce digital noise. Reference crystal / reference oscillator input. Should be AC-coupled if an external reference is used. See note 3. Reference crystal / reference oscillator input. Should be AC-coupled to ground if an external reference is used. See note 3. Connect to ground. Differential input 1. See note 1. Differential input 1. See note 1. Differential output 1. See note 2. Differential output 1. See note 2. Digital supply. Should be decoupled as close to the pin as possible. Analog supply. Should be decoupled as close to the pin as possible. Differential input 2. See note 1. Differential input 2. See note 1. Differential output 2. See note 2. Differential output 2. See note 2. Chip reset (active low). Connect to DIG_VDD if external reset is not required. Serial interface select (active low). An RC low-pass filter could be used to reduce digital noise. Serial interface clock. An RC low-pass filter could be used to reduce digital noise. Serial interface data. An RC low-pass filter could be used to reduce digital noise. Connect to ground. This is the ground reference for the circuit. All decoupling should be connected here through low impedance paths. Note 1: The signal should be connected to this pin such that DC current cannot flow into or out of the chip, either by using AC coupling capacitors or by use of a transformer (see evaluation board schematic). Note 2: DC current needs to flow from ANA_VDD into this pin, either through an RF inductor, or transformer (see evaluation board schematic). Note 3: Alternatively an external reference can be AC-coupled to pin 11 XTALIPN, and pin 10 XTALIPP decoupled to ground. This may make PCB routing simpler. DS140110 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. 3 of 39 RF2051 Absolute Maximum Ratings Parameter Supply Voltage (VDD) Input Voltage (VIN), any Pin Rating Unit -0.5 to +3.6 V -0.3 to VDD +0.3 V +15 dBm Operating Temperature Range -40 to +85 °C Storage Temperature Range -65 to +150 °C RF/IF Mixer Input Power Parameter Min. Specification Typ. Max. Unit Condition ESD Requirements Human Body Model General 2000 V RF Pins 1000 V Machine Model General 200 V RF Pins 100 V Operating Conditions Supply Voltage (VDD) 2.7 3.6 V Temperature (TOP) -40 3.0 +85 °C Input Low Voltage -0.3 +0.5 V Logic Inputs/Outputs VDD =Supply to DIG_VDD pin Input High Voltage VDD / 1.5 VDD V Input Low Current -10 +10 uA Input=0V Input High Current -10 +10 uA Input=VDD Output Low Voltage 0 0.2*VDD V Output High Voltage 0.8*VDD VDD Load Resistance 10 V k Load Capacitance 20 pF Static Programmable Supply Current (IDD) Low Current Setting 55 mA High Linearity Setting 75 mA Only one mixer operating. 3 mA Reference oscillator and bandgap only. 140 A Standby Power Down Current Mixer 1/2 Gain Only one mixer operating. ENBL=0 and REF_STBY=0 Mixer output driving 4:1 balun. -2 dB Low Current Setting 9.5 dB High Linearity Setting 12 dB Not including balun losses. Noise Figure 4 of 39 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. DS140110 RF2051 Parameter Min. Specification Typ. Max. Unit Condition Mixer 1/2, cont. IIP3 Low Current Setting +10 dBm High Linearity Setting +18 dBm Low Current Setting +2 dBm High Linearity Setting +12 Pin1dB RF and IF Port Frequency Range 30 Mixer Input Return Loss dBm 2500 MHz 10 dB 2GHz LO Frequency -130 dBc/Hz 1GHz LO Frequency -135 dBc/Hz 500MHz LO Frequency -140 dBc/Hz 100 differential Voltage Controlled Oscillator Open Loop Phase Noise at 1MHz Offset Reference Oscillator Xtal Frequency 10 52 MHz External Reference Frequency 10 104 MHz Reference Divider Ratio 1 7 External Reference Input Level 500 800 1500 mVP-P AC-coupled 2400 MHz Dependant on VCO 3 external inductor. After LO dividers. 52 MHz Local Oscillator Synthesizer Output Frequency 300 Phase Detector Frequency Closed Loop Phase-Noise at 10kHz Offset 26MHz phase detector frequency 2GHz LO Frequency -90 dBc/Hz 1GHz LO Frequency -95 dBc/Hz 500MHz LO Frequency -102 dBc/Hz DS140110 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. 5 of 39 RF2051 Typical Performance Characteristics: Synthesizer and VCO - VDD =3V, TA =25°C, as measured on RF2051 evaluation board, for application schematic see page 36. Phase Detector Frequency=26MHz, Loop Bandwidth=60kHz. VCO1 With Active Loop Filter VCO1 With Passive Loop Filter -60 -60 2000MHz 1000MHz 500MHz -80 Phase Noise (dBc/Hz) Phase Noise (dBc/Hz) -80 -100 -120 -140 -160 10 100 1000 -140 1 10 100 1000 10000 Offset Frequency (kHz) Offset Frequency (kHz) VCO2 With Active Loop Filter VCO2 With Passive Loop Filter -60 1600MHz 800MHz 400MHz -100 -120 -140 1600MHz 800MHz 400MHz -80 Phase Noise (dBc/Hz) -80 Phase Noise (dBc/Hz) -120 10000 -60 -100 -120 -140 -160 -160 1 10 100 1000 1 10000 10 100 1000 Offset Frequency (kHz) Offset Frequency (kHz) VCO3 With Active Loop Filter VCO3 With Passive Loop Filter 10000 -60 -60 1200MHz 600MHz 300MHz -100 -120 -140 1200MHz 600MHz 300MHz -80 Phase Noise (dBc/Hz) -80 Phase Noise (dBc/Hz) -100 -160 1 -100 -120 -140 -160 -160 1 10 100 1000 Offset Frequency (kHz) 6 of 39 2000MHz 1000MHz 500MHz 10000 1 10 100 1000 10000 Offset Frequency (kHz) 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. DS140110 RF2051 Typical Performance Characteristics: Synthesizer and VCO - VDD =3V, TA =25°C unless stated, as measured on RF2051 evaluation board, for application schematic see page 36. V C O1 Tun in g Ga in versu s Frequ en cy VCO1 Open Loop Phase Noise 50 -20 2400MHz 2200MHz 2000MHz 45 40 Tuning Gain (MHz/V) Phase Noise (dBc/Hz) -40 -60 -80 -100 -120 35 30 25 20 15 10 -140 5 -160 0 1 10 100 1000 10000 1900 2200 2300 2400 VCO2 Open Loop Phase Noise VCO2 Tuning Gain versus Frequency 2500 40 2000MHz 1800MHz 1600MHz 35 Tuning Gain (MHz/V) -40 Phase Noise (dBc/Hz) 2100 F V CO (M Hz) -20 -60 -80 -100 -120 -140 30 25 20 15 10 5 -160 0 1 10 100 1000 10000 1500 1600 1700 1800 1900 2000 Offset Frequency (kHz) FVCO (MHz) VCO3 Open Loop Phase Noise VCO1 F VCO versus V T for the same coarse tune setting 2095 -20 1600MHz 1400MHz 1200MHz -40 2100 2090 2085 -60 2080 FVCO (MHz) Phase Noise (dBc/Hz) 2000 Offset Frequency (kHz) -80 -100 2075 2070 2065 2060 -120 2055 -140 -40 2050 -160 80 2045 1 10 100 1000 Offset Frequency (kHz) DS140110 10000 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 V T (V) 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. 7 of 39 RF2051 Typical Performance Characteristics: RF Mixers - VDD =3V, TA =25°C unless stated, as measured on RF2051 evaluation board, for application schematic see page 36. Gain versus Temperature and Supply Voltage Mixer 1 Conversion Gain, IF Output=100MHz (excluding losses in PCB and Baluns) 0.0 0 2.7V 3.0V 3.6V -1 -0.5 Conversion Gain (dB) -2 -3 -1.0 Gain (dB) -4 -5 -6 -2.0 -7 -8 -40°C +27°C +85°C -9 -2.5 -10 250 -1.5 -3.0 500 750 1000 1250 1500 1750 -40 -20 0 RF Input Frequency (MHz) 20 40 60 80 100 Temperature (°C) Operating Current, One Mixer Enabled versus Temperature and Supply Voltage 80 Supply Current (mA) 75 70 -40°C, +2.7V -40°C, +3.0V -40°C, +3.6V +27°C, +2.7V +27°C, +3.0V +27°C, +3.6V +85°C, +2.7V +85°C, +3.0V +85°C, +3.6V 65 60 55 50 001 010 011 100 101 Mixer Bias Current Setting (MIX_IDD) RF2051 Typical Operating Current in mA in Full Duplex Mode (both mixers enabled) MIX1_IDD 001 010 011 100 101 8 of 39 001 010 MIX2_IDD 011 100 70 75 80 85 90 75 81 86 91 95 101 81 86 91 96 101 86 91 97 101 106 92 97 102 107 112 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. DS140110 RF2051 Typical Performance Characteristics: RF Mixers - VDD =3V, TA =25°C unless stated, as measured on RF2051 evaluation board, for application schematic see page 36. Mixer 1 Noise Figure versus Temperature IF Output=100MHz and MIX1_IDD=100 15 Mixer 1 Input IP3 versus Bias Current Setting 30 14 25 Input IP3 (dBm) Noise Figure (dB) 13 12 11 10 9 8 20 15 10 500MHz RF to 100MHz IF 7 -40°C +27°C +85°C 6 5 900MHz RF to 100MHz IF 2000MHz RF to 500MHz IF 5 0 250 500 750 1000 1250 1500 1750 001 010 RF Input Frequency (MHz) Mixer 1 Noise Figure versus Bias Current IF Output=100MHz 20.6 14 20.4 13 20.2 12 11 10 9 8 101 IIP3 versus Temperature and Supply Voltage (Max Linearity) 2.7V 3.0V 3.6V 6 19.8 19.6 19.4 MIX1_IDD = 001 MIX1_IDD = 010 MIX1_IDD = 011 MIX1_IDD = 100 MIX1_IDD = 101 7 19.2 19.0 5 18.8 250 500 750 1000 1250 1500 1750 -40 -20 0 RF Input Frequency (MHz) 20 40 60 80 100 Temperature (°C) NF versus Temperature and Supply Voltage (Low Noise Mode MIX1_IDD=001)) 11.0 14 10.5 Mixer 1 Input Power for 1dB Compression versus Temperature and Bias Current Setting IF Output=100MHz Pin 1dB (dBm) 12 10.0 NF (dB) 100 20.0 IIP3 (dBm) Noise Figure (dB) 15 011 Bias Current Setting (MIX1 IDD) 9.5 9.0 2.7V 3.0V 3.6V 8.5 8.0 -40 -20 0 20 40 Temperature (°C) DS140110 60 80 100 10 8 6 -40 Deg C, 001 +27 Deg C, 001 +85 Deg C, 001 -40 Deg C, 011 +27 Deg C, 011 +85 Deg C, 011 -40 Deg C, 101 +27 Deg C, 101 +85 Deg C, 101 4 2 0 -2 250 500 750 1000 1250 1500 1750 RF Input Frequency (MHz) 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. 9 of 39 RF2051 Typical Performance Characteristics: RF Mixers - VDD =3V, TA =25°C unless stated, as measured on RF2051 evaluation board, for application schematic see page 36. Mixer 1 Typical RF and LO Leakage at IF Output Mixer 2 Typical RF and LO Leakage at IF Output 0 0 -10 IF Output at 100MHz RF Leakage LO Leakage (High Side) -20 -30 -40 -50 -60 -70 250 500 750 1000 1250 1500 Level at Mixer 2 Output (dBm) Level at Mixer 1 Output (dBm) -10 -20 -30 -40 -50 IF Output at 100MHz RF Leakage LO Leakage (High Side) -60 -70 1750 250 500 RF Input Frequency (MHz) 750 1000 Mixer 1 Typical IF and LO Leakage at RF Input 1750 0 100MHz IF Leakage to RF Port -10 100MHz IF Leakage to RF Port -10 LO Leakage (High Side) to RF -20 Level at Mixer 2 Input (dBm) Level at Mixer 1 Input (dBm) 1500 Mixer 2 Typical IF and LO Leakage at RF Input 0 -30 -40 -50 -60 -70 -80 250 500 750 1000 1250 1500 1750 LO Leakage (High Side) to RF -20 -30 -40 -50 -60 -70 -80 250 500 RF Input Frequency (MHz) 1250 1500 1750 -30 -40 90 Isolation (dB) -20 1000 Full Duplex Mode Typical Isolation Between Mixers 100 -40°C, Path 1 -40°C, Path 2 +27°C, Path 1 +27°C, Path 2 +85°C, Path 1 +85°C, Path 2 -10 750 RF Input Frequency (MHz) Mixer Typical LO Leakage at IF Output IF Output=100MHz 0 LO Leakage (dBm) 1250 RF Input Frequency (MHz) 80 70 -50 60 -60 -70 50 0 500 1000 1500 2000 RF Input Frequency (MHz) 10 of 39 2500 0 500 1000 1500 2000 2500 RF Frequency (MHz) 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. DS140110 RF2051 Detailed Description The RF2051 is a wideband RF frequency converter chip which includes a fractional-N phase-locked loop, a crystal oscillator circuit, a low noise VCO core, a LO signal multiplexer, two buffer circuits and two RF mixers. Synthesizer programming, device configuration and control are achieved through a mixture of hardware and software controls. All on-chip registers are programmed through a simple three-wire serial interface. VCO The VCO core in the RF2051 consists of three VCOs which, in conjunction with the integrated 2/4 LO divider, cover the LO range from 300MHz to 2400MHz. VCO Tank Inductor VCO Frequency Range DIV 2 DIV 4 1 Internal 1800MHz to 2400MHz 900MHz to 1200MHz 450MHz to 600MHz 2 Internal 1500MHz to 2100MHz 750MHz to 1050MHz 375MHz to 525MHz 3 External 1200MHz to 1600MHz* 600MHz to 800MHz 300MHz to 400MHz *The frequency of VCO3 is set by external inductors and can be varied by the user. VCO 1, 2, and 3 are selected using the PLL1x0:P1_VCOSEL and PLL2x0:P2_VCOSEL control words. Each VCO has 128 overlapping bands to achieve an acceptable VCO gain (20MHz/V nom) and hence a good phase noise performance across the whole tuning range. The chip automatically selects the correct VCO band ("VCO coarse tuning") to generate the desired LO frequency based on the values programmed into the PLL1 and PLL2 registers banks. For information on how to program the desired LO frequency into the PLL1 and PLL2 banks refer to page 12. The automatic VCO band selection is triggered every time the ENBL pin is taken high. Once the band has been selected the PLL will lock onto the correct frequency. During the band selection process fixed capacitance elements are progressively connected to the VCO resonant circuit until the VCO is oscillating at approximately the correct frequency. The output of this band selection is made available in the RB1:CT_CAL read-back register. A value of 127 or 0 in this register indicates that the selection was unsuccessful, this is usually due to the wrong VCO being selected so the user is trying to program a frequency that is outside of the VCO operating range. A value between 1 and 126 indicates a successful calibration, the actual value being dependent on the desired frequency as well as process variation for a particular device. The band selection takes approximately 1500 cycles of the phase detector clock (about 50us with a 26MHz clock). The band select process will center the VCO tuning voltage at about 1.2V, compensating for manufacturing tolerances and process variation as well as environmental factors including temperature. For applications where the synthesizer is always on and the LO frequency is fixed, the synthesizer will maintain lock over a +/-60°C temperature range. However it is recommended to re-initiate an automatic band selection for every 30 degrees change in temperature in order to maintain optimal synthesizer performance. This assumes an active loop filter. If start-up time is a critical parameter, and the user is always programming the same frequency for the PLL, the calibration result may be read back from the RB1:CT_CAL register, and written to the PLL1x2:P1_CT_DEF or PLL2x2:P2_CT_DEF registers (depending on desired PLL register bank). The calibration function must then be disabled by setting the PLL1x0:P1_CT_EN and/or PLL2x0:P2_CT_EN control words to 0. For further information please refer to the RF205x Calibration User Guide. When operating using VCO1 for frequencies above 2.2GHz, it is recommended to change the coarse tuning voltage setting, PLL1x5:P1_CT_V and PLL2x5:P2_CT_V, from the default value of 16 down to 12. The LO divide ratio is set by the PLL1x0:P1_LODIV and PLL2x0:P2_LODIV control words. The LO is routed to mixer1, mixer2, or both depending on the state of the MODE pin and the value of CFG1:FULLD. The current in the VCO core can be programmed using the PLL1x3:P1_VCOI or PLL2x3:P2_VCOI control words. This allows optimization of VCO performance for a particular frequency. For applications where the required LO frequency is above 2GHz it is recommended that the LO buffer current be increased by setting CFG5:LO1_I and CFG5:LO2_I to 1100 (hex value C). DS140110 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. 11 of 39 RF2051 Fractional-N PLL The IC contains a charge-pump based fractional-N phase locked loop (PLL) for controlling the three VCOs. The PLL includes automatic calibration systems to counteract the effects of process and environmental variations, ensuring repeatable locktime and noise performance. The PLL is intended to use a reference frequency signal of 10MHz to 104MHz. A reference divider (divide by 1 to divide by 7) is supplied and should be programmed to limit the frequency at the phase detector to a maximum of 52MHz. The reference divider bypass is controlled by bit CLK DIV_BYP, set low to enable the reference divider and set high for divider bypass (divide by 1). The remaining three bits CLK DIV set the reference divider value, divide by 2 (010) to 7 (111) when the reference divider is enabled. Two PLL programming banks are provided, the first bank is preceded by the label PLL1 and the second bank is preceded by the label PLL2. For the RF2051 these banks are used to program mixer 1 and mixer 2 respectively, and are selected automatically as the mixer is selected (using the MODE pin). The PLL will lock the VCO to the frequency FVCO according to: FVCO =NEFF*FOSC/R where NEFF is the programmed fractional N divider value, FOSC is the reference input frequency, and R is the programmed R divider value (1 to 7). The N divider is a fractional divider, containing a dual-modulus prescaler and a digitally spur-compensated fractional sequence generator to allow fine frequency steps. The N divider is programmed using the N and NUM bits as follows: First determine the desired, effective N divider value, NEFF: NEFF =FVCO*R/FOSC N(9:0) should be set to the integer part of NEFF. NUM should be set to the fractional part of NEFF multiplied by 224 =16777216. Example: VCO1 operating at 2220MHz, 23.92MHz reference frequency, the desired effective divider value is: NEFF =FVCO *R / FOSC =2220 *1 / 23.92=92.80936454849. The N value is set to 92, equal to the integer part of NEFF, and the NUM value is set to the fractional portion of NEFF multiplied by 224: NUM=0.80936454849 * 224 =13,578,884. Converting N and NUM into binary results in the following: N=0 0101 1100 NUM=1100 1111 0011 0010 1000 0100 So the registers would be programmed: P1_N (or P2_N)=0 0101 1100 P1_NUM_MSB (or P2_NUM_MSB)=1100 1111 0011 0010 P1_NUM_LSB (or P2_NUM_LSB)=1000 0100 The maximum NEFF is 511, and the minimum NEFF is 15, when in fractional mode. The minimum step size is FOSC/R*224. Thus for a 23.92MHz reference, the frequency step size would be 1.4Hz. The minimum reference frequency that could be used to program a frequency of 2400MHz (using VCO1) is 2400/511, 4.697MHz (approx). 12 of 39 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. DS140110 RF2051 Phase Detector and Charge Pump The chip provides a current output to drive an external loop filter. An on-chip operational amplifier can be used to design an active loop filter or a passive design can be implemented. The maximum charge pump output current is set by the value contained in the P1_CP_DEF/P2_CP_DEF field and CP_LO_I. In the default state (P1_CP_DEF/P2_CP_DEF=31 and CP_LO_I=0) the charge pump current (ICPset) is 120uA. If CP_LO_I is set to 1 this current is reduced to 30uA. The charge pump current can be altered by changing the value of P1_CP_DEF/P2_CP_DEF. The charge pump current is defined as: ICP= ICPset*CP_DEF / 31 If automatic loop bandwidth correction is enabled the charge pump current is set by the calibration algorithm based upon the VCO gain. For more information on the VCO gain calibration, which is disabled by default, please refer to the RF205x Calibration User Guide. The phase detector will operate with a maximum input frequency of 52MHz. Note that for high phase detector frequencies, the divider ratio decreases. For N5ns t2 Programming setup time >5ns t3 Programming hold time >5ns t4 ENX setup time >5ns 16 of 39 Programming updates Time t5 ENX hold time >5ns t6 Data setup time >5ns t7 Data hold time >5ns t8 ENBL setup time >0ns t9 ENBL hold time >0ns 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. DS140110 RF2051 Write ENX SCLK SDATA X A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Initially ENX is high and SDATA is high impedance. The write operation begins with the controller starting SCLK. On the first falling edge of SCLK the baseband asserts ENX low. The second rising edge of SCLK is reserved to allow the SDI to initialize, and the third rising edge is used to define whether the operation will be a write or a read operation. In write mode the baseband will drive SDATA for the entire telegram. RF2051 will read the data bit on the rising edge of SCLK. The next 7 data bits are the register address, MSB first. This is followed by the payload of 16 data bits for a total write mode transfer of 24 bits. Data is latched into RF2051 on the last rising edge of SCLK (after ENX is asserted high). For more information, please refer to the timing diagram on page 16. The maximum clock speed for a register write is 19.2MHz. A register write therefore takes approximately 1.3us. The data is latched on the rising edge of the clock. The datagram consists of a single start bit followed by a ‘0’ (to indicate a write operation). This is then followed by a seven bit address and a sixteen bit data word. Note that since the serial bus does not require the presence of the crystal clock, it is necessary to insert an additional rising clock edge before the ENX line is set low to ensure the address/data are read correctly. Read ENX SCLK SDATA X A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Initially ENX is high and SDATA is high impedance. The read operation begins with the controller starting SCLK. The controller is in control of the SDATA line during the address write operation. On the first falling edge of SCLK the baseband asserts ENX low. The second rising edge of SCLK is reserved to allow the SDI to initialize, and the third rising edge is used to define whether the operation will be a write or a read operation. In read mode the baseband will drive SDATA for the address portion of the telegram, and then control will be handed over to RF2051 for the data portion. RF2051 will read the data bits of the address on the rising edge of SCLK. After the address has been written, control of the SDATA line is handed over to RF2051. One and a half clocks are reserved for turn-around, and then the data bits are presented by RF2051. The data is set up on the rising edge of SCLK, and the controller latches the data on the falling edge of SCLK. At the end of the data transmission, RF2051 will release control of the SDATA line, and the controller asserts ENX high. The SDATA port on RF2051 transitions from high impedance to low impedance on the first rising edge of the data portion of the transaction (for example, 3 rising edges after the last address bit has been read), so the controller chip should be presenting a high impedance by that time. For more information, please refer to the timing diagram on page 16. The maximum clock speed for a register read is 19.2MHz. A register read therefore takes approximately 1.4us. The address is latched on the rising edge of the clock and the data output on the falling edge. The datagram consists of a single start bit fol- DS140110 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. 17 of 39 RF2051 lowed by a ‘1’ (to indicate a read operation), followed by a seven bit address. A 1.5 bit delay is introduced before the sixteen bit data word representing the register content is presented to the receiver. Note that since the serial bus does not require the presence of the crystal clock, it is necessary to insert an additional rising clock edge before the ENX line is set low to ensure the address is read correctly. Hardware Control Three hardware control pins are provided: ENBL, MODE, and RESETB. ENBL Pin The ENBL pin has two functions: to enable the analog circuits in the chip and to trigger the VCO band selection as described in the VCO section on page 11. ENBL Pin REFSTBY Bit XO and Bias Block Analogue Block Digital Block Low 0 Off Off On Low 1 On Off On High 0 On On On High 1 On On On As outlined in the VCO section the chip has a built-in automatic VCO band selection to tune the selected VCO to the desired frequency. The band selection is initiated when the ENBL pin is taken high. Every time the frequency of the synthesizer is re-programmed, the ENBL has to be inserted high to initiate the automatic VCO band selection (VCO coarse tune). ENBL MODE Parameter Description Time t1 MODE setup time >5ns t2 MODE hold time >5ns t1 t2 RESETB Pin The RESETB pin is a hardware reset control that will reset all digital circuits to their start-up state when asserted low. The device includes a power-on-reset function, so this pin should not normally be required, in which case it should be connected to the positive supply. MODE Pin The MODE pin controls which mixer(s) and PLL programming register bank is active. See the PLL and Mixer description sections for details. 18 of 39 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. DS140110 RF2051 Programming the RF2051 The figure below shows an overview of the device programming. Device off Apply power Apply power to the device. Reset device Ensure the device is set into a known and correct state. 1 Set-up device operation 2 To use the device it will be necessary to program the registers with the desired contents to achieve the required operating characteristics. Set calibration mode See following sections for details. 3 Set operating frequencies 4 ENABLE device When programming is complete the device can be enabled. Note: The set-up processes 1 to 2, 2 to 3, and 3 to 4 are explained further below. Additional information on device use and programming can be found on the RF205X family page of the RFMD web site (http://www.rfmd.com/rf205x). The following documents may be particularly helpful: • RF205x Frequency Synthesizer User Guide • RF205x Calibration User Guide DS140110 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. 19 of 39 RF2051 Start-up When starting up and following device reset then REFSTBY=0, REFSTBY should be asserted high approximately 500s before ENBL is taken high. This is to allow the XO to settle and will depend on XO characteristics. The various calibration routines will also take some time depending on whether they are enabled or not. Coarse tuning calibration takes about 50s and VCO tuning gain compensation takes about 100s. Additionally, time for the PLL to settle will be required. All of these timings will be dependant upon application specific factors such as loop filter bandwidth, reference clock frequency, XO characteristics and so on. The fastest turn-on and lock time will be obtained by leaving REFSTBY asserted high, disabling all calibration routines, and setting the PLL loop bandwidth as wide as possible. The device can be reset into its initial state (default settings) at any time by performing a hard reset. This is achieved by setting the RESETB pin low for at least 100ns. Setting Up Device Operation The device offers a number of operating modes which need to be set up in the device before it will work as intended. This is achieved as follows. 1 Set-up device operation Disable active loop filter? Yes LF_ACT Set to 0 When setting up the device it is necessary to decide if an active or passive loop filter will be used in the phase locked loop. The LF_ACT bit is located in the CFG1 register and is active by default. Set the phase detector polarity bit in CFG1since the active filter inverts the loop filter voltage. Yes FULLD Set to 1 The user must then activate the full duplex mode of operation if fast frequency switching is required or it is necessary to have both mixers operating simultaneously. This bit is also located in the CFG1 register and is inactive by default. Default Full duplex operation? Default Program MIX1_IDD and MIX2_IDD Program XO_CT, XO_CR_S and CLK_DIV Set-up complete Mixer linearity The mixer linearity setting is then selected. The default value is 4 with 1 being the lowest setting and 5 the highest. The MIX1_IDD and MIX2_IDD bits are located in the CFG2 register. Internal capacitors used to set Xtal load The internal crystal loading capacitors are also programmed to present the correct load to the crystal. The capacitance internal to the chip can be varied from 8-16pF in 0.25pF steps (default=10pF). The reference divider must also be set to determine the phase detector frequency (default=1). These bits are located in the CFG4 register. 2 Three registers need to be written, taking 3.9us at the maximum clock speed. If the device is used with an active filter in simplex operation it will not be necessary to program CFG1 reducing the programming time to 2.6us. 20 of 39 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. DS140110 RF2051 Setting Up VCO Coarse Tuning and Loop Filter Calibration If the user wishes to disable the VCO coarse tune calibration or enable the loop filter calibration then the following programming operation will need to take place. 2 Set calibration mode Disable VCO coarse tune? Yes P1_CT_EN, P2_CT_EN Set to 00 When setting up the device it is necessary to decide whether to deactivate the devices' internal VCO calibration or provide the calibration information directly. These bits are located in the PLL1x0 and PLL2x0 registers and are active by default. Yes Loop filter calibration It is also necessary to decide whether to activate the loop filter calibration mode, only necessary when operating the device over very wide band of frequencies. These bits are also located in the PLL1x0 and PLL2x0 registers. The default setting assumes an active loop filter is used. Default Enable loop filter cal? Default Operating mode set 3 Two registers need to be written taking 2.6us at maximum clock speed if the course tuning is deactivated or the loop filter calibration activated. Since it is necessary to program these registers when setting the operating frequency (see next section) this operation usually carries no overhead. The coarse tune calibration takes approximately 50us when using a 26MHz reference clock (it will take proportionally longer if a slower clock is used, and vice versa). DS140110 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. 21 of 39 RF2051 Setting The Operating Frequency Setting the operating frequency of the device requires a number of registers to be programmed. 3 Set operating frequencies Program P1_VCOSEL, P2_VCOSEL, P1_LODIV and P2_LODIV Program P1_N, P2_N When programming the operating frequency it is necessary to select the appropriate VCO and LODIV values. The P1_VCOSEL and P1_LODIV bits are located in the PLL1x0 register and the corresponding P2 bits in the PLL2x0 register. If the LO frequency is above 2GHz the LO path current (CFG5) should be set to 0xC The integer part of the PLL division ratio is programmed into the PLL1x3 and PLL2x3 registers according to the required synthesizer path. Program P1_NUM_MSB, P2_NUM_MSB The MSB of the fractional part of the synthesizer PLL divider value is programmed into the PLL1x1 and PLL2x1 registers. Program P1_NUM_LSB, P2_NUM_LSB, P1_CT_DEF, P2_CT_DEF The LSB of the fractional part of the synthesizer PLL divider value is programmed into the PLL1x2 and PLL2x2 registers together with the CT_CAL bits if fast frequency switching is required. (Depending on required frequency resolution and coarse tune settings this may not be required.) Frequency programmed 4 A total of four registers must be programmed to set the device operating frequency for each path within the device. This will take 5.2us for each path at maximum clock speed. To change the frequency of the VCO it will be necessary to repeat these operations. However, if the frequency shift is small it may not be necessary to reprogram the VCOSEL and LODIV bits reducing the register writes to three per path. For an example on how to determine the integer and fractional parts of the synthesizer PLL division ratio please refer to the detailed description of the PLL on page 12. 22 of 39 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. DS140110 RF2051 Programming Registers Register Map Diagram Reg. Name Data R/W Add CFG1 R/W 00 LD_EN LD_LEV TVCO CFG2 R/W 01 MIX1_IDD MIX1_VB CFG3 R/W 02 TKV1 TKV2 CFG4 R/W 03 CLK_DIV_BYPASS XO_CT CFG5 R/W 04 LO1_I LO2_I CFG6 R/W 05 PLL1x0 R/W 08 PLL1x1 R/W 09 PLL1x2 R/W 0A P1_NUM_LSB PLL1x3 R/W 0B P1_N 15 14 13 12 11 10 8 7 6 PDP LF_ACT MIX2_IDD 5 4 CPL MIX2_VB 3 2 1 0 CT_POL Res EXT_VCO FULLD CP_LO_I Res KV_RNG NBR_CT_AVG Res FLL_FACT XO_I2 XO_I1 XO_CR_S NBR_KV_AVG CT_CPOLREFSTBY TCT T_PH_ALGN SU_WAIT P1_VCOSEL Res P1_CT_E P1_KV_E P1_LON N DIV Res P1_CP_DEF P1_NUM_MSB PLL1x4 R/W 0C P1_DN PLL1x5 R/W 0D P1_N_PHS_ADJ PLL2x0 R/W 10 PLL2x1 R/W 11 PLL2x2 R/W 12 P2_NUM_LSB PLL2x3 R/W 13 P2_N P2_VCOSEL P1_CT_DEF Res Res P1_VCOI P1_CT_GAIN P1_KV_GAIN Res P2_CT_E P2_KV__E P2_LON DIV N Res P1_CT_V Res P2_CP_DEF P2_NUM_MSB PLL2x4 R/W 14 P2_DN PLL2x5 R/W 15 P2_N_PHS_ADJ GPO R/W 18 CHIPREV R 19 RB1 R 1C RB2 R 1D RB3 R 1E TEST R 1F DS140110 9 Res P1_G- Res P1_ P1_ PO1 GPO GPO 3 4 P2_CT_DEF Res P2_CT_GAIN P2_GPO1 Res P2_G- P2_ PO3 GPO 4 CP_CAL Res V1_CAL RSM_STATE TMUX Res REVNO CT_CAL V0_CAL TEN Res P2_CT_V PARTNO LOCK P2_KV_GAIN Res Res Res P2_VCOI Res CPU CPD FNZ LDO TSEL _BY P Res DACTEST 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. Res 23 of 39 RF2051 CFG1 (OOh) - Operational Configuration Parameters # Bit Name Default LD_EN 1 14 LD_LEV 0 Modify lock range for lock detector 13 TVCO(4:0) 0 VCO warm-up time=TVCO/(FREF=256) 12 0 11 0 10 0 9 Enable lock detector circuitry 1 0 8 PDP 1 7 LF_ACT 1 6 CPL(1:0) 5 4 9 Function 15 Phase detector polarity: 0=positive, 1=negative C 1 Charge pump leakage current: 00=no leakage, 01=low leakage, 10=mid leakage, 11=high leakage 0 CT_POL 3 0 0 Active loop filter enable, 1=Active 0=Passive Polarity of VCO coarse-tune word: 0=positive, 1=negative 0 2 EXT_VCO 0 0=Normal operation 1=external VCO (VCO3 disabled, KV_CAL and CT_CAL must be disabled) 1 FULLD 0 0=Half duplex, mixer is enabled according to MODE pin, 1=Full duplex, both mixers enabled 0 CP_LO_I 0 0=High charge pump current, 1=low charge pump current CFG2 (O1h) - Mixer Bias and PLL Calibration # 15 Bit Name MIX1_IDD 14 0 1 MIX2_IDD 9 1 Mixer 2 current setting: 000=0mA to 111=35mA in 5mA steps 0 MIX2_VB 6 0 5 Mixer 2 voltage bias 8 Number of averages during CT cal 1 5 0 4 KV_RNG 1 3 NBR_CT_AVG 1 NBR_KV_AVG 0 2 1 Mixer 1 voltage bias. C 0 8 7 Function Mixer 1 current setting: 000=0mA to 111=35mA in 5mA steps 0 MIX1_VB 11 10 8 0 13 12 Default 1 Sets accuracy of voltage measurement during KV calibration: 0=8bits, 1=9bits 0 0 24 of 39 Number of averages during KV cal 0 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. DS140110 RF2051 CFG3 (O2h) - PLL Calibration # 15 Bit Name TKV1 Default 0 14 0 13 0 12 11 Settling time for first measurement in LO KV compensation 4 Settling time for second measurement in LO KV compensation 0 TKV2 0 10 1 9 0 8 0 7 0 6 0 5 0 4 3 Function 0 0 0 FLL_FACT 2 0 4 Default setting 01. Needs to be set to 00 for N