RF2667

RF2667 7 Typical Applications • CDMA/FM Cellular Systems • CDMA PCS Systems • GSM/DCS Systems • TDMA Systems • Spread-Spectrum Cordless Phones • Wireless Local Loop Systems RECEIVE AGC AND DEMODULATOR Product Description The RF2667 is an integrated complete IF AGC amplifier and quadrature demodulator developed for the receive section of dual-mode CDMA/FM cellular and PCS applications and for GSM/DCS and TDMA systems. It is designed to amplify received IF signals, while providing 100dB of gain control range, and demodulate to baseband I and Q signals. Noise figure, IP3, and other specifications are designed to be compatible with the IS-98, and J-STD-018 Interim Standard for CDMA cellular communications. This circuit is part of the RFMD line of complete solutions for digital radio applications. The IC is manufactured on an advanced 15GHz FT Silicon Bipolar process, and is packaged in a standard miniature 24-lead plastic QSOP package. Optimum Technology Matching® Applied 0.157 0.150 -A0.0098 0.0040 0.012 0.008 0.344 0.337 0.025 0.2440 0.2284 Dimensions in inches. 0.0688 0.0532 7 QUADRATURE DEMODULATORS 8° MAX 0° MIN 0.050 0.016 0.0098 0.0075 NOTES: 1. Shaded lead is Pin 1. 2. All dimensions are excluding mold flash. 3. Lead coplanarity: 0.005 with respect to datum "A". ü Package Style: QSOP-24 Si BJT Si Bi-CMOS GaAs HBT SiGe HBT GaAs MESFET Si CMOS Features • Similar to RF9957with Higher I/Q Output Voltage FL+ GC 23 19 • Supports Dual Mode Operation • Digitally Controlled Power Down Mode 16 Q OUT+ 15 Q OUT- CDMA IN+ 4 CDMA IN- 5 IN SEL 14 FM IN+ 8 FM IN- 9 Input Select Gain Control • 2.7V to 3.3V Operation • IF AGC Amp with 100dB Gain Control Quad. ÷2 13 LO+ 12 LO21 I OUT+ Band Gap Reference 22 I OUT- Ordering Information 24 PD 18 FL- 10 BG OUT RF2667 RF2667 PCBA Receive AGC and Demodulator Fully Assembled Evaluation Board Functional Block Diagram RF Micro Devices, Inc. 7625 Thorndike Road Greensboro, NC 27409, USA Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com Rev A14 010622 7-1 RF2667 Absolute Maximum Ratings Parameter Supply Voltage Power Down Voltage (VPD) Input RF Power Ambient Operating Temperature Storage Temperature Rating -0.5 to +5 -0.5 to VCC +0.7 +3 -40 to +85 -40 to +150 Unit VDC VDC dBm °C °C Caution! ESD sensitive device. RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s). Parameter Overall (Cascaded) Maximum Gain Minimum Gain Gain Variation Input IP3 Specification Min. Typ. Max. Unit Condition T=25 °C, VCC =3.0V, ZLOAD =5kΩ, LO=170MHz @400mVPP, IF Freq=85MHz, ZS =500 Ω (CDMA), ZS =850 Ω (FM) VGC =2.5V, FM or CDMA Input, Balanced VGC =0.5V, FM or CDMA Input, Balanced T=-20°C to +85°C, Ref = 25°C VGC =2.5V, Maximum Gain VGC =0.5V, Minimum Gain Gain = 35 dB, PIN=-61dBm VGC =2.5V, Maximum Gain VGC=0.5V, Minimum Gain FM or CDMA, Balanced FM or CDMA, Single-ended +45 -3 -54 -7 -39 +50 -55 -50 -4 -36 5 70 70 to 230 2400 1200 0.1 1 2.4 1200 2400 2.0 20 140 to 460 400 800 400 3.0 20 20 -50 +3 7 QUADRATURE DEMODULATORS Noise Figure IF Input Frequency Range IF Input Impedance I/Q Frequency Range I/Q Amplitude Balance I/Q Phase Balance Max I/Q Output Voltage I/Q Output Impedance I/Q DC Output I/Q DC Offset LO Input Frequency Range LO Input Level LO Input Impedance 100 60 680 340 2.7 50 2040 1020 0 8 77 250 2760 1380 50 0.5 5 1380 2760 2.0 1020 2040 dB dB dB dBm dBm dBm dB dB MHz Ω Ω MHz dB deg VPP Ω Ω VDC mVDC MHz mVPP Ω Ω V mA mA µA V V Balanced, maximum output level Single-ended Balanced Common Mode I OUT+ to I OUT-; Q OUT+ to Q OUTBalanced Balanced Single Ended 600 600 920 460 3.3 23 23 20 0.5 Power Supply Supply Voltage Current Consumption Power Down Current VPD HIGH Voltage VPD LOW Voltage CDMA Mode FM Mode VCC-0.7 7-2 Rev A14 010622 RF2667 Pin 1 Function VCC1 Description Supply voltage for the LO flip-flop divider and limiting amp. This pin may be connected in parallel with pins 2 and 3. It should be bypassed by a 10nF capacitor. The trace length between the pin and the bypass capacitor should be minimized. The ground side of the bypass capacitor should connect immediately to ground plane. The part is designed to work from a 2.7V to 3.3V supply. Supply voltage for the bandgap, gain control bias circuitry, and AGC stages 2, 3, and 4. This pin may be connected in parallel with pins 1 and 3. It should be bypassed by a 10nF capacitor. The trace length between the pin and the bypass capacitor should be minimized. The ground side of the bypass capacitor should connect immediately to ground plane. The part is designed to work from a 2.7V to 3.3V supply. Supply voltage for the FM and CDMA AGC input stages. This pin may be connected in parallel with pins 1 and 2. It should be bypassed by a 10nF capacitor. The trace length between the pin and the bypass capacitor should be minimized. The ground side of the bypass capacitor should connect immediately to ground plane. The part is designed to work from a 2.7V to 3.3V supply. CDMA Balanced Input pin. This pin is internally DC biased and should be DC blocked if connected to a device with a DC level present. For single-ended input operation, one pin is used as an input and the other CDMA input is AC coupled to ground. The balanced input impedance is 2.4kΩ, while the single-ended input impedance is 1.2kΩ. Interface Schematic 2 VCC2 3 VCC3 4 CDMA IN+ BIAS BIAS 1200 Ω 1200 Ω CDMA IN+ CDMA IN- 7 QUADRATURE DEMODULATORS 5 6 7 8 CDMA INGND GND FM IN+ Same as pin 4, except complementary input. Ground connection. Keep traces physically short and connect immediately to ground plane for best performance. Same as pin 6. FM Balanced Input pin. This pin is internally DC biased and should be DC blocked if connected to a device with DC present. For single-ended input operation, one pin is used as an input and the other FM input is AC coupled to ground. The balanced input impedance is 2.4kΩ, while the single-ended input impedance is 1.2kΩ. See pin 4. BIAS BIAS 1200 Ω 1200 Ω FM IN+ FM IN- 9 10 FM INBG OUT Same as pin 8, except complementary input. Bandgap Voltage Reference. This voltage, constant over temperature and supply variation, is used to bias internal circuits. A 10nF external bypass capacitor is required. The trace length between the pin and the bypass capacitor should be minimized. The ground side of the bypass capacitor should connect immediately to ground plane. AGC decoupling pin. An external bypass capacitor of 10nF capacitor is required. The trace length between the pin and the bypass capacitor should be minimized. The ground side of the bypass capacitor should connect immediately to ground plane. LO Balanced Input pin. This pin is internally DC biased and should be DC blocked if connected to a device with DC present. For single-ended input operation, one pin is used as an input and the other LO input is AC coupled to ground. The frequency of the signal applied to these pins is internally divided by a factor of 2, hence the carrier frequency for the modulator becomes one half of the applied frequency. The singleended input impedance is 400 Ω (balanced is 800 Ω). The LO input may be driven single-ended but balanced provides optimum gain and phase balance. Same as pin 12, except complementary input. See pin 8. 11 DEC 12 LO- BIAS BIAS 400 Ω 400 Ω LO- LO+ 13 LO+ See pin 12. Rev A14 010622 7-3 RF2667 Pin 14 Function IN SEL Description Selects between CDMA and FM mode. This is a digitally controlled input. A logic “high” (≥ VCC-0.7VDC) selects CDMA mode. A logic “low” (