RF3000PCBA

RF3000 0 Typical Applications • IEEE802.11b Wireless LAN Systems • ISM Band Systems • Direct Sequence Systems Product Description The RF3000 is a monolithic CMOS baseband processor. It is suitable for use in 11Mbps IEEE802.11b wireless LAN systems, and contains all functions required to convert a spread-spectrum signal to bit stream. The on-chip equalizer provides protection against multi-path in high data rate modes. All functions are configurable via an SPI port. A complete 2.4GHz radio reference design is available from RFMD. -A4.00 3.80 0.30 0.20 SPREAD-SPECTRUM BASEBAND MODEM • Wireless Modems • Wireless Point-to-Point 0.25 0.10 10.00 9.80 0.64 6.20 5.80 8° MAX 0° MIN 1.75 1.35 1.27 0.40 0.25 0.19 NOTES: 1. Shaded lead is Pin 1. 2. All dimensions are excluding mold flash. 3. Lead coplanarity - 0.10 with respect to datum "A". Optimum Technology Matching® Applied Si BJT Si Bi-CMOS InGaP/HBT GaAs HBT SiGe HBT GaN HEMT GaAs MESFET Si CMOS SiGe Bi-CMOS Package Style: SSOP-28 Features • On-Chip ADCs and DACs, RSSI, AGC • BPSK/QPSK/CCK RX VGC RXVGC DAC CCA RX VGC ANT SEL • 250nS Delay Spread Equalizer CCA LNA GS • Supports Antenna Diversity • Reference Design Available I IN I IN ADC Demodulator 802.11 Preamble/ Header VREF IN Data Converter Reference RX DATA Q IN Q IN ADC RX RDY DATA CLK TX VGC TX VGC DAC Control Port Mode Control SPI TX RDY Ordering Information RF3000 RF3000 PCBA Spread-Spectrum Baseband Modem Fully Assembled Evaluation Board I OUT I OUT DAC Modulator TX DATA 802.11 Preamble/ Header Tx Length Tx Signal Service RX PE TX PE M CLK Q OUT Q OUT DAC Functional Block Diagram RF Micro Devices, Inc. 7628 Thorndike Road Greensboro, NC 27409, USA Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com Rev A4 031216 11-321 RF3000 Absolute Maximum Ratings Parameter Supply Voltage Input, Output or I/O Voltage Voltage VDDD Output Max. Storage Temperature Max. Junction Temperature Operating Ambient Temperature Rating Unit VDC VDC V VDC °C °C °C +4.0 Ground-0.5 to VCC+0.5 2.7 to 3.6 2.7 -65 to +150 +150 -40 to +85 Caution! ESD sensitive device. RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s). Parameter DC Electrical Power Supply Voltage VREF Input Voltage Output Voltage Current Consumption Sleep Mode Input Leakage Current Output Leakage Current Output Loading Specification Min. Typ. Max. Unit Condition See Figures 15 and 16. VCC =3.0V to 3.3V+10%, TZ =-40°C to +85°C VDDA VDDD, Output Only. No current draw. Logical “1” (VIH) Logical “0” (VIL) Logical “1” (VOH) Logical “0” (VOL) Transmit Mode (ITX) Receive Mode (IRX) Mode 1, Reset Active, No Clocks (IS1) Mode 2, Reset Inactive, No Clocks (IS2) II IO VCC =3.0V to 3.3V+10%, TA =-40°C to +85°C. See Note 1. 2.7 TBD 1.6 2.5 -0.2 TBD TBD 3.3 2.2 1.7 VDDA-1.0 0.2 25 50 500 1.5 20 3.6 TBD 1.8 VDDA+0.2 +0.7 TBD 0.7 TBD TBD 500 1.5 10 10 20 V V V V V V V mA mA µA mA µA µA pF AC Electrical M CLK Duty Cycle Rise/Fall TXPE to IOUT/QOUT TXDATA to I/QOUT TXPE Inactive Width TXRDY Active to 1st DATACLK Hi Setup TXDATA to DATACLK Hold TXDATA to DATACLK Hi Reset to TXPE Reset to RXPE TXDATA Modulation Extension RXPE Inactive Width DATACLK Period DATACLK Width Hi or Low DATACLK to RX Data RXRDY to 1st DATACLK RXDATA to 1st DATACLK Setup RXDATA to DATACLK RESET Width Active RXPE to CCA Valid RXPE to RSSI Valid I/QIN to RXDATA 40/60 3.0 1 500 10 10 100 100 2 0 90 22 30 40 40 30 40 60/40 10 3.1 1.0 % nS µS µS µS nS nS nS µS µS µS nS nS nS nS nS nS nS nS µS µS µS All outputs. See Notes 2 and 3. 1st valid chip. 802.11 modes. See Notes 2 and 4. 44 68 See Notes 2 and 5. See Notes 2 and 6. 11Mbps Mode 11Mbps Mode See Note 2. 15 15 2.25 See Note 2. See Note 2. See Note 8. 11-322 Rev A4 031216 RF3000 Parameter I/Q ADC Full Scale Input Voltage Input Bandwidth Input Capacitance Input Impedance 0.7 11 5 50 200 11 6 0.5 0.5 1.2 2.0 6 0.5 0.5 1.2 2.0 6 0.5 0.5 +10% VP-P MHz pF kΩ mV MHz bits LSB LSB V V bits LSB LSB V V bits LSB LSB See Note 7. Specification Min. Typ. Max. Unit Condition I/Q DAC Full Scale Output Voltage Sample Rate Resolution DNL INL See Note 7. 1.0 Tested for monotonicity. TX VGC DAC Maximum Gain Output Voltage Minimum Gain Output Voltage Resolution DNL INL 1.0 Tested for monotonicity. RX VGC DAC Maximum Gain Output Voltage Minimum Gain Output Voltage Resolution DNL INL 1.0 Tested for monotonicity. Control Port Timing Characteristics SPI Mode C CLK Clock Frequency CS High Time Between Transmissions CS Falling to C CLK Edge C CLK Low Time C CLK High Time CD IN to C CLK Setup Time C CLK Rising to Data Hold Time C CLK Falling to CD OUT Stable 6 1.1 22 68 68 42 16 47 MHz µS nS nS nS nS nS nS Mode Switching Characteristics. See Figure 3. fCLK tCSH tCSS tCLKL tCLKH tDSU tDHLD tPD Notes: 1. AC tests performed with CL =20pF, IOL =2mA, and IOH =-1mA. Input reference level all inputs VCC/2. Test VIH =VCC, VIL =0V; VOH =VOL =VCC/2. 2. Not tested, but characterized at initial design and at major process/design changes. 3. Measured from VIL to VIH. 4. TX PE must be inactive before going active to generate a new packet. 5. IOUT/QOUT are modulated after last chip of valid data to provide ramp-down time for RF/IF circuits. 6. A new search will begin after last bit of 802.11 packet in 802.11 modes. 7. Centered about 1.7V VREF. 8. Accurate to within ±3dB of final gain setting. Rev A4 031216 11-323 RF3000 For more information on Figure 1, see parameter table (on previous pages). CSb CCLK CDIN CDOUT Figure 1. SPI Timing Transition Detail ss TXPE TXRDY DATACLK TXDATA ss ss ss Figure 2. Transmit Port Detail Timing ss RXPE RXRDY DATACLK RXDATA ss ss ss Figure 3. Receiver Port Detail Timing 11-324 Rev A4 031216 RF3000 Index GENERAL DESCRIPTION Figure 4. 2.4GHz IEEE802.11b Chipset Diagram Figure 5. RF3000 Block Diagram IEEE802.11b Preamble/Header Detection and Extraction Data Converters A/D Converters D/A Converters RSSI, CCA and AGC Scramblers Diversity Equalizer SPI CONTROL PORT SPI Mode Description SPI Mode Pin Definitions Table SPI Method of Operation Write Read SPI Operation Summary Write Read SPI Mode Functional Timing Diagrams Figure 6. SPI Write Functional Timing Diagram Figure 7. SPI Read Functional Timing Diagram CONTROL PORT REGISTER DEFINITIONS FOR RF3000 Register 0x0 - Reserved Register 0x01 - Modem Control and RX Status Mode 3-0 - TX Mode Table Register 0x02 - CCA Control CCA1, CCA0 - 802.11 CCA Mode Table Register 0x03 - Diversity and RSSI Value Register 0x04 - RX Signal Field Register 0x05 - RX Length Field MSB’s Register 0x06 - RX Length Field LSB’s Register 0x07 - RX Service Field Register 0x08 - Reserved Register 0x09 - Reserved Register 0x0A - Reserved Register 0x0B - Reserved Register 0x0C - Reserved Register 0x0D - Reserved Register 0x0E - Reserved Register 0x0F - Reserved Register 0x10 - Reserved Register 0x11 - TX Variable Gain and TX Length Field Extension Scrambler Mode Table Register 0x12 - TX Length Field MSB’s Register 0x13 - TX Length Field LSB’s Register 0x14 - Low Gain Calibration Register 0x15 - High Gain Calibration Register 0x16 - Reserved Register 0x17 - Reserved Register 0x18 - Reserved Register 0x19 - Reserved Register 0x1A - Reserved Register 0x1B - Reserved Register 0x1C - Options Register 1 Register 0x1D - Options Register 2 Register 0x1E - Reserved Register 0x1F - Reserved METHOD OF OPERATION IEEE802.11b Transmit Modes IEEE802.11b DSSS Transmit Modes IEEE802.11b DSSS Transmission Summary Figure 8. IEEE802.11b Transmit Timing Overview Figure 8a. Alternate Transmit Interface IEEE802.11b Receive Mode Diversity Figure 9. Diversity and AGC Algorithm AGC Algorithm Figure 10. AGC Decision Structure AGC Calibration Figure 11. High Gain Mode (LNAGS=1) Plot of RXVGC Showing Normal Operation and Calibration Ranges Figure 12. Low Gain Mode (LNAGS=0) Plot of RXVGC Showing Normal Operation and Calibration Ranges High Gain Calibration Procedure Low Gain Calibration Procedure Post-AGC IEEE802.11b DSSS Receive Summary Figure 13. IEEE802.11b Receive Timing Overview Figure 13a. Alternate Receiver Interface BLOCK DIAGRAM BREAKOUT Modulator PSK Modes CCK Mode IEEE802.11b Preamble/Header Creation and Assembly Demodulator PSK Modes CCK Mode Rev A4 031216 11-325 RF3000 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Function TXPE RXPE MCLK TXRDY RXRDY VDDD GNDD CCA LNAGS TXDATA DATACLK RXDATA CSb CCLK CDIN CDOUT RXVGC NC IIN QIN VDDA GNDA IOUT QOUT TXVGC ANTSEL RESET VREF Description Input from the external network processor. The rising edge of TX PE places the transmitter into an active state. The falling edge of TX PE indicates the end of transmission. When active (value '1'), the receiver is powered up and CCA circuitry is active. Master clock. This should be a 44MHz for IEEE802.11b and is used to generate other internally used clocks. Indicates that the chip is ready to accept data from the MAC for Tx. Indicates that the chip is ready to deliver data to the MAC from Rx. Output from 2.2V internal voltage regulator for digital sections of RF3000. This pin should not be connected to anything. Ground signal for digital power. Clear channel assessment per IEEE802.11b standard. “1” indicates “clear”. LNA gain select. “1” indicates “high gain”. TX data stream input. Data clock for TX and RX data. RX data stream output. In SPI mode this pin serves as serial port chip select. Serial port clock. This clock is used for SPI mode. In SPI mode this pin serves as CDIN input. In SPI mode this pin serves as CDOUT output. Analog receive variable gain control output: 1.2V to 2.0V. Not connected. Analog I input. Analog Q input. DC power for analog sections 3.3V. Ground signal for analog power. Analog I output: 1.6V to 1.8V. Analog Q output: 1.6V to 1.8V. Analog voltage for transmitter variable gain control: 1.2V to 2.0V. Antenna selection signal for diversity receiver. Pin='1' chip reset. Pin='0' standard operation. Reference voltage for internal data converters. Connect to RF2948 VREF or set to 1.7VDC. Interface Schematic 11-326 Rev A4 031216 RF3000 General Description RFMD 2.4 GHz WLAN System Block Diagram RF2948 RX VGC RXVGC DAC CCA RX VGC CCA LNA GS RX Q DATA VREF Q-IN ADC Data Converter Reference I-IN ADC TXVGC DAC 802.11 Preamble/ Header RX DATA RX RDY DATA CLK TX VGC Control Port Mode Control SPI Demodulator ANT Select RX TX IF Amp RX I DATA Base Band Amp. Active Selectable LPF (fC = 1 MHz to 35 MHz) 0-30 dB Gain VREF_1 ÷2 +45° -45° Filter TX I DATA I-OUT DAC TX RDY Modulator TX DATA 802.11 Preamble/ Header Tx Length Tx Signal Service RX PE TX PE MCLK PA Driver Σ TX Filter Selectable LPF TX Q DATA Q-OUT DAC RF3000 Fc = 2442 MHz Fc = 2442 MHz IF VCO RF VCO SAW RX Gain Select Antenna 1 LNA Dual Gain Modes IF Fc = 374 MHz Filter Fc = 2442 Mhz Antenna 2 T/R Switch Diversity Switch RF Figure 4. 2.4GHz IEEE802.11b Chipset Diagram Figure 4 shows the complete 2.4GHz chipset, and where the RF3000 fits into the system. Figure 5 shows a simplified block diagram of the RF3000. The RF3000 is a complete spread-spectrum transceiver, allowing PSK system operation. The RF3000 performs all of the functions necessary to modulate a digital data source for transmission in a wireless environment. The RF3000: handles preamble and header generation and extraction; automatic gain control; clear channel assessment; antenna diversity; and, implements an equalizer to handle multi-path events at high data rates. Rev A4 031216 11-327 RF3000 RX VGC ANT Select RXVGC DAC CCA Rx VGC CCA LNA GS I Input VREF Q Input I-IN ADC Data Converter Reference Q-IN ADC TXVGC DAC 802.11 Preamble/ Header Rx Data Rx RDY Data CLK Control Port Mode Control SPI Demodulator TX VGC I Output I-OUT DAC Tx RDY Modulator Tx Data 802.11 Preamble/ Header Tx Length Tx Signal Service Rx PE Tx PE Mclk Q Output Q-OUT DAC RF3000 Figure 5. RF3000 Block Diagram 11-328 Rev A4 031216 RF3000 SPI Control Port The control port is used by the Media Access Controller (MAC) to set up and modify the multiple operation modes of the RF3000. The port is set to SPI mode, with the RF3000 acting as Slave. Note that if no setup information is programmed into the RF3000's registers, it will default to a BPSK 1Mbps IEEE802.11b DSSS mode. If an IEEE802.11b mode is selected in Register 1, other waveform registers are ignored and the appropriate, standards compliant features are enabled (e.g., PN code, preamble/header, etc.). TX length is required for all IEEE802.11b modes. All Registers, as defined in the Register Definition section of this datasheet, can be read in real time through this control port. Selected registers, as indicated in the Register section are read-only. The control port of the RF3000 contains a mode to automatically increment the register pointer, allowing reading or writing of adjacent bytes without the need to stop and restart control port access. SPI Mode Description SPI mode pin definitions. Pin Name CS C CLK CD IN CD OUT Description Serial port chip select. A value of '0' is port enabled. Control port-bit clock input from serial port master. Serial data input to the RF3000. Data is clocked in on the rising edge of C CLK. Serial data output from the RF3000. Data is clocked out on the falling edge of C CLK. SPI Method of Operation Write: To Write into a register of the RF3000, the accessing SPI master needs to simply bring CS low, then Address the RF3000 (01000002) and provide a '0' for the Read/Write-bit. The user should note that all data transfers to/from the RF3000 are msb first. This should be followed by the Auto-increment-bit and the Memory address pointer (MAP), this is an 7-bit value to indicate the initial address for the write process. Register data is to immediately follow the MAP. If the Auto-Increment-bit is set RF3000 will continue to write data 1 byte at a time into the address pointed to by the MAP, and increment the MAP after each byte. When the SPI Master is finished filling registers, it must raise CS to indicate the cycle end. Read: Reading the contents of the RF3000 internal registers, the procedure is actually a write process followed by the read. The SPI Master must bring CS low, to prepare the RF3000 to look for its address. The SPI Master now addresses the RF3000, by placing the RF3000 base address (01000002) on the data bus and append a '0' for the Read/Write-bit. The SPI Master must now set the Auto-increment-bit and initialize the 7-bit MAP to the value of the register to be read. The user should raise CS, to end the write portion of the cycle. To complete the Write/Read cycle the SPI Master now needs to lower CS again, and readdress the RF3000 providing a '1' for the Read/Write-bit. Once this is completed the RF3000 will begin outputting the register contents. As long as the CS remains low, and the auto-increment bit is set, the RF3000 will auto-increment the MAP. When the RF3000 reaches Address 31, the MAP will be reset to Register 0 and the process continues. Rev A4 031216 11-329 RF3000 SPI Operation Summary To Write: 9. Bring CS low. 10.Chip Address (7-bits) - This should match the RF3000 chip address of 01000002. 11.Read/Write-bit = '0' 12.Auto-Increment-bit - Value of '1' enables auto-increment 13.Memory Address Pointer (MAP) (7-bits) - This is the address of the register to be written to, MSB first. 14.Register Data (8-bits) - MSB First 15.Repeat step 6 if Auto-Increment or bring CS HIGH to end operation. To Read: 1. Bring CS low. 2. Chip Address (7-bits) - This should match the RF3000 chip address of 01000002. 3. Read/Write-bit = '0' 4. Auto-Increment-bit - Value of '1' enables auto-increment 5. Memory Address Pointer (MAP) (7-bits) - This is the address of the register to be written to, MSB first. 6. Bring CS high. 7. Bring CS low. 8. Chip Address (same as step 2) - MSB First 9. Read/Write-bit = '1' 10. RF3000 will output 8-bit register value, MSB First, and Increment MAP, if Auto increment enabled. 11. Repeat step 10 for polling or Auto-Increment or bring CS high to end operation. SPI Mode Functional Timing Diagrams Write CS CCLK CDIN CDOUT Chip Address AI Memory Address "Hi Z" Data Data Figure 6. SPI Write Functional Timing Diagram Read CS CCLK CDIN CDOUT Chip Address Memory Address "Hi Z" Chip Address Data "Hi Z" Figure 7. SPI Read Functional Timing Diagram 11-330 Rev A4 031216 RF3000 RF3000 Method of Operation The transmitter power enable (TX PE) input enables the transmitter process. (Note: Transmit has priority over receive.) When TX PE is high, the LNA GS signal will be driven low. The TX RDY output indicates the readiness of the RF3000 to receive data for transmit. Transmitted data is passed into the RF3000 through the TXDATA input and clocked by the DATA CLK output. The receiver power enable (RX PE) input enables the receiver, and the receive data ready (RX RDY) signal indicates that received data is upcoming. The RF3000 generates the received data clocks, and outputs the received data, through the RX DATA output. The receiver port also provides a clear channel assessment (CCA) to the MAC. The table below summarizes the operation of the chip. The user should note that RX PE must be High to perform CCA. TX PE 0 0 1 1 RX PE 0 1 0 1 Standby mode. Operation RX is powered up. CCA circuity is active. TX is powered up. Begin TX. CCA is inactive. RESERVED IEEE802.11b Transmit Modes IEEE802.11b DSSS Transmit Modes The RF3000 supports PSK and CCK DSSS modes defined in IEEE802.11b specification. The RF3000 also supports the optional short preamble and header format as defined in IEEE802.11b. The following section describes IEEE802.11b DSSS data transmission. The user must first prepare the applicable control port registers to determine the mode of operation and the transmission length. The mode of operation must be written into Register 1, followed by setting the transmission length (in microseconds). The length is to be written into Registers 17 (bit 0 only), 18 and 19. Mode byte values for IEEE802.11b modes are summarized below . IEEE802.11 DSSS Mode 1Mbps DBPSK 2Mbps DQPSK Long preamble 2Mbps DQPSK Short preamble 5.5Mbps CCK Long preamble 5.5Mbps CCK Short preamble 11Mbps CCK Long preamble 11Mbps CCK Short preamble Mode Byte Value 0x0016 0x2016 0x3016 0x4016 0x5016 0x6016 0x7016 Once the control port values are written, the RF3000 is ready to transmit data. Optionally, the TX length value can be written during the 128 µS of preamble. When the user is ready to transmit, TX PE is driven High. This signals the RF3000 to assemble and transmit the 802.11 preamble and header, as described below. Preamble 128 1’s SFD (16-bits) Service (8-bits) Header Signal (8-bits) Length (16-bits) CRC (16-bits) Data Data (x-bits) The preamble and header for 1Mbps mode is always transmitted as 1Mbps BPSK. However for 2Mbps, 5.5Mbps and 11Mbps modes, IEEE802.11b allows a short preamble, which has the preamble, transmitted as 1Mbps BPSK and the header transmitted as 2Mbps QPSK. The usage of the optional short preamble is selected when the transmission mode is written to the control port. Rev A4 031216 11-331 RF3000 The RF3000 signals that it is nearing the end of the preamble and header transmission by driving TX RDY high. This signals the user that transmission data clocks are coming. When the RF3000 is ready to transmit data it will begin clocking transmit data. Data to be transmitted should be present on TX DATA on the rising edge of DATA CLK. The RF3000 will only clock in the number of data-bits to fill the specified transmission time. IEEE802.11b DSSS Transmission Summary 1. TX Mode different: Write value to the mode register according to table. 2. TX Length different: Write the number of uS to transmit in the TX length registers. 3. Drive TX PE High and wait for TX RDY to go High. 4. Transmit data must be valid on the rising edge of DATA CLK. Figure 8 shows the primary interface mode for the RF3000 TX Data port. CCA RX PE TX PE TX RDY DATA CLK TX DATA TX I TX Q Preamble and Header Data Rate Determined from Control Port Register 1 Figure 8. IEEE802.11b Transmit Timing Overview The RF3000 has provision for an alternate Transmit Data port interface. In the transmit interface an extra clock is asserted after TXRDY goes ‘high' and before the first TX data clock on DATA CLK, see Figure 8a. The alternate Transmit interface is enabled by writing 0x08 into RF3000 Register 0x1C. CCA RX PE TX PE TX RDY DATA CLK TX DATA TX I TX Q Preamble and Header Data Rate Determined from Control Port Register 1 Figure 8a. Alternate Transmit Interface 11-332 Rev A4 031216 RF3000 IEEE802.11b Receive Mode The RF3000 receiver has an interface similar to the transmit port, and provides link support data through the control port. The user drives RX PE High to enable the receiver circuitry. The RF3000 then begins to watch the incoming data stream for a valid Barker code PN sequence. The RF3000 contains logic to perform AGC when used in conjunction with the RF2948 and RF2494 as in the RF031X reference designs for IEEE802.11b. The following sections will explain the method of AGC and the calibration hooks that exist inside the RF3000 to compensate for manufacturing tolerances in total system gain of an IEEE802.11b radio. Diversity The RF3000 makes diversity decisions every 1mS while looking for A/D saturation according to the state machine in Figure 9. NOT Saturated ANTSEL = 0 ANTSEL = 1 NOT Saturated Saturated Saturated NOT Acquired AGC Algorithm (Course Gain) Wait 15 uS Acquired Demodulation (Fine Gain) Figure 9. Diversity and AGC Algorithm AGC Algorithm The RF3000 AGC algorithm is implemented to automatically control both the RXVGC of the RF2948 and the LNAGS pin of the RF2494. The RF3000 is programmed to search the possible gain settings of LNAGS and RXVGC in a binary fashion to quickly determine the final gain setting needed to optimize the inputs to the A/D converters for demodulation. The AGC algorithm is completely controlled by detection of saturation of the A/D converters. Rev A4 031216 11-333 RF3000 The RF3000 begins the algorithm by setting the RXVGC and LNAGS pins to a predetermined maximum gain condition. Upon detection of A/D saturation, the RF3000 will decrease the system gain (via the RXVGC pin) to a predetermined “mid-point”. This mid point is chosen to allow the RF3000 to determine the correct setting of the LNAGS pin. If the RF3000 detects saturation at this “mid-point”, the RF3000 will place the RF front end into a low gain mode, and will begin searching for the correct RXVGC setting in a binary tree fashion. If the RF3000 does not detect saturation on the A/D converters while at this “mid-point”, the RF3000 will leave the LNAGS pin in high gain mode and proceed with the binary search of RXVGC. This binary tree representation of the gain algorithm can be seen in Figure 9. It is important to note that once the RF3000 makes a decision on the LNAGS setting, that setting will remain for the entire duration of the packet and cannot be altered until the next packet. Gain (VGC, LNAGS) Max Gain HIGH GAIN LNA GS=1 Solid Lines are shifted along the Gain axis with adjustment of Register 0x15 LOW GAIN LNA GS=0 Dashed Lines are shifted along the Gain axis with adjustment of Register 0x14 Indicates decision points Min Gain t=0 1uS 2uS 3uS ... 6uS Time(t) Figure 10. AGC Decision Structure RSSI is a function of RXVGC and LNAGS. RSSI is updated every 1 µS during the AGC algorithm. While demodulating data, the demodulator will make fine tuning adjustments to RSSI based on the value of RXVGC. An optional AGC algorithm is available, enabled by writing a '1' into bit 4 of Register 0x1C. In this mode the AGC may be kicked off after it has already settled if a large signal is present. This addresses a scenario in which an interferer (which may be noise) initially kicks off the AGC. The AGC then chooses the gain setting to accommodate this level of signal. Subsequently, a desired signal is incident on the antenna. This signal may be larger than the interferer and, because of the gain setting of the radio, may be difficult to demodulate. Under the optional AGC mode, the gain would be re-optimized to the desired signal. We believe that this will help radio performance in many environments. When using the new AGC algorithm, Register 0x1C should be written to 0x78. The values of 0, 1, 1 in b7, b6, b5 respectively increases the saturation requirement for the AGC algorithm. This has the effect of biasing the algorithm to produce a higher gain setting to give the baseband processor an optimum input amplitude for robust demodulation. 11-334 Rev A4 031216 RF3000 Another optional mode has been added to the AGC algorithm. This mode adds a delay into the algorithm after the LNA gain select is changed to allow enough time for the radio to settle properly. The delay eliminates the possibility of a 'dead zone' where there is a small range of input power levels with a probability that the AGC will settle to an incorrect gain setting. To enable this mode, Register 0x1D is written to 0x80. In addition, the 6 lsb's of reg20 must be set to 4 higher the 6 lsb's of reg21 because the outcome of the AGC decision step will change. If this mode is not to be used, Register 0x1D should be written to 0x00. AGC Calibration The RF3000 is preprogrammed for a “typical” radio. The default settings of the RF3000 may be used without modification, but the conditions of the AGC algorithm may be modified by writing to register 21 and register 20 of the control port. Register 21 controls an offset to the RXVGC DAC for LNAGS=1 (high gain mode), and register 20 controls an offset to the RXVGC DAC for LNAGS=0 (low gain mode). Caution should be taken when setting these registers; incorrect settings can create a “dead zone” between the high/low gain trees. The following figure shows the “typical” settings for the RXVGC output of the RF3000 during LNAGS=1. Also shown are the expected production variances of an IEEE802.11 radio, and the calibration ranges of the RF3000. Writing to register 21 of the RF3000 will move the range of AGC operation on the RXVGC pin. For example, if the six LSB's in register 21 are written to 000100b (4 decimal), the starting point for the AGC algorithm (max gain) will be with a DAC code of 8+4=12 codes, and the LNAGS decision will be made at a code of 47+4=51 codes. This has the overall effect of decreasing the gain provided by the RF2948 by four D/A codes or approximately 5dB for both initial AGC setting for detection of saturation and for determining LNAGS. Likewise if the six LSB's of register 21 are written to 1111000 (-4 decimal), the initial condition that the RF3000 uses to look for saturation is 8-4=4 codes, and the LNAGS decision is determined at 47-4=43 codes. Process Variation Process Variation Cal Range Typical RF3000 AGC Range D/A Code Typical RF2948 Gain 0 8 67.8dB 24 39 Cal Range 47 21.7dB 63 Figure 11. High Gain Mode (LNAGS=1) Plot of RXVGC Showing Normal Operation and Calibration Ranges Similar to the high gain calibration, register 20 controls an offset into the LNAGS=0 (low gain mode) values that are applied to the D/A converter. The figure below shows the normal operation range of the RF3000 and the calibration range that is provided. Process Variation Process Variation Cal Range Typical RF3000 AGC Range D/A Code Typical RF2948 Gain 0 8 67.8dB 17 39 Cal Range 54 13.4dB 63 Figure 12. Low Gain Mode (LNAGS=0) Plot of RXVGC Showing Normal Operation and Calibration Ranges Rev A4 031216 11-335 RF3000 High Gain Calibration Procedure Calibration of an IEEE802.11b radio can be accomplished by sending a repetitive pattern to the radio at a known input power, and adjusting the register settings until all packets are correctly received without errors or missing packets. A simple procedure is contained outlined as follows. 1. Write the six LSB's of register 21 to the value 011000 (24 decimal). This will decrease the total system gain. 2. Apply an 1Mbps IEEE802.11b signal to the input of the radio of a known input power (-75dBm). 3. Decrease the six LSB's of register 21 by one LSB until all packets are received correctly without dropping any packets. 4. Since the input power of the reference signal was set to -75dBm (to eliminate effects of thermal noise), calculate the final register 21 setting by subtracting a known predetermined value from the value found in step 3 of the calibration procedure. Low Gain Calibration Procedure Similar techniques can be applied to calibrate the Low gain settings of the RF3000. As an initial value, the register setting in register 20 should be equal to the value of register 21. Register 20 is provided to allow manufacturing calibration to account for reverse isolation variances in the T/R switch if used as an additional pad. Post-AGC When the Barker code is acquired, the RF3000 assigns the ACQ-bit in the mode register to a 1 and proceeds to extract the header information. When the start frame delimiter is identified, the RF3000 will assign a 1 to the SFD-bit in the mode register. The RF3000 will now decode the transmission mode and data length from the header, and check the header via the 16-bit CRC. The RF3000 will then clock-out 32 bits of header information. This will be the 8-bit RX signal field, followed by the 8-bit RX service field, and then the 16-bit RX length field. The MAC can also read these values through the serial port registers 0x04 through 0x07. The header data will be followed by 16 bit times of no clock transitions. Immediately before providing data, the RF3000 will drive RX RDY High. The received data will be stable on the rising edge of DATA CLK. In the event the header CRC is incorrect, the RF3000 will bring RX RDY high for the duration of the packet, but no DATA CLK or RX DATA transitions will occur. 11-336 Rev A4 031216 RF3000 IEEE802.11b DSSS Receive Summary 1. Drive RXPE High. 2. RF3000 looks for incoming valid Barker Code. 3. RF3000 sets ACQ bit in Register 0x01. 4. When the Start Frame Delimiter is identified, the RF3000 sets the SFD bit in Register 0x01. 5. RF3000 Extracts Header information. This information is copied into the RF3000 RX Status, Service fields and presented on the RXDATA Pin with Clocks on DATA CLK. 6. This will be followed by 16 bit times of no clock transitions. 7. RF3000 Drives RXRDY high, and clocks Received Data on the rising edge of DATA CLK. 8. RF3000 Drives RXRDY low at the end of the data packet. RXPE RXRDY DATACLK RXDATA 32CLK Cycles Header Data Preamble and Header Extraction Data Rate Determined from Received IEEE802.11 Signal Field Figure 13. IEEE802.11b Receive Timing Overview The RF3000 has provision for an alternate Receive Data port interface. In the receiver interface, the DATACLK is inverted, and an extra clock is asserted after RXRDY goes 'low' indicating the end of the received packet, see Figure 13a. The alternate Transmit interface is enabled by writing 0x08 into RF3000 Register 0x1C. RXPE RXRDY DATACLK RXDATA 32CLK Cycles Header Data Preamble and Header Extraction Data Rate Determined from Received IEEE802.11 Signal Field Figure 13a. Alternate Receiver Interface Rev A4 031216 11-337 RF3000 Block Diagram Breakout The following sections describe each of the blocks, as indicated in the block diagram, that comprise the RF3000. Modulator PSK Modes The RF3000 uses a proprietary architecture that allows the modulation of PSK signals by simply reprogramming the part via the control port. The transmitted data stream is first spread and the resulting data stream is modulated. CCK Mode IEEE802.11b Preamble/Header Creation and Assembly The RF3000 provides circuitry to generate and assemble a preamble and header as specified in the IEEE802.11b specification. The short preamble option for 2Mbps, 5.5Mbps and 11Mbps, as specified in IEEE802.11b, is selectable in the mode control register. The RF3000 will transmit these fields along with a protective CRC-16 for error detection. For other protocols, the preamble/header circuitry is disabled, and packet structures should be generated externally. Demodulator PSK Modes The RF3000 uses a proprietary architecture that allows the demodulation of PSK signals by simply reprogramming the part via the control port. The received signal is first de-spread and the PSK signal is recovered. CCK Mode In order to perform CCK demodulation, circuitry is provided to pass the output of the A/D converters to a fast Walsh transform (FWT). The output of the FWT is then passed to decision circuitry to determine the received signal. IEEE802.11b Preamble/Header Detection and Extraction Circuitry is provided to search the incoming data for start frame delimiter (SFD) and to obtain length field information as well as modulation type. In 802.11 modes, this circuitry is always active since the preamble and header tells the PHY which modulation type the data packet is using. The RF3000 will also check the preamble/header field for errors by checking the CRC-16 field for errors. Data Converters The RF3000 contains all A/D converters and D/A converters required to implement a transceiver. A/D Converters I/Q A/Ds - These are 4-bit analog-to-digital converters used to sample the data according to the mode of the RF3000. D/A Converters Four (4) digital-to-analog converters are present for transmitter VGC, receiver VGC, I Out, and Q Out. RSSI, CCA and AGC Scramblers Scramblers for whitening the spectrum are provided, as specified in IEEE802.11b. SCRAMBLER NOTE: The data scrambler defined by IEEE802.11b has a probability of 1/128, to lock up scrambling when random data is followed by a repetitive pattern. The patterns identified are: all 0's; all 1’s; repetitive 01's; repeated 0011's; and, repeated 000111's. Once the pattern ceases the scrambler will resume its normal operation. 11-338 Rev A4 031216 RF3000 Diversity Switching and detection at beginning of Receive. Equalizer Proprietary architecture, active only in 5.5Mbps and 11Mbps CCK modes. For multipath cancellation, the RF3000 defines the path with the largest magnitude as the main path and all others as secondary paths. The RF3000 equalizer can cancel the two most significant secondary paths. these can either be two (2) post-cursor, echo paths, or they can be one (1) post-cursor and one (1) pre-cursor paths. Pre-cursor delay can be up to one-quarter symbol period. Post-cursor delay can be up to one (1) symbol period. The magnitude of cancelled multipaths up to -3dBc, normalized to the main path. Rev A4 031216 11-339 RF3000 Control Port Register Definitions for RF3000 Register 0x00 - Reserved R7 R6 R5 R4 R3 R2 R1 R0 This register is reserved. Register 0x01 - Modem Control and RX Status Mode 3 Mode 2 Mode 1 Mode 0 Short Preamble* ACQ * SFD * CRC * * - Read Only This register is used to setup primary operation of the modem. NOTE: The four (4) LSB’s are read-only and reflect the receiver status. Mode (3-0) - TX Mode Mode 3 0 0 0 0 0 0 0 0 1 1 1 1 Mode 2 0 0 0 0 1 1 1 1 0 0 0 0 Mode 1 0 0 1 1 0 0 1 1 0 0 1 1 Mode 0 0 1 0 1 0 1 0 1 0 1 0 1 Mode ID 802.11 1Mbps DSSS Default Mode Reserved Reserved Notes 802.11 2Mbps DSSS Long preamble 802.11 2Mbps DSSS Short preamble 802.11 5.5Mbps CCK Long preamble 802.11 5.5Mbps CCK Short preamble 802.11 11Mbps CCK Long preamble 802.11 11Mbps CCK Short preamble BPSK QPSK Reserved Reserved Reserved Reserved Reserved Reserved Default 802.11 1Mbps DSSS, RX mode detected automatically. NOTE: In 802.11 modes, the received data rate will be accepted from the received header and therefore will be selected automatically. Short Preamble - READ ONLY 0 - Long Preamble Received 1 - Short Preamble Received ACQ - Receiver acquisition status - READ ONLY 0 - Not locked 1 - acquired SFD - 802.11 SFD status - Read Only 0 - Not found 1 - SFD detected CRC - 802.11 RX CRC - Read Only 0 - CRC valid 1 - CRC error 11-340 Rev A4 031216 RF3000 Register 0x02 - CCA Control CCA1 CCA0 RSSI_t5 RSSI_t4 RSSI_t3 RSSI_t2 RSSI_t1 RSSI_t0 CCA1, CCA0 - 802.11 CCA Mode: CCA1 0 0 1 CCA0 0 1 X CCA Mode RSSI Threshold Sensitive Acquisition Sensitive Both RSSI_t - 6-bit RSSI threshold value for CCA. Register 0x03 - Diversity and RSSI Value Diversity Cpantsel RSSI5 * RSSI4 * RSSI3 * RSSI2 * RSSI1 * RSSI0 * * - Read Only NOTE: The six (6) LSB’s are read-only and reflect the receiver status. Diversity - RX diversity enable bit. Default - 0 0 - No diversity, ANT SEL pin is forced to Cpantsel. 1 - Diversity active, RF3000 automatically selects ANT SEL pin. Cpantsel - Antenna selection bit in non-diversity mode. Default - 0 0 - ANT SEL forced to 0. 1 - ANT SEL forced to 1. RSSI5-0 - Output of the RSSI A/D - Read Only Register 0x04 - RX Signal Field (Read only) RX_Sig7 RX_Sig6 RX_Sig5 RX_Sig4 RX_Sig3 RX_Sig2 RX_Sig1 RX_Sig0 In DSSS modes, this value is the received byte of the received signal field. In FHSS, only the four (4) LSB’s are used. BIT 7 0 0 0 0 0 0 0 0 0 0 0 0 BIT 6 0 0 0 1 0 0 0 0 0 0 0 0 BIT 5 0 0 1 1 0 0 0 0 0 0 0 0 BIT 4 0 1 1 0 0 0 0 0 0 0 0 0 BIT 3 1 0 0 1 0 0 0 0 0 0 0 0 BIT 2 0 1 1 1 0 0 0 0 1 1 1 1 BIT 1 1 0 1 1 0 0 1 1 0 0 1 1 BIT 0 0 0 1 0 0 1 0 1 0 1 0 1 Received Mode 1Mbps DSSS 2Mbps DSSS 5.5Mbps DSSS 11Mbps DSSS Reserved 1.5Mbps FSK*** Reserved 2.5Mbps FSK*** 3Mbps FSK*** 3.5Mbps FSK*** 4Mbps FSK*** 4.5Mbps FSK*** *** - IEEE802.11b proposed modulation rates not currently supported. Register 0x05 - RX Length Field MSB’s (Read only) RX_LN15 RX_LN14 RX_LN13 RX_LN12 RX_LN11 RX_LN10 RX_LN9 RX_LN8 The upper byte of the length field received. In DSSS mode, this value is the length in microseconds of the received data packet. Rev A4 031216 11-341 RF3000 Register 0x06 - RX Length Field LSB’s (Read only) RX_LN7 RX_LN6 RX_LN5 RX_LN4 RX_LN3 RX_LN2 RX_LN1 RX_LN0 The lower byte of the length field received. Register 0x07 - RX Service Field (Read only) RX_SER7 RX_SER6 RX_SER5 RX_SER4 RX_SER3 RX_SER2 RX_SER1 RX_SER0 This register is used per IEEE802.11b specification. RX_SER7 is length field extension in high data rate proposal 802.11b. RX_SER3 is modulation selection bit for high rate transmission. 0 - CCK RX_SER2 signifies Synth Clock to Signal Clock per 802.11 specification. Register 0x08 - Reserved Register 0x09 - Reserved Register 0x0A - Reserved Register 0x0B - Reserved Register 0x0C - Reserved Register 0x0D - Reserved Register 0x0E - Reserved Register 0x0F - Reserved Register 0x10 - Reserved Register 0x11 - TX Variable Gain and TX Length Field Extension TXVGC5 TXVGC4 TXVGC3 TXVGC2 TXVGC1 TXVGC0 SCRAMBLER TX_LN16 TXVGC5-TXVGC0 - Gain setting for transmission. 000000 - Min gain 111111 - Max gain SCRAMBLER - This bit enables and disables the IEEE802.11b data scrambler. Bit Value 0 1 Scrambler Mode Enabled Disabled TX_LN16 - TX length extension bit as defined in IEEE 802.11b specification. Register 0x12 - TX Length Field MSB’s TX_LN15 TX_LN14 TX_LN13 TX_LN12 TX_LN11 TX_LN10 TX_LN9 TX_LN8 Register 0x13 - TX Length Field LSB’s TX_LN7 TX_LN6 TX_LN5 TX_LN4 TX_LN3 TX_LN2 TX_LN1 TX_LN0 Registers 0x12 and 0x13 indicate the number of microseconds that the RF3000 is to transmit after receiving a request to start transmission. 11-342 Rev A4 031216 RF3000 Register 0x14 - Low Gain Calibration Reserved Reserved Low_Gain5 Low_Gain4 Low_Gain3 Low_Gain2 Low_Gain1 Low_Gain0 Bit 5 .. Bit 0:Low Gain Calibration, Range -32 to +16 Register 0x15 - High Gain Calibration Bit 7 Bit 6 Bit 5 High_Gain5 Bit 4 High_Gain4 Bit 3 High_Gain3 Bit 2 High_Gain2 Bit 1 High_Gain1 Bit 0 High_Gain0 Channel 14 Filter DSSS PAD Bit 7: A value of ‘1’ enables the channel 14 filter Bit 6: 6dB pad of DS modes Bit 5 .. Bit 0:High Gain Calibration, Range -8 to +31 Register 0x16 - Reserved Register 0x17 - Reserved Register 0x18 - Reserved Register 0x19 - Reserved Register 0x1A - Reserved Register 0x1B - Reserved Register 0x1C - Options Register 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SAT_THRESH [2] SAT_THRESH [1] SAT_THRESH [0] ALT AGC Enabled Alternative RESERVED ’0’ RESERVED ‘0’ RESERVED ‘0’ Data Port Interface Bit 7 .. Bit 5:Signed Magnitude Offset for all steps of course AGC. Saturation threshold is 4+ value where V=3< Value< 3. Bit 4: A value of ‘1’ allows the AGC algorithm to retrigger with ADC saturation. Bit 3: A value of ‘1’ enables the alternate TX/RX data bus interface. Bit 2: Reserved, set to ‘0’. Register 0x1D - Options Register 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LNAGS DELAY RESERVED ‘0’ RESERVED ‘0’ RESERVED ‘0’ RESERVED ‘0’ AGC Re-trigger RESERVED ‘0’ RESERVED ‘0’ Threshold LNAGs Delay-When set to ‘1’, this delays the next AGC decision step an extra 1 µS (total of 2 µS) if a transition of the LNAGs pin from 1 to 0 occurs. Bit 6 .. Bit 3:Reserved, set to ‘0’. Bit 2: Sets threshold for AGC re-trigger. ‘0’ sets re-trigger threshold to high count. ‘1’ sets re-trigger threshold to low count. Bit 1: Reserved, set to ‘0’. Bit 0: Reserved, set to ‘0’. Bit 7: Register 0x1E - Reserved Register 0x1F - Reserved Rev A4 031216 11-343 RF3000 Pin Out TXPE RXPE MCLK TXRDY RXRDY VDDD GNDD CCA LNAGS TXDATA DATACLK RXDATA CSb CCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VREF RESET ANTSEL TXVGC QOUT IOUT GNDA VDDA QIN IIN NC RXVGC CDOUT CDIN 11-344 Rev A4 031216 RF3000 Evaluation Board Schematic (Download Bill of Materials from www.rfmd.com.) P1 1 GND E1 MCLK 2 P2 3 P3 4 P4 5 P5 J1 MCLK MCLK U1 GND 35 CD1 36 P37 37 P38 38 P39 39 P40 40 P41 41 CE2 42 REFRESH 43 I/ORD 44 I/OWR 45 P46 46 P47 47 P48 48 P49 49 P50 50 5.0 VCC 51 VPP2 52 P53 53 P54 54 P55 55 P56 56 VS2 57 RESET 58 WAIT 59 INPACK 60 REG 61 SPKR 62 STSCHG 63 P64 64 P65 65 P66 66 CD2 67 GND 68 GNDD RESET E17 5.0 VCC CCLK CDOUT CDIN E2 E8 E4 LNA CNTL TXDATA DATACLK RXDATA CS E12 E6 E11 E3 E7 6 P6 R3 10 kΩ VREF 28 RESET 27 ANTSEL 26 TXVGC 25 QOUT 24 IOUT 23 GNDA 22 VDDA 21 Q IN 20 I IN 19 RSSI 18 RSVGC 17 CDOUT SDA 16 CDIN AD1 15 RESET ANTSEL TXVGC QOUT IOUT GNDA 3.3VCC Q IN I IN RSSI RXVGC CDOUT CDIN GNDD 23 P23 I IN 7 CE1 VREF 8 P8 9 OE E14 E15 E18 E21 E19 CCA TXRDY RXRDY RXPE TXPE 10 P10 11 P11 12 P12 13 P13 14 P14 15 WE:P 16 READY 3.3 VCC 5.0 VCC 17 5.0 VCC 18 VPP 19 P19 20 P20 TXPE GNDD J2 Q OUT Q OUT 1 TXPE 2 RXPE 3 MCLK 4 TXRDY 5 RXRDY 6 VDDD 7 GNDD 8 CCA 9 LNA CNTL 10 TXDATA 11 DATACLK 12 RXDATA 13 CSN AD0 14 CCLK RF3000 RXPE MCLK E22 E10 TXRDY RXRDY VDDD C3 0.47 µF GNDD CCA C4 0.1 µF GNDA J3 I OUT I OUT E23 LNA CNTL TXDATA R1 0Ω C2 0.47 µF C1 10 nF GNDA J4 Q IN Q IN DATACLK RXDATA E24 CS CCLK R2 4.7 kΩ 21 P21 22 P22 GNDA J5 I IN E25 3000400, Rev. B 24 P24 25 P25 26 P26 27 P27 28 P28 29 P29 30 P30 31 P31 32 P32 P2 Analog I/O 1 2 3 4 E9 RSSI GNDA ANTSEL TXVGC P3 Power 1 2 3 4 RXVGC E5 VREF 5 E16 GNDA GNDD 5.0 VCC R5 0Ω GNDA VREF E20 E13 33 WP GNDD 34 GND GNDD PCMCIA CON U2 3.3 VCC SHTDN R4 330 kΩ 1 C7 0.01 uF 2 3 4 C6 4.7 uF BYPASS 8 7 6 5 C5 4.7 uF NC ERROR 5.0 VCC GND SENSE INPUT OUTPUT LP2987 Rev A4 031216 11-345 RF3000 Evaluation Board Layout Board Size 2.12” x 3.57” Board Thickness 0.062”, Board Material FR-4 11-346 Rev A4 031216 RF3000 Rev A4 031216 11-347 RF3000 11-348 Rev A4 031216