RF5176

Preliminary RF5176 3V W-CDMA POWER 1900MHZ/ 3V LINEAR POWER AMPLIFIER 2 Typical Applications • 3V 1850-1910MHz CDMA-2000 Handsets • 3V 1920-1980MHz W-CDMA Handsets • Spread-Spectrum Systems • Commercial and Consumer Systems • Portable Battery-Powered Equipment 2 POWER AMPLIFIERS Product Description The RF5176 is a high-power, high-efficiency linear amplifier IC targeting 3V handheld systems. The device is manufactured on an advanced Gallium Arsenide Heterojunction Bipolar Transistor (HBT) process, and has been designed for use as the final RF amplifier in 3V CDMA-2000 and W-CDMA handsets as well as other applications in the 1850MHz to 2000MHz band. The device is self-contained, and the output can be easily matched to obtain optimum power, efficiency, and linearity characteristics over all recommended supply voltages. The device has a continuously variable bias circuit to allow idle current to be optimized for a given output power. 1.00 0.90 0.60 0.24 typ 4.00 sq. 4 PLCS 0.65 0.30 3 0.20 2.10 sq. 12° MAX 0.05 Dimensions in mm. 0.75 0.50 0.50 Note orientation of package. 0.23 0.13 4 PLCS NOTES: 1 Shaded lead is Pin 1. 2 Pin 1 identifier must exist on top surface of package by identification mark or feature on the package body. Exact shape and size is optional. 3 Dimension applies to plated terminal: to be measured between 0.02 mm and 0.25 mm from terminal end. 4 Package Warpage: 0.05 mm max. 5 Die Thickness Allowable: 0.305 mm max. Optimum Technology Matching® Applied Si BJT Si Bi-CMOS ü NC Package Style: LCC, 20-Pin, 4x4 GaAs HBT SiGe HBT GaAs MESFET Si CMOS RF IN Features • Single 3V Supply • 27dBm Linear Output Power • 26dB Linear Gain • 40% Linear Efficiency • On-board Power Down Mode Q1B 18 NC 20 VREG1 1 VCC BIAS 2 19 17 NC 16 15 NC 14 NC Bias VREG2 3 VS2 4 BIAS GND 5 6 NC 13 VCC1 12 VCC1 11 NC 7 8 RF OUT 9 RF OUT 10 RF OUT Ordering Information RF5176 RF5176 PCBA 3V W-CDMA Power 1900MHZ/ 3V Linear Power Amplifier Fully Assembled Evaluation Board Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com Functional Block Diagram NC RF Micro Devices, Inc. 7628 Thorndike Road Greensboro, NC 27409, USA Rev A0 010910 2-197 RF5176 Absolute Maximum Ratings Parameter Supply Voltage (RF off) Supply Voltage (POUT ≤ 31dBm) Bias Voltage (VBIAS) Preliminary Rating +8.0 +5.0 +3.0 +3.0 +6 -30 to +100 -30 to +150 Unit VDC VDC VDC VDC dBm °C °C Caution! ESD sensitive device. RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s). 2 POWER AMPLIFIERS Control Voltage (VREG) Input RF Power Operating Case Temperature Storage Temperature Parameter Overall Usable Frequency Range Typical Frequency Range Linear Gain Second Harmonic (including second harmonic trap) Third Harmonic Maximum Linear Output Power (W-CDMA Modulation) Total Linear Efficiency Adjacent Channel Power Rejection@5MHz Adjacent Channel Power Rejection@10MHz Noise Power Input VSWR Output Load VSWR Specification Min. Typ. Max. Unit Condition T=25°C, VCC =3.4V, Freq=1920MHz to 1980MHz, VREG =2.5V, unless otherwise specified 1850 1850 to 1910 1920 to 1980 26 -55 -50 27 40 -40 -50 -144 < 2:1 2000 MHz MHz MHz dB dBc dBc dBm % POUT =27dBm POUT =27dBm, W-CDMA Modulation, 3GPP 3.2 03-00 DPCCH + 1 DPDCH POUT =27dBm, W-CDMA Modulation, 3GPP 3.2 03-00 DPCCH + 1 DPDCH POUT =+27dBm, Rx Band 2110MHz to 2170MHz No oscillations V mA µA ns µA V V -38 -48 dBc dBc dBm/Hz 5:1 3.0 3.4 80 10 5.0 Power Supply Power Supply Voltage Idle Current VREG Current Turn On/Off time Total Current (Power down) VREG “Low” Voltage VREG “High” Voltage VREG =2.5V Total pins 1 and 3, VREG =2.5V VREG =Low See Alternative Biasing Network table following the application schematic. 0 2.5 10 0.2 2-198 Rev A0 010910 Preliminary Pin 1 Function VREG1 Description Bias control for the first stage. Needs to be divided down from its nominal value of 2.5V using a resistive divider network of 240kΩ and 360kΩ. VREG1 and VREG2 may be adjusted to minimize idle current for a given output power. Alternative VREG voltages can be used as defined on the application schematic. Supply for bias circuits. Bias control for the second stage. Needs to be divided down from its nominal value of 2.5V using a resistive divider network of 240kΩ and 240kΩ. Alternative VREG voltages can be used as defined on the application schematic. Second stage bias circuit source. For best linearity, decouple with bypassing capacitors of 15pF and 100nF. Connect to ground plane via a 15nH inductor. DC return for the second stage bias circuit. Not currently used. Not currently used. RF output and power supply for the final stage. This is the unmatched collector of the final stage. It requires an output matching network, including a DC blocking capacitor. Same as pin 8. Same as pin 8. Not currently used. Power supply for the first stage and interstage match. Requires a shunt capacitor of 12pF close to the pin for optimum match. Same as pin 12. Not currently used. Not currently used. RF input. Requires a blocking capacitor and shunt inductor to provide 2:1 VSWR. Not currently used. Base bias for first stage. For best linearity, decouple with 15pF and 100nF capacitors. Not currently used. Not currently used. Ground connection. The backside of the package should be soldered to a top side ground pad which is connected to the ground plane with multiple vias. The pad should have a short thermal path to the ground plane. RF5176 Interface Schematic 2 3 VCC BIAS VREG2 2 POWER AMPLIFIERS 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pkg Base VS2 BIAS GND NC NC RF OUT RF OUT RF OUT NC VCC1 VCC1 NC NC RF IN NC Q1B NC NC GND Rev A0 010910 2-199 RF5176 Application Schematic RF IN 100 nF 1.5 nH Preliminary 2 POWER AMPLIFIERS R6 360 kΩ VREG R8 240 kΩ R7 240 kΩ R5 240 kΩ 20 1 2 15 pF 5.6 pF 19 18 17 16 15 14 W = 0.028" L = 0.060" 10 nH 1 µF 4.7 µF VCC Bias 3 4 13 12 11 12 pF 10 nF VCC BIAS 100 nF 15 pF 15 nH 5 6 7 8 9 10 16 nH W = 0.028" L = 0.060" 15 pF 10 nF 1 µF 3.6 pF VCC = 3.4 V VREG = 2.5 V VCC BIAS = 3.4 V ER = 4.7 H = 14 mils 3 pF W = 0.028" L = 0.120" 15 pF RF OUT Alternative Biasing Networks for Various VREG Voltages VREG (V) 2.50 2.60 2.70 2.80 2.90 R5 (1ST) kΩ 240 240 240 240 220 R6 (1ST-GND) kΩ 360 330 300 270 240 R7 (2ND-GND) kΩ 240 360 200 220 180 R8 (2ND) kΩ 240 380 230 270 240 2-200 Rev A0 010910 Preliminary Evaluation Board Schematic (Download Bill of Materials from www.rfmd.com.) RF5176 J1 RF IN C3 100 nF C2 15 pF C1 5.6 pF L1 1.5 nH P1 P1 1 VCC CON1 P2 1 VREG CON1 P3 1 VCCBIAS CON1 P4 1 GND CON1 P1 C4 12 pF C5 10 nF C6 + 1 µF C11 + 4.7 µF 2 POWER AMPLIFIERS P2 R6 360 kΩ P2 R8 240 kΩ R7 240 kΩ C7 15 pF L3 15 nH R5 240 kΩ 20 1 2 19 18 17 16 15 14 W = 0.028" L = 0.060" P3 L4 10 nH Bias 3 4 5 6 13 12 11 7 8 9 10 L2 16 nH P3 C16 100 nF VCC = 3.4 V VREG = 2.5 V VCC BIAS = 3.4 V ER = 4.7 H = 14 mils W = 0.028" L = 0.060" C8 15 pF C9 10 nF C10 + 1 µF C12 3.6 pF C13 3 pF W = 0.028" L = 0.120" 15 pF J2 RF OUT Rev A0 010910 2-201 RF5176 Evaluation Board Layout Board Size 2.0" x 2.0" Board Thickness 0.028”, Board Material FR-4, Multi-Layer Ground Plane at 0.014” Preliminary 2 POWER AMPLIFIERS 2-202 Rev A0 010910