RF6886PCK-411

RF6886 RF68863.6V, 100MHz to 1000 MHz Linear Power Amplifier 3.6V, 100MHz TO 1000MHz LINEAR POWER AMPLIFIER Features  100MHz to 1000MHz  Single 3.6V Power Supply  34dBm OP1dB   36.5dBm Saturated Output Power >50% Efficiency 23 22 21 20 Vreg1 NC 24 NC VBias Pwr Ref Package: QFN, 24-Pin, 4mmx4mm 19 18 RFout 2 17 RFout Vcc 3 16 RFout NC 4 15 RFout Vreg2 5 14 RFout RFin 6 13 RFout Vcc 1 Vcc Bias Applications      7 CDMA/GSM/EDGE Repeater Final Amplifier NC 450MHz and 865MHz to 955MHz ISM Band Amplifier General Purpose High Power Amplifier TETRA Handheld/Walkie-Talkie Final Amplifier HPA Driver 8 9 10 11 12 NC NC NC NC NC Functional Block Diagram Product Description The RF6886 is a linear, high power, high efficiency amplifier designed to use as a final stage/driver in linear or saturated transmit applications. The device is manufactured on an advanced InGaP HBT process and is provided in a 24-pin leadless chip carrier with backside ground. External matching allows for use in standard bands from 100MHz to 1000MHz. Ordering Information RF6886SR RF6886SQ RF6886TR7 RF6886TR13 RF6886PCK-410 RF6886PCK-411 7” Reel with 100 pieces Sample bag with 25 pieces 7” Reel with 750 pieces 13” Reel with 2500 pieces 865MHz to 955MHz PCBA with 5-piece sample bag 433MHz to 470MHz PCBA with 5-piece sample bag Optimum Technology Matching® Applied GaAs HBT GaAs MESFET InGaP HBT  SiGe BiCMOS Si BiCMOS SiGe HBT GaAs pHEMT Si CMOS Si BJT GaN HEMT BiFET HBT LDMOS RF MICRO DEVICES®, RFMD®, Optimum Technology Matching®, Enabling Wireless Connectivity™, PowerStar®, POLARIS™ TOTAL RADIO™ and UltimateBlue™ are trademarks of RFMD, LLC. BLUETOOTH is a trademark owned by Bluetooth SIG, Inc., U.S.A. and licensed for use by RFMD. All other trade names, trademarks and registered trademarks are the property of their respective owners. ©2006, RF Micro Devices, Inc. DS140303 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. 1 of 16 RF6886 Absolute Maximum Ratings Parameter Rating Unit VC2 Collector Quiescent Bias Current (ICQ2) 350 mA VC1 Collector Quiescent Bias Current (ICQ1) 150 mA Maximum Supply Current (ICC1 +ICC2) 3100 mA Device Voltage (VD) 4.0 V Power Dissipation 5 W -40 to +85 °C Max RF Input 50 Output Load 12 dBm Max RF Output 50 Load 38 dBm Operating Lead Temperature (TAMBIENT) Output Load VSWR See Theory of Operation Section Storage Temperature Range -40 to +150 °C Operating Junction Temperature (TJ) 150 °C ESD Rating - Human Body Model (HBM) Class 1A V Moisture Sensitivity Level (MSL) MSL1 Parameter Min. Specification Typ. Max. Unit Typical Electrical Specifications for 433MHz to 470MHz Operating Frequency OP1dB Small SIgnal Gain Saturated Output Power (PSAT) Saturated Efficiency Condition See 433MHz to 470MHz Evaluation Board Schematic 433 450 34.5 470 MHz VCC =3.6V, VREG1 =VREG2 =3.1V, ICQ total=390mA dBm 33 dB 36.8 dBm 55 % Saturated Output Power (PSAT) 36.3 dBm Saturated Efficiency 54.5 % Saturated Output Power (PSAT) VCC=3.3V, VREG1=VREG2=3.1V, ICQ total=380mA 35.2 dBm Saturated Efficiency 53 % TETRA ADJ Channel Power -38 dBc VCC=3.6V, VREG1 =VREG2 =2.7V, ICQ total=187mA TETRA ALT Channel Power -53 dBc TETRA: PAR=2.6dB, POUT =32dBm, 24.3kHz channel BW, ADJ offset=25kHz, ALT offset=50kHz CDMA ADJ Channel Power -50 dBc CDMA ALT Channel Power -67 dBc 2 of 16 VCC=3.0V, VREG1=VREG2=3.1V, ICQ total=370mA CDMA: PAR=4.5dB, POUT =32dBm, 1.23MHz channel BW, ADJ CH offset/BW=750kHz/30kHz, ALT CH offset/BW=1.98MHz/30kHz 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. DS140303 RF6886 Parameter Min. Specification Typ. Max. Unit Condition See 865MHz to 955MHz Evaluation Board Schematic. TA =25 °C Operating Frequency 865 OP1dB 900 955 33.5 Small Signal Gain 29 Saturated Output Power (PSAT) 31.0 33.5 36.2 Saturated Efficiency 50 MHz VCC =3.6V, VREG1 =VREG2 =3.1V, ICQ total=390mA dBm dB Frequency = 900MHz dBm 54 % Saturated Output Power (PSAT) 35.5 dBm Saturated Efficiency 53.5 % Saturated Output Power (PSAT) 34.4 dBm Saturated Efficiency 52.5 % CDMA ADJ Channel Power -52 dBc CDMA ALT Channel Power -66 dBc CDMA: PAR=4.5dB, POUT =31.5dBm, 1.23MHz channel BW, ADJ CH offset/BW=750kHz/30kHz, ALT CH offset/BW=1.98MHz/30kHz VCC =3.6V, VREG1 =VREG2 =3.1V Quiescent Current (ICQ) VCC=3.0V, VREG1=VREG2=3.1V ICQ total=370mA 390 420 mA Leakage Current 5 10 uA VCC =3.6V, VREG1 =VREG2 =0V Current at VREG1 and VREG2 (IREG1 and IREG2) 3 mA VCC =3.6V, VREG1 =VREG2 =3.1V. VREG1/2 supplied through 220 bias resistance (see evaluation board schematic). Thermal Resistance, RTH 11 °C/W DS140303 340 VCC=3.3V, VREG1=VREG2=3.1V ICQ total=380mA 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. 3 of 16 RF6886 Pin 1, 2, 3 Function VCC1 5 6 VREG2 RF IN Description Interface Schematic Inter-stage match and bias for first stage output. Connect inter-stage matching capacitor to pin with a short trace. Connect low frequency bypass capacitor to this pin with a long trace. See evaluation board layout for detail. This pin requires a regulated supply to set output stage DC bias. RF Input. An external blocking capacitor is required if this pin is connected to DC path. VCC Bond Wire Inductance RF IN BIAS 4, 7-12, 20, 21 13, 14, 15, 16, 17, 18 19 22 23 NC RF OUT No Connect. RF Output and bias for the output stage. The power supply for the output transistor needs to be supplied to this pin. This can be done through an RF inductor that supports the required DC currents. RF OUT BIAS VREG1 VCC BIAS PWR SENSE This pin requires a regulated supply to set driver stage DC bias. Bias circuitry supply voltage. PWR SEN and PWR REF pins can be used in conjunction with an external feedback path to provide an RF power control function for the RF6886. The power control function is based on sampling the RF drive to the final stage of the RF6886. RF OUT PWR SEN PWR REF BIAS 24 Pkg Base 4 of 16 PWR REF GND Same as pin 23. Ground connection. The backside of the package should be connected to the ground plane through a short path, i.e., vias under the device are required. 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. DS140303 RF6886 Theory of Operation This section provides specific guidelines for operation of RF6886. Applications can generally be placed into two categories: 1. High power applications • Output power ranging between 34.5 - 36.5dBm • Efficiency >50% in band of interest 2. Linear applications • RF6886 shows linearity along the lines of a handset power amplifier in terms of adjacent channel power (ACP) performance, with the distinct advantage of obtaining ACP compliance at >2x comparative output power. Resultant output power for linear operation will depend on the waveform being considered. All pertinent specifications and performance curves are seen in the tabular and graph sections of the data sheet. The first standard evaluation board has been matched for 865MHz to 955MHz. Operation with VCC=3.6V shows output power >36dBm and efficiency >50%. For reduced power ranges, efficiency is maintained, with no change to output match, by lowering VCC. See data for 3.3/3.0V in the tables provided. The standard evaluation board also demonstrates impressive linearity, shown with conventional CDMA modulation. The same data set format is also provided for the 433MHz to 470MHz evaluation board. Nominal data is taken with VCC=3.6V and VREG1/2=3.1V. For linear operation, it has been shown that reducing VREG1/2 to 2.7 - 2.8V enhances performance. This can be explained by observing how the compression characteristic behaves. Operation with VREG=3.1V shows gradual (soft) compression once power exceeds 31dBm. With VREG reduced to 2.7 - 2.8V, small signal gain drops by 1 - 2dB. Self bias is now more prominent at 31dBm, and gain expansion offsets slow compression. The result is flattening of the gain characteristic, extending effective compression point out in power. Waveform distortion is reduced as compared to the VREG=3.1V case, and adjacent channel power improves. The sole advantage in using VREG=3.1V would be a slightly higher value for saturated output power. Low thermal resistance enables reliable high power operation, provided that output load is set to achieve efficiency equal to or better than that seen on the RFMD evaluation boards. The maximum rating for output load VSWR on page 2 calls out requirement for discussion in this section. RF6886 has shown excellent performance into 50, but any system using it as a final amplifier will have to take VSWR variation into account. Test on properly matched evaluation board has shown that rated output power is obtained with 10dBm at RF input. Practically speaking then, at or near 10dBm would be a maximum reasonable limit for input power. When considering VSWR variation, ruggedness is one of the main considerations. Ruggedness here, being the worse case VSWR which can be tolerated for a transient period without damage to the device. The following maximum VSWR limits apply: VCC Freq POUT into 50 Load (Across Band) Maximum Practical Input Drive Maximum Output VSWR (Survival) V MHz dBm dBm 3.6 865 to 955 36.2 to 35.2 10 3.5:1 3.3 35.5 to 34.4 10 5.0:1 3 34.4 to 33.4 8 5.0:1 37 to 36.4 10 3.5:1 3.3 36.3 to 35.6 10 5.0:1 3 35.2 to 34.5 8 5.0:1 3.6 DS140303 433 to 470 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. 5 of 16 RF6886 In each case, VSWR was tested over phase, with device on/off cycle done several times at phase angle where current was maximum. Test showed that the best off/on sequence for RF6886 is as follows: Turn on: 1. Apply VCC 2. Apply VREF1/2 3. Apply drive at RF input Turn off: 1. Remove drive at RF input 2. Bring down voltage at VREF1/2 3. Bring down VCC (not necessary in system of course) Many systems will use closed loop power control. When taking output VSWR variation into account, the limits in table above still apply, with same practical maximum limit on RF drive. At some phase angles, higher output powers will not be attainable. Thus, a limit on maximum drive should be taken into account to prevent overdrive of the device by power control circuit. The VSWR limits set here apply to the most demanding case, where input drive is set for maximum output power. For example, Pout >36dBm, VCC=3.6V, Pin=10dBm. It is entirely conceivable that the amplifier be used in a linear application at backed off power. In that case, it follows that a higher VSWR could be tolerated. As an example, consider 32dBm output power with VCC=3.6V. Test showed that power control loop would achieve 32dBm from 865MHz to 955MHz over phase into 5:1 VSWR. The increased VSWR specification as compared to the 3:5:1 limit in table comes about for the following reason: The harshest condition is encountered at phase angle where 10dBm drive results in forward power >38.5dBm and current > >3000mA. A power control loop sensing forward (coupled) power would back input drive down in this case and prevent damage. That provided it reacts quickly enough. The more limiting factor in this case, phase angle for lowest power presents a situation where target power cannot be achieved. That even if drive is allowed to go beyond practical maximum. But because the amplifier was seen to achieve 32dBm over phase along with ruggedness, the increased VSWR specification becomes reasonable in the presence of power control and lower output power requirement. So, a multitude of scenarios could exist, with test being required to determine allowable VSWR specification. Power control can be implemented via several different methodologies, using circuitry external to RF6886. One method already touched upon, sampling forward coupled output power and feedback to adjust at one of two points in the system: 1. With constant drive level at RF6886 input, adjust voltage level at VREG1 and/or VREG2. VREG1/2 can be tied together, or one of the two can be kept constant with the other adjusted. 2. With VREF1/2 constant, RF drive at device input can be adjusted via feedback to a system control point behind RF6886. Two RF6886 output pins are also available for use in a power control scheme, PWR SENSE (pin 23) and PWR REF (pin 24). Viewing the evaluation board schematics, it can be seen that both pins are tied to VCC through 390 resistors. Both pins sink current, resulting in following voltages at respective board connectors: V_PWR REF = VCC - 390*I_PWR_REF V_PWR SENSE = VCC - 390*I_PWR_SENSE 6 of 16 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. DS140303 RF6886 V_PWR_REF output pin yields a voltage proportional to DC component of total output stage drive current, while V_PWR_SENSE output pin does likewise for DC + RF components. Subtraction between these voltages gives result proportional to RF current only, and therefore output power as well. Graphs of Log 10 (V_PWR REF - V_PWR SENSE) vs. RF6886 power out are shown for two scenarios: 1. RF drive at device input = constant 10dBm, with ramp at VREG1/2. 2. VREG1/2 = constant 3.1V, with RF drive ramp from 0 - 10dBm. In both cases, it can be seen that output power versus Log of this difference maintains a linear relationship up to 33.5dBm. Non-linear behavior past 33.5dBm is caused by 2 contributors: 1. Compression beginning to take effect at RF6886 1st and/or 2nd stage. 2. PWR_REF and PWR_SENSE transistor collector voltage reduction and associated compression. Note that changing 390 value will influence curve shape and shift graphs up/down on y-axis. As an additional exercise to investigate #2 above, like graphs are shown for 180 pull up resistor vs. 390. With 180 in place, internal PWR_REF and PWR_SENSE transistors retain higher collector voltage, and do not enter into compression. As a result, we see altered curves as compared to 390 case. Log (V_PWR_REF - V_PWR_SENSE) continue to increase, with increasing slope, vs. output power. One other interesting data point, the curve for ramp at VREG1/2 now closely resembles that for ramp at RF input. The curves will remain consistent for a given frequency and temperature provided the following remain constant: 1. REF/SENSE resistance (Does not change value in design. This only noted for clarity) 2. Output load VSWR Practically speaking then, this method offers a relatively simple approach, with presumably less accuracy as compared to closed loop control which couples forward power at output. In the coupled power method, VSWR variation will of course also impact accuracy. Here are general schematics for approaches utilizing PWR_REF/PWR_SENSE pins in described power control schemes: Approach 1: DS140303 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. 7 of 16 RF6886 Approach 2: Approach #1 feeds back to variable gain stage behind RF6886. Approach #2 utilizes feedback to VREG1/2 pins of RF6886. Recall Log of the Loop Reference Voltage is shown in graphs for both methods. In the circuits shown above, no Log function is performed. Data for V_delta = (V_PWR_REF - V_PWR_SENSE) vs. Output Power out is collected, and Loop Reference Voltage is set to V_delta(s) for corresponding Output Power(s). Data can be collected at selected frequency and temperature points, depending on accuracy desired in a particular application. Next, a discussion covering RF6886 used in balanced configuration. The application as depicted here: This configuration can be implemented with readily available surface mount hybrid couplers, and offers significant performance and reliability advantages. Use single ended RF6886 3.6V specifications for reference: 1. >38.5dBm output power 2. Linear performance with 2.5dB increase in power for equivalent adjacent channel power specification 3. Immunity to antenna VSWR variation 8 of 16 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. DS140303 RF6886 One key consideration will be output side isolated port 50 termination resistance. In the case where output VSWR deviates significantly from 50, reflected power will be absorbed in the isolated port. This will require placement of resistor bank capable of handling power dissipation while fault condition exists. Finally, consider the maximum allowable operating device voltage, listed at 4.0V in the table on page 2. Operating with VCC =4.0 V enables higher compression point, which becomes attractive in two types of applications: 1. High power, high efficiency 2. Linear, requiring specification compliance at higher power level Viewing curves in the graph section, it can be seen that device junction temperature stays below 150°C (85°C ambient) up to rated power levels. Junction temperature becomes a more critical specification with higher operating voltage. It should be stressed again here that a properly matched output load impedance is required to provide high efficiency. Load impedance has been measured on both standard evaluation boards. The table below contains that data: Standard Evaluation Board Load Impedance Freq MHz A+jB MHz A+jB 865 1.983+j 0.157 433 1.997-j 0.941 900 1.983+j 0.579 450 1.866-j 0.251 928 1.953+j 0.789 470 1.778-j 0.268 955 1.969+j 0.914 Freq Standard Evaluation Board Load Impedance In any application where greater than 3.6V operation is being considered, use of an isolator at RF6886 output is recommended. This, of course, excludes the balanced configuration already discussed. The recommendation would also hold for VCC 3.6V, in cases where potential output VSWR conditions exceed those outlined previously in this section. DS140303 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. 9 of 16 RF6886 Evaluation Board Schematic 433MHz to 470MHz Vreg1 Key locations shown in red type. Output capacitors are Johanson Hi-Q tight tolerance 10uF Vcc 10uF Vreg2 390  390  PWR SEN PWR REF 10uF 1uF 1uF 1uF 0 24 23 22 21 20 19 18 1 Bias 220  2.2 uF 100 pF 0 jumpers in place of ferrites used on 865 MHz to 955 MHz board 2.2 uF 1uF RF IN 0 220  1 uF 220 pF @ C46 0 22 pF 2 17 3 16 4 15 5 14 6 13 7 8 9 10 11 12.55nH Coilcraft 1606 0 2.2 uF 100 pF RF OUT 10 pF @ C16 27//10//1.2 pF @ C17/18/19 12 8.2 nH @ L3 10 of 16 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. DS140303 RF6886 Evaluation Board Schematic 865MHz to 955MHz Vreg1 Key locations shown in red type. Output capacitors are Johanson Hi-Q tight tolerance 10uF Vcc 10uF Vreg2 390  390  PWR SEN PWR REF 10uF 1uF 1uF 220  1 uF @ C4 220 pF @ C6 2.2 uF 1uF 24 23 22 21 20 19 18 1 Bias 220  2.2 uF RF IN 39 pF 2 A, low DC resistance ferrites (see evaluation board BOM) 1uF 2 17 3 16 4 15 5 14 6 13 7.5 pF 7 8 9 10 11 5.6 nH Coilcraft 1606 1.5 nH 27 pF 39 pF RF OUT 15//12//10 pF @ C8//C13//C14 5.6/0.5 pF @ C17/C18 12 2.7 nH @ L3 DS140303 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. 11 of 16 RF6886 Typical Electrical Performance, 25°C: 433MHz to 470MHz Evaluation Board Schematic 865MHz to 955MHz Evaluation Board 12 of 16 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. DS140303 RF6886 Thermal Performance, 900MHz, 85°C: DS140303 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. 13 of 16 RF6886 Power Control Performance, REF/SENSE Pull-Up Resistance=390, 25°C: 865MHz to 955MHz Evaluation Board, Constant Power at RF IN, Ramp at VREG1/2 865MHz to 955MHz Evaluation Board, Power Ramp at RF IN, Constant 3.1V at VREG1/2 14 of 16 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. DS140303 RF6886 Power Control Performance, REF/SENSE Pull-Up Resistance=180, 25°C: 865MHz to 955MHz Evaluation Board, Constant Power at RF IN, Ramp at VREG1/2 865MHz to 955MHz Evaluation Board, Power Ramp at RF IN, Constant 3.1V at VREG1/2 DS140303 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. 15 of 16 RF6886 Package Drawing PCB Patterns A = 0.234 x 0.475 (mm) B = 0.475 x 0.234 (mm) C = 1.125 x 1.125 (mm) A = 0.400 x 0.668 (mm) B = 0.668 x 0.400 (mm) C = 2.840 x 2.840 (mm) A = 0.260 x 0.528 (mm) B = 0.528 x 0.260 (mm) C = 2.700 x 2.700 (mm) 10x 0.266 10x 0.100 A 12x 0.250 10x 0.100 A A A A A B 2x 1.250 B B 2x 0.750 B B 2x 0.250 0.000 B B 2x 0.250 B B 2x 0.750 B 2x 1.250 12x 0.110 B B 2x 1.250 B 2x 0.750 B B 2x 0.250 0.000 B B 2x 0.250 B B 2x 0.750 B 2x 1.250 C B A A C C 2x 1.250 B 2x 0.750 B 2x 0.725 2x 0.250 B 0.000 2x 0.250 2x 0.325 C B C B B B 6x 1.864 6x 1.864 A 2x 1.250 2x 1.250 A 2x 0.750 2x 0.750 PCB METAL PATTERN A 2x 0.250 2x 0.250 A 6x 1.864 0.000 2x 0.250 A 2x 0.750 A 2x 1.250 A 6x 1.864 B 12x 0.339 B 6x 1.864 A 6x 1.864 A 2x 0.250 0.000 2x 1.250 6x 1.864 A 2x 0.750 B A 2x 0.325 10x 0.240 12x 0.110 12x 0.250 A A B B 10x 0.240 C A A 12x 0.339 B B B A 6x 1.864 A A PCB SOLDER MASK PATTERN A A A A 2x 0.750 2x 0.725 2x 1.250 6x 1.864 6x 1.864 6x 1.864 2x 1.250 A 2x 0.750 A 2x 0.250 2x 0.725 A 2x 0.750 A 2x 0.725 2x 0.250 0.000 A 2x 1.250 A 6x 1.864 10x 0.240 PCB STENCIL PATTERN Thermal vias for center slug "C" should be incorporated into the PCB design. The number and size of thermal vias will depend on the application, the power dissipation, and the electrical requirements. Example of the number and size of vias can be found on the RFMD evaluation board layout. Notes: 1. Shaded are represents Pin 1. 16 of 16 7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. DS140303