RFM95/96/97/98（W）
RFM95/96/97/98(W) - Low Power Long Range Transceiver Module
V1.0
GENERAL DESCRIPTION
The
RFM95/96/97/98(W) transceivers
feature
the
LoRaTM long range modem that provides ultra-long range
spread spectrum communication and high interference
immunity whilst minimising current consumption.
Using Hope RF’s patented LoRaTM modulation technique
RFM95/96/97/98(W) can achieve a sensitivity of over 148dBm using a low cost crystal and bill of materials. The
high sensitivity combined with the integrated +20 dBm
power amplifier yields industry leading link budget
making it optimal for any application requiring range or
robustness. LoRaTM also provides significant advantages in
both blocking and selectivity over conventional modulation
techniques, solving the traditional design compromise
between range, interference immunity and energy
consumption.
These devices also support high performance (G)FSK
modes for systems including WMBus, IEEE802.15.4g. The
RFM95/96/97/98(W) deliver exceptional phase noise,
selectivity, receiver linearity and IIP3 for significantly
lower current consumption than competing devices.
KEY PRODUCT FEATURES
LoRaTM Modem.
168 dB maximum link budget.
+20 dBm - 100 mW constant RF output vs. V supply.
+14 dBm high efficiency PA.
Programmable bit rate up to 300 kbps.
High sensitivity: down to -148 dBm.
Bullet-proof front end: IIP3 = -12.5 dBm.
Excellent blocking immunity.
Low RX current of 10.3 mA, 200 nA register retention.
Fully integrated synthesizer with a resolution of 61 Hz.
FSK, GFSK, MSK, GMSK, LoRaTM and OOK modulation.
Built-in bit synchronizer for clock recovery.
Preamble detection.
127 dB Dynamic Range RSSI.
Automatic RF Sense and CAD with ultra-fast AFC.
Packet engine up to 256 bytes with CRC.
Built-in temperature sensor and low battery indicator.
Modue Size：16*16mm
RFM95/96/97/98(W)
APPLICATIONS
Automated Meter Reading.
Home and Building Automation.
Wireless Alarm and Security Systems.
Industrial Monitoring and Control
Long range Irrigation Systems
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Page 1
RFM95/96/97/98（W）
Section
1.
2.
Page
General Description ................................................................................................................................................. 9
1.1.
Simplified Block Diagram ................................................................................................................................. 9
1.2.
Product Versions .........................................................................................................................................10
1.3.
Pin Diagram ................................................................................................................................................... 10
1.4.
Pin Description ............................................................................................................................................... 11
Electrical Characteristics ....................................................................................................................................... 12
2.1. ESD Notice .................................................................................................................................................... 12
2.2. Absolute Maximum Ratings ........................................................................................................................... 12
2.3. Operating Range............................................................................................................................................ 12
2.4.
Chip Specification .......................................................................................................................................13
2.4.1. Power Consumption .................................................................................................................................. 13
2.4.2. Frequency Synthesis ................................................................................................................................. 13
2.4.3. FSK/OOK Mode Receiver ......................................................................................................................... 14
2.4.4. FSK/OOK Mode Transmitter ..................................................................................................................... 15
2.4.5. Electrical specification for LoraTM modulation .......................................................................................... 16
2.4.6. Digital Specification ................................................................................................................................... 19
3.
RFM95/96/97/98(W) Features ................................................................................................................................ 20
3.1. LoRaTM Modem ............................................................................................................................................. 21
3.2. FSK/OOK Modem ........................................................................................................................................... 21
4.
RFM95/96/97/98(W) Digital Electronics ................................................................................................................. 22
4.1. The LoRaTM Modem ..................................................................................................................................... 22
4.1.1. Link Design Using the LoRaTM Modem .................................................................................................23
4.1.2. LoRaTM Digital Interface ........................................................................................................................29
4.1.3. Operation of the LoRaTM Modem ............................................................................................................. 31
4.1.4. Frequency Settings ................................................................................................................................32
4.1.5. LoRaTM Modem State Machine Sequences ...........................................................................................33
4.2. FSK/OOK Modem .......................................................................................................................................... 41
4.2.1. Bit Rate Setting ......................................................................................................................................... 41
4.2.2. FSK/OOK Transmission ............................................................................................................................ 42
4.2.3. FSK/OOK Reception ................................................................................................................................. 43
4.2.4. Operating Modes in FSK/OOK Mode ........................................................................................................ 50
4.2.5. Startup Times ............................................................................................................................................ 50
4.2.6. Receiver Startup Options .......................................................................................................................... 53
4.2.7. Receiver Restart Methods ......................................................................................................................... 54
4.2.8. Top Level Sequencer ................................................................................................................................ 55
4.2.9. Data Processing in FSK/OOK Mode ......................................................................................................... 60
4.2.10. FIFO .....................................................................................................................................................61
4.2.11. Digital IO Pins Mapping ........................................................................................................................... 64
4.2.12. Continuous Mode .................................................................................................................................... 65
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Page 2
RFM95/96/97/98（W）
Section
Page
4.2.13. Packet Mode ........................................................................................................................................... 66
4.2.14. io-homecontrol® Compatibility Mode ...................................................................................................... 74
4.3.
5.
SPI Interface .................................................................................................................................................. 75
RFM95/96/97/98(W) Analog & RF Frontend Electronics........................................................................................ 76
5.1. Power Supply Strategy .................................................................................................................................. 76
5.2. Low Battery Detector ..................................................................................................................................... 76
5.3. Frequency Synthesis ..................................................................................................................................... 76
5.3.1. Crystal Oscillator ....................................................................................................................................... 76
5.3.2. CLKOUT Output ........................................................................................................................................ 77
5.3.3. PLL ............................................................................................................................................................ 77
5.3.4. RC Oscillator ............................................................................................................................................. 77
5.4.
Transmitter Description ...............................................................................................................................78
5.4.1. Architecture Description ............................................................................................................................ 78
5.4.2. RF Power Amplifiers.................................................................................................................................. 78
5.4.3. High Power +20 dBm Operation ............................................................................................................... 79
5.4.4. Over Current Protection .........................................................................................................................80
5.5. Receiver Description ...................................................................................................................................... 80
5.5.1. Overview ................................................................................................................................................... 80
5.5.2. Receiver Enabled and Receiver Active States .......................................................................................... 80
5.5.3. Automatic Gain Control In FSK/OOK Mode .............................................................................................. 80
5.5.4. RSSI in FSK/OOK Mode ........................................................................................................................... 81
5.5.5. RSSI in LoRaTM Mode ............................................................................................................................. 82
5.5.6. Channel Filter ............................................................................................................................................ 82
5.5.7. Temperature Measurement ....................................................................................................................... 83
6.
Description of the Registers.................................................................................................................................... 84
6.1. Register Table Summary ............................................................................................................................... 84
6.2.
FSK/OOK Mode Register Map....................................................................................................................... 87
6.3. Band Specific Additional Registers .............................................................................................................. 100
6.4. LoRaTM Mode Register Map ....................................................................................................................... 102
7.
Application Information ........................................................................................................................................ 108
7.1. Crystal Resonator Specification ................................................................................................................... 108
7.2. Reset of the Chip ......................................................................................................................................... 108
7.2.1. POR......................................................................................................................................................... 108
7.2.2. Manual Reset .......................................................................................................................................109
7.3. Top Sequencer: Listen Mode Examples ...................................................................................................... 109
7.3.1. Wake on Preamble Interrupt ................................................................................................................... 109
7.3.2. Wake on SyncAddress Interrupt ...........................................................................................................112
7.4.
Top Sequencer: Beacon Mode .................................................................................................................115
7.4.1. Timing diagram........................................................................................................................................ 115
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Page 3
RFM95/96/97/98(W)
Section
Page
7.4.2. Sequencer Configuration......................................................................................................................... 115
8.
7.5.
Example CRC Calculation ........................................................................................................................117
7.6.
Example Temperature Reading ................................................................................................................118
Packaging Information ......................................................................................................................................... 119
8.1.
8.2.
Package Outline Drawing ............................................................................................................................ 119
Recommended Land Pattern ....................................................................................................................... 120
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Page 4
RFM95/96/97/98(W)
Section
Page
Table 1. RFM95/96/97/98(W) Device Variants and Key Parameters .............................................................................10
Table 2. Absolute Maximum Ratings .............................................................................................................................12
Table 3. Operating Range .............................................................................................................................................12
Table 4. Power Consumption Specification ...................................................................................................................13
Table 5. Frequency Synthesizer Specification ..............................................................................................................13
Table 6. FSK/OOK Receiver Specification ....................................................................................................................14
Table 7. Transmitter Specification .................................................................................................................................15
Table 8. LoRa Receiver Specification. ..........................................................................................................................17
Table 9. Digital Specification .........................................................................................................................................19
Table 10. Example LoRaTM Modem Performances .....................................................................................................22
Table 11. Range of Spreading Factors ..........................................................................................................................24
Table 12. Cyclic Coding Overhead ................................................................................................................................24
Table 13. LoRaTM Operating Mode Functionality .........................................................................................................31
Table 14. LoRa CAD Consumption Figures ..................................................................................................................40
Table 15. DIO Mapping LoRaTM Mode .........................................................................................................................41
Table 16. Bit Rate Examples .........................................................................................................................................42
Table 17. Preamble Detector Settings ...........................................................................................................................48
Table 18. RxTrigger Settings to Enable Timeout Interrupts ..........................................................................................49
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Basic Transceiver Modes ..............................................................................................................................50
Receiver Startup Time Summary ..................................................................................................................51
Receiver Startup Options ..............................................................................................................................54
Sequencer States ..........................................................................................................................................55
Sequencer Transition Options .......................................................................................................................56
Sequencer Timer Settings .............................................................................................................................58
Status of FIFO when Switching Between Different Modes of the Chip .........................................................62
DIO Mapping, Continuous Mode ...................................................................................................................64
DIO Mapping, Packet Mode ..........................................................................................................................64
CRC Description ...........................................................................................................................................72
Power Amplifier Mode Selection Truth Table ................................................................................................78
High Power Settings ......................................................................................................................................79
Operating Range, +20dBm Operation ...........................................................................................................79
Operating Range, +20dBm Operation ...........................................................................................................79
Trimming of the OCP Current ........................................................................................................................80
LNA Gain Control and Performances ............................................................................................................81
RssiSmoothing Options .................................................................................................................................82
Available RxBw Settings ................................................................................................................................82
Registers Summary .......................................................................................................................................84
Register Map .................................................................................................................................................87
Low Frequency Additional Registers ...........................................................................................................100
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Page 5
RFM95/96/97/98(W)
Section
Page
Table 40. High Frequency Additional Registers ..........................................................................................................101
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Crystal Specification ....................................................................................................................................108
Listen Mode with PreambleDetect Condition Settings .................................................................................111
Listen Mode with PreambleDetect Condition Recommended DIO Mapping ...............................................111
Listen Mode with SyncAddress Condition Settings .....................................................................................114
Listen Mode with PreambleDetect Condition Recommended DIO Mapping ...............................................114
Beacon Mode Settings ................................................................................................................................116
Revision History ...........................................................................................................................................121
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Page 6
RFM95/96/97/98(W)
Section
Page
Figure 1. Block Diagram ...............................................................................................................................................9
Figure 2. Pin Diagrams ...............................................................................................................................................10
Figure 3. RFM95/96/97/98(W) Block Schematic Diagram ..........................................................................................20
Figure 4. LoRaTM Modem Connectivity ......................................................................................................................23
Figure 5. Interrupts generated in the case of successful frequency hopping communication. .....................................28
Figure 6. Channel activity detection (CAD) time as a function of spreading factor ......................................................39
Figure 7. Consumption Profile of the LoRa CAD Process ............................................................................................40
Figure 8. OOK Peak Demodulator Description .............................................................................................................44
Figure 9. Floor Threshold Optimization ........................................................................................................................45
Figure 10. Bit Synchronizer Description .......................................................................................................................46
Figure 11. FEI Process .................................................................................................................................................47
Figure 12. Startup Process ...........................................................................................................................................50
Figure 13. Time to Rssi Sample ...................................................................................................................................52
Figure 14. Tx to Rx Turnaround ...................................................................................................................................52
Figure 15. Rx to Tx Turnaround ...................................................................................................................................52
Figure 16. Receiver Hopping ........................................................................................................................................53
Figure 17. Transmitter Hopping ....................................................................................................................................53
Figure 18. Timer1 and Timer2 Mechanism ...................................................................................................................57
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Sequencer State Machine ...........................................................................................................................59
RFM95/96/97/98(W) Data Processing Conceptual View .............................................................................60
FIFO and Shift Register (SR) ......................................................................................................................61
FifoLevel IRQ Source Behavior ...................................................................................................................62
Sync Word Recognition ...............................................................................................................................63
Continuous Mode Conceptual View ............................................................................................................65
Tx Processing in Continuous Mode .............................................................................................................65
Rx Processing in Continuous Mode ............................................................................................................66
Packet Mode Conceptual View ...................................................................................................................67
Fixed Length Packet Format .......................................................................................................................68
Variable Length Packet Format ...................................................................................................................69
Unlimited Length Packet Format .................................................................................................................69
Manchester Encoding/Decoding .................................................................................................................73
Data Whitening Polynomial .........................................................................................................................74
SPI Timing Diagram (single access) ...........................................................................................................75
TCXO Connection .......................................................................................................................................76
RF Front-end Architecture Shows the Internal PA Configuration. ...............................................................78
Temperature Sensor Response ..................................................................................................................83
POR Timing Diagram ................................................................................................................................108
Manual Reset Timing Diagram ..................................................................................................................109
Listen Mode: Principle ...............................................................................................................................109
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Page 7
RFM95/96/97/98(W)
Section
Page
Figure 40. Listen Mode with No Preamble Received .................................................................................................110
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Listen Mode with Preamble Received .......................................................................................................110
Wake On PreambleDetect State Machine .................................................................................................111
Listen Mode with no SyncAddress Detected .............................................................................................112
Listen Mode with Preamble Received and no SyncAddress .....................................................................112
Listen Mode with Preamble Received & Valid SyncAddress ....................................................................113
Wake On SyncAddress State Machine .....................................................................................................113
Beacon Mode Timing Diagram ..................................................................................................................115
Beacon Mode State Machine ....................................................................................................................115
Example CRC Code ..................................................................................................................................117
Example Temperature Reading ................................................................................................................118
Package Outline Drawing ..........................................................................................................................119
Recommended Land Pattern ....................................................................................................................120
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Page 8
RFM95/96/97/98(W)
WIRELESS & SENSING
PRELIMINARY
DATASHEET
1. General Description
The RFM95/96/97/98(W) incorporates the LoRaTM spread spectrum modem which is capable of achieving significantly
longer range than existing systems based on FSK or OOK modulation. With this new modulation scheme sensitivities 8 dB
better than FSK can be achieved with a low-cost, low-tolerance, crystal reference. This increase in link budget provides
much longer range and robustness without the need for external amplification. LoRaTM also provides significant
advances in selectivity and blocking performance, further improving communication reliability. For maximum flexibility the
user may decide on the spread spectrum modulation bandwidth (BW), spreading factor (SF) and error correction rate (CR).
Another benefit of the spread modulation is that each spreading factor is orthogonal - thus multiple transmitted signals can
occupy the same channel without interfering. This also permits simple coexistence with existing FSK based systems.
Standard GFSK, FSK, OOK, and GMSK modulation is also provided to allow compatibility with existing systems or
standards such as wireless MBUS and IEEE 802.15.4g.
The RFM97 offers bandwidth options ranging from 7.8 kHz to 500 kHz with spreading factors ranging from 6 to 12, and
covering all available frequency bands. The RFM97 offers the same bandwidth and frequency band options with
spreading factors from 6 to 9. The RFM98 offers bandwidths and spreading factor options, but only covers the lower UHF
bands.
1.1. Simplified Block Diagram
Figure 1. Block Diagram
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RFM95/96/97/98(W)
WIRELESS & SENSING
PRELIMINARY
DATASHEET
1.2. Product Versions
The features of the three product variants are detailed in the following table.
Table 48 RFM95/96/97/98(W) Device Variants and Key Parameters
Part Number
Frequency Range
Spreading Factor
Bandwidth
Effective Bitrate
Est. Sensitivity
RFM95W
868/915 MHz
6 - 12
7.8 - 500 kHz
.018 - 37.5 kbps
-111 to -148 dBm
RFM97W
868/915 MHz
6-9
7.8 - 500 kHz
0.11 - 37.5 kbps
-111 to -139 dBm
433/470MHz
6- 12
7.8 - 500 kHz
.018 - 37.5 kbps
-111 to -148 dBm
RFM96W/RFM98W
1.3. Pin Diagram
The following diagram shows the pin arrangement , top view.
Figure 2. Pin Diagrams
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RFM95/96/97/98(W)
WIRELESS & SENSING
PRELIMINARY
DATASHEET
1.4. Pin Description
Number
Name
Type
Description
Description Stand Alone Mode
1
GND
-
Ground
2
MISO
I
SPI Data output
3
MOSI
O
SPI Data input
4
SCK
I
SPI Clock input
5
NSS
I
SPI Chip select input
6
RESET
I/O
Reset trigger input
7
DIO5
I/O
Digital I/O, software configured
8
GND
-
Ground
9
ANT
-
RF signal output/input.
10
GND
-
Ground
11
DIO3
I/O
Digital I/O, software configured
12
DIO4
I/O
Digital I/O, software configured
13
3.3V
-
Supply voltage
14
DIO0
I/O
Digital I/O, software configured
15
DIO1
I/O
Digital I/O, software configured
16
DIO2
I/O
Digital I/O, software configured
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RFM95/96/97/98(W)
WIRELESS & SENSING
PRELIMINARY
DATASHEET
2. Electrical Characteristics
2.1. ESD Notice
The RFM95/96/97/98(W) is a high performance radio frequency device. It satisfies:
Class 2 of the JEDEC standard JESD22-A114-B (Human Body Model) on all pins.
Class III of the JEDEC standard JESD22-C101C (Charged Device Model) on all pins
It should thus be handled with all the necessary ESD precautions to avoid any permanent damage.
2.2. Absolute Maximum Ratings
Stresses above the values listed below may cause permanent device failure. Exposure to absolute maximum ratings for
extended periods may affect device reliability.
Table 49 Absolute Maximum Ratings
Symbol
Description
Min
Max
Unit
VDDmr
Supply Voltage
-0.5
3.9
Tmr
Temperature
-55
+115
°C
Tj
Junction temperature
-
+125
°C
Pmr
RF Input Level
-
+10
dBm
Min
Max
Note
V
Specific ratings apply to +20 dBm operation (see Section 5.4.3).
2.3. Operating Range
Table 50 Operating Range
Symbol
Description
Unit
VDDop
Supply voltage
1.8
3.7
V
Top
Operational temperature range
-20
+70
°C
Clop
Load capacitance on digital ports
-
25
pF
ML
RF Input Level
-
+10
dBm
Note
A specific supply voltage range applies to +20 dBm operation (see Section 5.4.3).
Page 12
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RFM95/96/97/98(W)
WIRELESS & SENSING
PRELIMINARY
DATASHEET
2.4. Chip Specification
The tables below give the electrical specifications of the transceiver under the following conditions: Supply voltage
VDD=3.3 V, temperature = 25 °C, FXOSC = 32 MHz, FRF = 169/434/868/915 MHz (see specific indication), Pout =
+13dBm, 2-level FSK modulation without pre-filtering, FDA = 5 kHz, Bit Rate = 4.8 kb/s and terminated in a matched 50
Ohm impedance, shared Rx and Tx path matching., unless otherwise specified.
2.4.1. Power Consumption
Table 51 Power Consumption Specification
Symbol
Description
Conditions
Min
Typ
Max
Unit
-
0.2
1
uA
IDDSL
Supply current in Sleep mode
IDDIDLE
Supply current in Idle mode
RC oscillator enabled
-
1.5
-
uA
IDDST
Supply current in Standby mode
Crystal oscillator enabled
-
1.6
1.8
mA
IDDFS
Supply current in Synthesizer
mode
FSRx
-
5.8
-
mA
IDDR
Supply current in Receive mode
LnaBoost Off, higher bands
LnaBoost On, higher bands
Lower bands
-
10.8
11.5
12.1
-
mA
IDDT
Supply current in Transmit mode
with impedance matching
RFOP = +20 dBm, on PA_BOOST
RFOP = +17 dBm, on PA_BOOST
RFOP = +13 dBm, on RFO_LF/HF pin
RFOP = + 7 dBm, on RFO_LF/HF pin
-
120
87
29
20
-
mA
mA
mA
mA
2.4.2. Frequency Synthesis
Table 52 Frequency Synthesizer Specification
Symbol
Description
Conditions
Typ
Max
Unit
137
410
862
-
175
525
1020
MHz
FR
Synthesizer frequency range
FXOSC
Crystal oscillator frequency
-
32
-
MHz
TS_OSC
Crystal oscillator wake-up time
-
250
-
us
TS_FS
Frequency synthesizer wake-up
time to PllLock signal
-
60
-
us
-
20
20
50
50
50
50
50
-
us
us
us
us
us
us
us
-
61.0
-
Hz
TS_HOP
Frequency synthesizer hop time
at most 10 kHz away from the target frequency
FSTEP
Frequency synthesizer step
Programmable
Min
From Standby mode
200 kHz step
1 MHz step
5 MHz step
7 MHz step
12 MHz step
20 MHz step
25 MHz step
FSTEP = FXOSC/219
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RFM95/96/97/98(W)
WIRELESS & SENSING
PRELIMINARY
FRC
RC Oscillator frequency
After calibration
BRF
Bit rate, FSK
BRO
DATASHEET
-
62.5
-
kHz
Programmable values (1)
1.2
-
300
kbps
Bit rate, OOK
Programmable
1.2
-
32.768
kbps
BRA
Bit Rate Accuracy
ABS(wanted BR - available BR)
-
-
250
ppm
FDA
Frequency deviation, FSK (1)
Programmable
FDA + BRF/2 =< 250 kHz
0.6
-
200
kHz
Note
For Maximum Bit rate the maximum modulation index is 0.5.
2.4.3. FSK/OOK Mode Receiver
All receiver tests are performed with RxBw = 10 kHz (Single Side Bandwidth) as programmed in RegRxBw, receiving a
PN15 sequence. Sensitivities are reported for a 0.1% BER (with Bit Synchronizer enabled), unless otherwise specified.
Blocking tests are performed with an unmodulated interferer. The wanted signal power for the Blocking Immunity, ACR,
IIP2, IIP3 and AMR tests is set 3 dB above the receiver sensitivity level.
Table 53 FSK/OOK Receiver Specification
Symbol
Description
Conditions
Min
Typ
Max
Unit
Direct tie of RFI and RFO pins,
shared Rx, Tx paths FSK sensitivity, highest LNA gain.
Lower frequency bands
FDA = 5 kHz, BR = 1.2 kb/s
FDA = 5 kHz, BR = 4.8 kb/s
FDA = 40 kHz, BR = 38.4 kb/s*
FDA = 20 kHz, BR = 38.4 kb/s**
FDA = 62.5 kHz, BR = 250 kb/s***
-
-121
-117
-107
-108
-95
-
dBm
dBm
dBm
dBm
dBm
Split RF paths, the RF switch
insertion loss is not accounted for.
Lower frequency bands
FDA = 5 kHz, BR = 1.2 kb/s
FDA = 5 kHz, BR = 4.8 kb/s
FDA = 40 kHz, BR = 38.4 kb/s*
FDA = 20 kHz, BR = 38.4 kb/s**
FDA = 62.5 kHz, BR = 250 kb/s***
-
-123
-119
-109
-110
-97
-
dBm
dBm
dBm
dBm
dBm
Direct tie of RFI and RFO pins,
shared Rx, Tx paths FSK sensitivity, highest LNA gain.
Higher frequency bands
FDA = 5 kHz, BR = 1.2 kb/s
FDA = 5 kHz, BR = 4.8 kb/s
FDA = 40 kHz, BR = 38.4 kb/s*
FDA = 20 kHz, BR = 38.4 kb/s**
FDA = 62.5 kHz, BR = 250 kb/s***
-
-119
-115
-105
-105
-92
-
dBm
dBm
dBm
dBm
dBm
Split RF paths, LnaBoost is turned
on, the RF switch insertion loss is
not accounted for.
Higher frequency bands
FDA = 5 kHz, BR = 1.2 kb/s
FDA = 5 kHz, BR = 4.8 kb/s
FDA = 40 kHz, BR = 38.4 kb/s*
FDA = 20 kHz, BR = 38.4 kb/s**
FDA = 62.5 kHz, BR = 250 kb/s***
-
-123
-119
-109
-109
-96
-
dBm
dBm
dBm
dBm
dBm
RFS_O
OOK sensitivity, highest LNA gain
shared Rx, Tx paths
BR = 4.8 kb/s
BR = 32 kb/s
-
-117
-108
-
dBm
dBm
CCR
Co-Channel Rejection
-
-9
-
dB
RFS_F_LF
RFS_F_HF
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ACR
Adjacent Channel Rejection
FDA = 5 kHz, BR=4.8kb/s
Offset = +/- 25 kHz or +/- 50kHz
169MHz Band
434 MHz Band
8-900 MHz Band
BI_HF
Blocking Immunity, higher bands
Offset = +/- 1 MHz
Offset = +/- 2 MHz
Offset = +/- 10 MHz
-
71
76
84
-
dB
dB
dB
BI_LF
Blocking Immunity, lower bands
Offset = +/- 1 MHz
Offset = +/- 2 MHz
Offset = +/- 10 MHz
-
71
72
78
-
dB
dB
dB
IIP2
2nd order Input Intercept Point
Unwanted tones are 20 MHz
above the LO
Highest LNA gain
-
+55
-
dBm
IIP3_HF
3rd order Input Intercept point
Unwanted tones are 1MHz and
1.995 MHz above the LO
Higher bands
Highest LNA gain G1
LNA gain G2, 4dB sensitivity hit
-
-12.5
-8.5
-
dBm
dBm
IIP3_LF
3rd order Input Intercept point
Unwanted tones are 1MHz and
1.995 MHz above the LO
Lower bands
Highest LNA gain G1
LNA gain G2, 2.5dB sensitivity hit
-
-22
-16
-
dBm
dBm
BW_SSB
Single Side channel filter BW
Programmable
2.7
-
250
kHz
IMR
Image Rejection
Wanted signal 3dB over sensitivity
BER=0.1%
-
48
-
dB
IMA
Image Attenuation
-
57
-
dB
DR_RSSI
RSSI Dynamic Range
-
-127
0
-
dBm
dBm
AGC enabled
*
RxBw = 83 kHz (Single Side Bandwidth)
**
RxBw = 50 kHz (Single Side Bandwidth)
***
RxBw = 250 kHz (Single Side Bandwidth)
Min
Max
-
59
56
50
-
dB
dB
dB
2.4.4. FSK/OOK Mode Transmitter
Table 54 Transmitter Specification
Symbol
Description
RF output power in 50 ohms
on RFO pin (High efficiency PA).
RF_OP
ΔRF_
RF output power stability on RFO
pin versus voltage supply.
OP_V
RF_OPH
RF output power in 50 ohms, on
PA_BOOST pin (Regulated PA).
Conditions
Min
Typ
Max
Unit
+11
-
+14
-1
-
dBm
dBm
-
3
8
-
dB
dB
-
+17
+2
-
dBm
dBm
Programmable with steps
Max
Min
VDD = 2.5 V to 3.3 V
VDD = 1.8 V to 3.7 V
Programmable with 1dB steps
Max
Min
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RFM95/96/97/98(W)
RF_OPH_
MAX
Max RF output power, on
PA_BOOST pin
ΔRF_
RF output power stability on PA_BOOST pin versus voltage supply.
OPH_V
ΔRF_T
RF output power stability versus
temperature on PA_BOOST pin.
High power mode
-
+20
-
dBm
-
+/-1
-
dB
-
+/-1
-
dB
10kHz Offset
50kHz Offset
400kHz Offset
1MHz Offset
-
-118
-118
-128
-132
-
dBc/
Hz
10kHz Offset
50kHz Offset
400kHz Offset
1MHz Offset
-
-109
-109
-121
-128
-
dBc/
Hz
10kHz Offset
50kHz Offset
400kHz Offset
1MHz Offset
-
-103
-103
-115
-122
-
dBc/
Hz
dBm
VDD = 2.4 V to 3.7 V
From T = -40 °C to +85 °C
169 MHz band
433 MHz band
PHN
Transmitter Phase Noise
868/915 MHz band
ACP
Transmitter adjacent channel
power (measured at 25 kHz offset)
BT=1. Measurement conditions as
defined by EN 300 220-1 V2.3.1
-
-
-37
TS_TR
Transmitter wake up time, to the
first rising edge of DCLK
Frequency Synthesizer enabled, PaRamp = 10us, BR = 4.8 kb/s
-
120
-
us
2.4.5. Electrical specification for LoraTM modulation
The table below gives the electrical specifications for the transceiver operating with LoraTM modulation. Following
conditions apply unless otherwise specified:
Supply voltage = 3.3 V.
Temperature = 25° C.
fXOSC = 32 MHz.
Lower bands: 169 MHz and 433 MHz, higher bands: 868 and 915 MHz
bandwidth (BW) = 125 kHz.
Spreading Factor (SF) = 12.
Error Correction Code (EC) = 4/6.
Packet Error Rate (PER)= 1%
CRC on payload enabled.
Output power = 13 dBm in transmission.
Payload length = 64 bytes.
Preamble Length = 12 symbols (programmed register PreambleLength=8)
With matched impedances
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Table 55 LoRa Receiver Specification.
Symbol
Description
Conditions
Supply current in receiver LoraTM
mode, LnaBoost off
IDDR_L
Supply current in transmitter mode
IDDT_L
IDDT_H_L
Supply current in transmitter mode
with an external impedance
transformation
Min.
Typ
Max
Unit
Lower Bands, Lower BW
Lower Bands, BW = 125 kHz
Lower Bands, BW = 250 kHz
Lower Bands, BW = 500 kHz
-
TBC
11.5
12.4
13.8
-
mA
mA
mA
mA
Higher Bands, Lower BW
Higher Bands, BW = 125 kHz
Higher Bands, BW = 250 kHz
Higher Bands, BW = 500 kHz
-
TBC
10.3
11.1
12.6
-
mA
mA
mA
mA
RFOP = 13 dBm
RFOP = 7 dBm
-
28
20
-
mA
mA
Using PA_BOOST pin
RFOP = 17 dBm
-
90
-
mA
offset = +/- 1 MHz
offset = +/- 2 MHz
offset = +/- 10 MHz
-
TBC
TBC
TBC
-
-12.5
-8.5
-
dBm
dBm
-
-22
-16
-
dBm
dBm
-
+55
-
dBm
0.018
-
37.5
kbps
BI_L
Blocking immunity, FRF=868 MHz
CW interferer
IIP3_L_HF
3rd order Input Intercept point
Higher bands
Unwanted tones are 1MHz and 1.995 Highest LNA gain G1
MHz above the LO
LNA gain G2, 4dB sensitivity hit
IIP3_L_LF
Lower bands
3rd order Input Intercept point
Highest LNA gain G1
Unwanted tones are 1MHz and 1.995
LNA gain G2, 2.5dB sensitivity
MHz above the LO
hit
IIP2_L
BR_L
RFS_L10
RFS_L62
dB
dB
dB
2nd order input intercept point,
highest LNA gain, FRF=868 MHz,
CW interferer.
F1 = FRF + 20 MHz
F2 = FRF+ 20 MHz + Δf
Bit rate, Long-Range Mode
From SF6, BW=500kHz to
SF12, BW=7.8kHz
RF sensitivity, Long-Range Mode,
highest LNA gain, LNA boost for
higher bands, using split Rx/Tx path
10.4 kHz bandwidth
SF = 6
SF = 7
SF = 8
SF = 9
SF = 10
SF = 11
SF = 12
-
TBC
-134
TBC
TBC
TBC
TBC
TBC
-
dBm
dBm
dBm
dBm
dBm
dBm
dBm
RF sensitivity, Long-Range Mode,
highest LNA gain, LNA boost for
higher bands, using split Rx/Tx path
62.5 kHz bandwidth
SF = 6
SF = 7
SF = 8
SF = 9
SF = 10
SF = 11
SF = 12
-
-121
-126
-129
-132
-135
-137
-139
-
dBm
dBm
dBm
dBm
dBm
dBm
dBm
Table 56. Electrical specifications: LoraTM mode
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Symbol
PRELIMINARY
Min.
Typ
Max
Unit
RF sensitivity, Long-Range Mode,
highest LNA gain, LNA boost for
higher bands, using split Rx/Tx path
125 kHz bandwidth
SF = 6
SF = 7
SF = 8
SF = 9
SF = 10
SF = 11
SF = 12
-
-118
-123
-126
-129
-132
-133
-136
-
dBm
dBm
dBm
dBm
dBm
dBm
dBm
RF sensitivity, Long-Range Mode,
highest LNA gain, LNA boost for
higher bands, using split Rx/Tx path
250 kHz bandwidth
SF = 6
SF = 7
SF = 8
SF = 9
SF = 10
SF = 11
SF = 12
-
-115
-120
-123
-125
-128
-130
-133
-
dBm
dBm
dBm
dBm
dBm
dBm
dBm
RF sensitivity, Long-Range Mode,
highest LNA gain, LNA boost for
higher bands, using split Rx/Tx path
500 kHz bandwidth
SF = 6
SF = 7
SF = 8
SF = 9
SF = 10
SF = 11
SF = 12
-
-111
-116
-119
-122
-125
TBC
TBC
-
dBm
dBm
dBm
dBm
dBm
dBm
dBm
CCR_LCW
Co-channel rejection
Single CW tone = Sens +6 dB
1% PER
SF = 7
SF = 8
SF = 9
SF = 10
SF = 11
SF = 12
-
5
9.5
12
14.4
17
19.5
-
dB
dB
dB
dB
dB
dB
CCR_LL
Co-channel rejection
Interferer is a LoRaTM signal
using same BW and same SF.
Pw = Sensitivity + 3 dB
RFS_L125
RFS_L250
RFS_L500
ACR_LCW
IMR_LCW
FERR_L
Description
Conditions
DATASHEET
-6
dB
Interferer is 1.5*BW_L from the
wanted signal center frequency
1% PER, Single CW tone =
Sens + 3 dB
Adjacent channel rejection
SF = 7
SF = 12
-
60
72
-
dB
dB
1% PER, Single CW tone =
Sens +3 dB
-
66
-
dB
BW_L = 10.4 kHz
Maximum tolerated frequency offset BW_L = 62.5 kHz
between transmitter and receiver, no BW_L = 125 kHz
BW_L = 250 kHz
sensitivity degradation, SF6 thru 9
BW_L = 500 kHz
-2.5
-15
-30
-60
-120
-
2.5
15
30
60
120
kHz
kHz
kHz
kHz
kHz
Maximum tolerated frequency offset SF = 12
between transmitter and receiver, no SF = 11
sensitivity degradation, SF10 thru 11 SF = 10
-50
-100
-200
-
50
100
200
ppm
ppm
ppm
Image rejection after calibration.
Table 56. Electrical specifications: LoraTM mode
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2.4.6. Digital Specification
Conditions: Temp = 25° C, VDD = 3.3 V, FXOSC = 32 MHz, unless otherwise specified.
Table 57 Digital Specification
Symbol
Description
Conditions
Min
Typ
Max
Unit
VIH
Digital input level high
0.8
-
-
VDD
VIL
Digital input level low
-
-
0.2
VDD
VOH
Digital output level high
Imax = 1 mA
0.9
-
-
VDD
VOL
Digital output level low
Imax = -1 mA
-
-
0.1
VDD
FSCK
SCK frequency
-
-
10
MHz
tch
SCK high time
50
-
-
ns
tcl
SCK low time
50
-
-
ns
trise
SCK rise time
-
5
-
ns
tfall
SCK fall time
-
5
-
ns
tsetup
MOSI setup time
From MOSI change to SCK rising
edge.
30
-
-
ns
thold
MOSI hold time
From SCK rising edge to MOSI
change.
20
-
-
ns
tnsetup
NSS setup time
From NSS falling edge to SCK rising
edge.
30
-
-
ns
tnhold
NSS hold time
From SCK falling edge to NSS rising
edge, normal mode.
100
-
-
ns
tnhigh
NSS high time between SPI
accesses
20
-
-
ns
T_DATA
DATA hold and setup time
250
-
-
ns
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RFM95/96/97/98(W)
3. RFM95/96/97/98(W) Features
This section gives a high-level overview of the functionality of the RFM95/96/97/98(W) low-power, highly integrated
transceiver. The following figure shows a simplified block diagram of the RFM95/96/97/98(W).
Figure 3. RFM95/96/97/98(W) Block Schematic Diagram
RFM95/96/97/98(W) is a half-duplex, low-IF transceiver. Here the received RF signal is first amplified by the LNA. The
LNA inputs are single ended to minimise the external BoM and for ease of design. Following the LNA inputs, the
conversion to differential is made to improve the second order linearity and harmonic rejection. The signal is then downconverted to in- phase and quadrature (I&Q) components at the intermediate frequency (IF) by the mixer stage. A pair of
sigma delta ADCs then perform data conversion, with all subsequent signal processing and demodulation performed in
the digital domain. The digital state machine also controls the automatic frequency correction (AFC), received signal
strength indicator (RSSI) and automatic gain control (AGC). It also features the higher-level packet and protocol level
functionality of the top level sequencer (TLS).
The frequency synthesisers generate the local oscillator (LO) frequency for both receiver and transmitter, one covering the
lower UHF bands (up to 525 MHz), and the other one covering the upper UHF bands (from 860 MHz). The PLLs are
optimized for user-transparent low lock time and fast auto-calibrating operation. In transmission, frequency modulation is
performed digitally within the PLL bandwidth. The PLL also features optional pre-filtering of the bit stream to improve
spectral purity.
RFM95/96/97/98(W) feature three distinct RF power amplifiers. Two of those, connected to RFO_LF and RFO_HF, can
deliver up to +14 dBm, are unregulated for high power efficiency and can be connected directly to their respective RF
receiver inputs via a pair of passive components to form a single antenna port high efficiency transceiver. The third PA,
connected to the PA_BOOST pin and can deliver up to +20 dBm via a dedicated matching network. Unlike the high
efficiency PAs, this high- stability PA covers all frequency bands that the frequency synthesizer addresses.
RFM95/96/97/98(W) also include two timing references, an RC oscillator and a 32 MHz crystal
oscillator.
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All major parameters of the RF front end and digital state machine are fully configurable via an SPI interface which gives
access to RFM95/96/97/98(W)’s configuration registers. This includes a mode auto sequencer that oversees the
transition and calibration of the RFM95/96/97/98(W) between intermediate modes of operation in the fastest time possible.
The RFM95/96/97/98(W) are equipped with both standard FSK and long range spread spectrum (LoRaTM) modems.
Depending upon the mode selected either conventional OOK or FSK modulation may be employed or the LoRaTM spread
spectrum modem.
3.1. LoRaTM Modem
The LoRaTM modem uses a proprietary spread spectrum modulation technique. This modulation, in contrast to legacy
modulation techniques, permits an increase in link budget and increased immunity to in-band interference. At the same
time the frequency tolerance requirement of the crystal reference oscillator is relaxed - allowing a performance increase for
a reduction in system cost. For a fuller description of the design trade-offs and operation of the RFM95/96/97/98(W)
please consult Section 4.1 of the datasheet.
3.2. FSK/OOK Modem
In FSK/OOK mode the RFM95/96/97/98(W) supports standard modulation techniques including OOK, FSK, GFSK, MSK
and GMSK. The RFM95/96/97/98(W) is especially suited to narrow band communication thanks the low-IF architecture
employed and the built-in AFC functionality. For full information on the FSK/OOK modem please consult Section 4.2 of this
document.
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4. RFM95/96/97/98(W) Digital Electronics
4.1. The LoRaTM Modem
The LoRaTM modem uses spread spectrum modulation and forward error correction techniques to increase the range and
robustness of radio communication links compared to traditional FSK or OOK based modulation. Examples of the
performance improvement possible, for several possible settings, are summarised in the table below. Here the spreading
factor and error correction rate are design variables that allow the designer to optimise the trade-off between occupied
bandwidth, data rate, link budget improvement and immunity to interference.
Table 58 Example LoRaTM Modem Performances
Bandwidth
(kHz)
10.4
20.8
62.5
125
Spreading Factor
Coding rate
Nominal Rb
(bps)
Sensitivity
indication
(dBm)
6
12
6
12
6
12
6
12
4/5
4/5
4/5
4/5
4/5
4/5
4/5
4/5
782
24
1562
49
4688
146
9380
293
TBC
TBC
TBC
TBC
-121
-139
-118
-136
Frequency
Reference
TCXO
XTAL
For European operation the range of crystal tolerances acceptable for each sub-band (of the ERC 70-03) is given in the
specifications table. For US based operation a frequency hopping mode is available that automates both the LoRaTM spread
spectrum and frequency hopping spread spectrum processes.
Another important facet of the LoRaTM modem is its increased immunity to interference. The LoRaTM modem is capable of
co-channel GMSK rejection of up to 25 dB. This immunity to interference permits the simple coexistence of LoRaTM
modulated systems either in bands of heavy spectral usage or in hybrid communication networks that use LoRaTM to extend
range when legacy modulation schemes fail.
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4.1.1. Link Design Using the LoRaTM Modem
4.1.1.1. Overview
The LoRaTM modem is setup as shown in the following figure. This configuration permits the simple replacement of the FSK
modem with the LoRaTM modem via the configuration register setting RegOpMode. This change can be performed on the
fly (in Sleep operating mode) thus permitting the use of both standard FSK or OOK in conjunction with the long range
capability. The LoRaTM modulation and demodulation process is proprietary, it uses a form of spread spectrum modulation
combined with cyclic error correction coding. The combined influence of these two factors is an increase in link budget and
enhanced immunity to interference.
Figure 4. LoRaTM Modem Connectivity
A simplified outline of the transmit and receive processes is also shown above. Here we see that the LoRaTM modem has an
independent dual port data buffer FIFO that is accessed through an SPI interface common to all modes. Upon selection of
LoRaTM mode, the configuration register mapping of the RFM95/96/97/98(W) changes. For full details of this change
please consult the register description of Section 6.
So that it is possible to optimise the LoRaTM modulation for a given application, access is given to the designer to three
critical design parameters. Each one permitting a trade off between link budget, immunity to interference, spectral
occupancy and nominal data rate. These parameters are spreading factor, modulation bandwidth and error coding rate.
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4.1.1.2. Spreading Factor
The spread spectrum LoRaTM modulation is performed by representing each bit of payload information by multiple chips of
information. The rate at which the spread information is sent is referred to as the symbol rate (Rs), the ratio between the
nominal symbol rate and chip rate is the spreading factor and represents the number of symbols sent per bit of information.
The range of values accessible with the LoRaTM modem are shown in the following table.
Table 59 Range of Spreading Factors
SpreadingFactor
(RegModulationCfg)
Spreading Factor
(Chips / symbol)
LoRa Demodulator
SNR
6
7
8
9
10
11
12
64
128
256
512
1024
2048
4096
-5 dB
-7.5 dB
-10 dB
-12.5 dB
-15 dB
-17.5 dB
-20 dB
Note that the spreading factor, SpreadingFactor, must be known in advance on both transmit and receive sides of the link
as different spreading factors are orthogonal to each other. Note also the resulting signal to noise ratio (SNR) required at
the receiver input. It is the capability to receive signals with negative SNR that increases the sensitivity, so link budget and
range, of the LoRa receiver.
Spreading Factor 6
SF = 6 Is a special use case for the highest data rate transmission possible with the LoRa modem. To this end several
settings must be activated in the RFM95/96/97/98(W) registers when it is in use:
Set SpreadingFactor = 6 in RegModemConfig2
The header must be set to Implicit mode
Write bits 2-0 of register address 0x31 to value "0b101"
Write register address 0x37 to value 0x0C
4.1.1.3. Coding Rate
To further improve the robustness of the link the LoRaTM modem employs cyclic error coding to perform forward error
detection and correction. Such error coding incurs a transmission overhead - the resultant additional data overhead per
transmission is shown in the table below.
Table 60 Cyclic Coding Overhead
CodingRate
(RegTxCfg1)
Cyclic Coding
Rate
Overhead Ratio
1
2
3
4
4/5
4/6
4/7
4/8
1.25
1.5
1.75
2
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Forward error correction is particularly efficient in improving the reliability of the link in the presence of interference. So that
the coding rate (and so robustness to interference) can be changed in response to channel conditions - the coding rate can
optionally be included in the packet header for use by the receiver. Please consult Section 4.1.1.6 for more information on
the LoRaTM packet and header.
4.1.1.4. Signal Bandwidth
An increase in signal bandwidth permits the use of a higher effective data rate, thus reducing transmission time at the
expense of reduced sensitivity improvement. There are of course regulatory constraints in most countries on the
permissible occupied bandwidth. Contrary to the FSK modem which is described in terms of the single sideband
bandwidth, the LoRaTM modem bandwidth refers to the double sideband bandwidth (or total channel bandwidth). The range
of bandwidths relevant to most regulatory situations is given in the LoRaTM modem specifications table (see Section 2.4.5).
Note
4.1.1.5.
Bandwidth
(kHz)
Spreading Factor
Coding rate
Nominal Rb
(bps)
7.8
10.4
15.6
20.8
31.2
41.7
62.5
125
250
500
12
12
12
12
12
12
12
12
12
12
4/5
4/5
4/5
4/5
4/5
4/5
4/5
4/5
4/5
4/5
18
24
37
49
73
98
146
293
586
1172
In the lower band (169 MHz), the 250 kHz and 500 kHz bandwidths are not supported.
LoRaTM Transmission Parameter Relationship
With a knowledge of the key parameters that can be controlled by the user we define the LoRaTM symbol rate as:
W
--Rs = -----SF
2
where BW is the programmed bandwidth and SF is the spreading factor. The transmitted signal is a constant envelope
signal. Equivalently, one chip is sent per second per Hz of bandwidth.
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4.1.1.6. LoRaTM Packet Structure
The LoRaTM modem employs two types of packet format, explicit and implicit. The explicit packet includes a short header
that contains information about the number of bytes, coding rate and whether a CRC is used in the packet. The packet
format is shown in the following figure.
The LoRaTM packet comprises three elements:
A preamble.
An optional header.
The data payload.
Figure 5. LoRaTM Packet Structure
Preamble
The preamble is used to synchronize receiver with the incoming data flow. By default the packet is configured with a 12
symbol long sequence. This is a programmable variable so the preamble length may be extended, for example in the
interest of reducing to receiver duty cycle in receive intensive applications. However, the minimum length suffices for all
communication. The transmitted preamble length may be changed by setting the register PreambleLength from 6 to 65535,
yielding total preamble lengths of 6+4 to 65535+4 symbols, once the fixed overhead of the preamble data is considered.
This permits the transmission of a near arbitrarily long preamble sequence.
The receiver undertakes a preamble detection process that periodically restarts. For this reason the preamble length
should be configured identical to the transmitter preamble length. Where the preamble length is not known, or can vary, the
maximum preamble length should be programmed on the receiver side.
Header
Depending upon the chosen mode of operation two types of header are available. The header type is selected by the
ImplictHeaderMode bit found within the RegSymbTimeoutMsb register.
Explicit Header Mode
This is the default mode of operation. Here the header provides information on the payload, namely:
The payload length in bytes.
The forward error correction code rate
The presence of an optional 16-bits CRC for the payload.
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The header is transmitted with maximum error correction code (4/8). It also has its own CRC to allow the receiver to
discard invalid headers.
Implicit Header Mode
In certain scenarios, where the payload, coding rate and CRC presence are fixed or known in advance, it may be
advantageous to reduce transmission time by invoking implicit header mode. In this mode the header is removed from the
packet. In this case the payload length, error coding rate and presence of the payload CRC must be manually configured
on both sides of the radio link.
Note
With SF = 6 selected, implicit header mode is the only mode of operation possible.
Payload
The packet payload is a variable-length field that contains the actual data coded at the error rate either as specified in the
header in explicit mode or in the register settings in implicit mode. An optional CRC may be appended. For more
information on the payload and how it is loaded from the data buffer FIFO please see Section 4.1.2.3.
4.1.1.7. Time on air
For a given combination of spreading factor (SF), coding rate (CR) and signal bandwidth (BW) the total on-the-air
transmission time of a LoRaTM packet can be calculated as follows. From the definition of the symbol rate it is convenient to
define the symbol rate:
1
Ts = ----Rs
The LoRa packet duration is the sum of the duration of the preamble and the transmitted packet. The preamble length is calculated as
follows:
T pr ea mble = (n pr ea m b l e + 4.25)T sy m
where npreamble is the programmed preamble length, PreambleLength.The payload duration depends upon the header
mode that is enabled. The following formulae give the payload duration in implicit (headerless) and explicit (with header)
modes.
T payl oad
⎧
8l pa yl oad – 4SF + 24
⎪T
8 + ceil⎛⎝ --------------------------------------------------⎞⎠ (CR + 4 )
4SF
⎪ sy m
= ⎨
⎪
⎛ 8l paylo a--d – 4SF + 44⎞ (CR + 4 )
----------------------------⎪ T sy m 8 + cei l ⎝ ------------------- 4SF
⎠
⎩
where: l payloa d > 0, implicit header
where: l
> 0, explicit header
Addition of these two durations gives the total packet on -air time.
T packe t = T pr eam b le + T pa yl oad
4.1.1.8. Frequency Hopping with
LoRaTM
Frequency hopping spread spectrum (FHSS) is typically employed when the duration of a single packet could exceed
regulatory requirements relating to the maximum permittable channel dwell time. This is most notably the case in US
operation where the 902 to 928 MHz ISM band can be used ina frequency hopping mode. To ease implementation of
FHSS systems the frequency hopping mode of the LoRaTM modem can be enabled (see FhssMode of register RegTxCfg1).
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Principle of Operation
The principle behind the FHSS scheme is that a portion of each LoRaTM packet is transmitted on each hopping channel
from a look up table of frequencies managed by the host microcontroller. After a predetermined hopping period the
transmitter and receiver change to the next channel in a predefined list of hopping frequencies to continue transmission
and reception of the next portion of the packet. The time which the transmission will dwell in any given channel is
determined by HoppingPeriod which is an integer multiple of symbol periods:
HoppingPeriod = Ts × FreqHoppingPeriod
The frequency hopping transmission and reception process starts at channel 0. The preamble and header are transmitted
first on channel 0. At the beginning of each transmission the interrupt the channel counter FhssPresentChannel is
incremented and the interrupt signal FhssChangeChannel is generated. The new frequency must then be programmed
within the hopping period to ensure it is taken into account for the next hop, the interrupt FhssChangeChannel is then to be
cleared by writing a logical ‘1’.
FHSS Reception always starts on channel 0. The receiver waits for a valid preamble detection before starting the
frequency hopping process as described above. Note that in the eventuality of header CRC corruption, the receiver will
automatically request channel 0 and recommence the valid preamble detection process.
Timing of Channel Updates
The interrupt requesting the channel change, FhssChannelChange, is generated upon transition to the new frequency. The
frequency hopping process is recapitulated in the diagram below:
Figure 6. Interrupts generated in the case of successful frequency hopping communication.
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4.1.2. LoRaTM Digital Interface
The LoRaTM modem comprises three types of digital interface, static configuration registers, status registers and a FIFO
data buffer. All are accessed through the RFM95/96/97/98(W)’s SPI interface - full details of each type of register are
given below. Full listings of the register addresses used for SPI access are given in Section 6.4.
4.1.2.1. LoRaTM Configuration Registers
Configuration registers are accessed through the SPI interface. Registers are readable in all device mode including Sleep.
However, they should be written only in Sleep and Stand-by modes. Please note that the automatic top level
sequencer (TLS modes) are not available in LoRaTM mode and the configuration register mapping changes as
shown in Table 85. The content of the LoRaTM configuration registers is retained in FSK/OOK mode. For the functionality of
mode registers common to both FSK/OOK and LoRaTM mode, please consult the Analog and RF Front End section of this
document (Section 5).
4.1.2.2. Status Registers
Status registers provide status information during receiver operation.
4.1.2.3. LoRaTM Mode FIFO Data Buffer
Overview
The RFM95/96/97/98(W) is equipped with a 256 byte RAM data buffer which is uniquely accessible in LoRa mode. This
RAM area, thereafter reffered to as the FIFO Data buffer, is fully customizable by the user and allows access to the
received, or to be transmitted, data. All access to the LoRaTM FIFO data buffer is done via the SPI interface. A diagram of
the user defined memory mapping of the FIFO data buffer is shown below. These FIFO data buffer can be read in all
operating modes except sleep and store data related to the last receive operation performed. It is automatically cleared of
old content upon each new transition to receive mode.
Figure 7. LoRaTM data buffer
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Principle of Operation
Thanks to its dual port configuration, it is possible to simultaneously store both transmit and receive information in the FIFO
data buffer. The register FifoTxBaseAddr specifies the point in memory where the transmit information is stored. Similarly,
for receiver operation, the register FifoRxBaseAddr indicates the point in the data buffer where information will be written to
in event of a receive operation.
By default, the device is configured at power-up so that half of the available memory is dedicated to Rx (FifoRxBaseAddr
initialized at address 0x00) and the other half is dedicated for Tx (FifoTxBaseAddr initialized at address 0x80).
However, due to the contiguous nature of the FIFO data buffer, the base addresses for Tx and Rx are fully configurable
across the 256 byte memory area. Each pointer can be set independently anywhere within the FIFO. To exploit the
maximum FIFO data buffer size in transmit or receive mode, the whole FIFO data buffer can be used in each mode by
setting the base addresses FifoTxBaseAddr and FifoRxBaseAddr at the bottom of the memory (0x00).
The FIFO data buffer is cleared when the device is put in SLEEP mode, consequently no access to the FIFO data buffer is
possible in sleep mode. However, the data in the FIFO data buffer are retained when switching across the other LoRa
modes of operation, so that a received packet can be retransmitted with minimum data handling on the controller side. The
FIFO data buffer is not self-clearing (unless if the device is put in sleep mode) and the data will only be “erased” when a
new set of data is written into the occupied memory location.
The actual location to be read from, or written to, over the SPI interface is defined by the address pointer FifoAddrPtr.
Before any read or write operation it is hence necessary to initialise this pointer to the corresponding base value. Upon
reading or writing to the FIFO data buffer (RegFifo) the address pointer will then increment automatically.
The register FifoRxBytesNb defines the size of the memory location to be written in the event of a successful receive
operation. On the other hand PayloadLength indicates the size of the memory location to be transmitted. In implicit header
mode, the FifoRxBytesNb is not used as the number of payload bytes is known. Otherwise, in explicit header mode, the
initial size of the receive buffer is set to the packet length in the received header. The variable FifoRxCurrentAddr indicates
the location of the last packet received in the FIFO so that the last packet received can be easily read by pointing the
FifoAddrPtr to this register.
It is important to notice that all the received data will be written to the FIFO data buffer even if the CRC is invalid. This
allows for post-processing of received data for debug purposes for instance. It is also imporant to note that when receiving,
if the packet size exceeds the buffer memory allocated for the Rx it will overwrite the transmit portion of the data buffer.
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4.1.3. Operation of the LoRaTM Modem
4.1.3.1. Operating Mode Control
The operating modes of the LoRaTM modem are accessed by enabling LoRaTM mode (setting the LongRangeMode bit of
RegOpMode). Depending upon the operating mode selected the range of functionality and register access is given by the
following table:
Table 61 LoRaTM Operating Mode Functionality
Operating Mode
SLEEP
STAND-BY
Description
Low-power mode. In this mode only SPI and configuration registers are accessible. Lora FIFO is not
accessible.
Note that this is the only mode permissible to switch between FSK/OOK mode and LoRa mode.
both Crystal oscillator and Lora baseband blocks are turned on.RF part and PLLs are disabled
FSTX
This is a frequency synthesis mode for transmission. The PLL selected for transmission is locked and active
at the transmit frequency. The RF part is off.
FSRX
This is a frequency synthesis mode for reception. The PLL selected for reception is locked and active at the
receive frequency. The RF part is off.
TX
RXCONTINUOUS
RXSINGLE
CAD
When activated the RFM95/96/97/98(W) powers all remaining blocks required for transmit, ramps the PA,
transmits the packet and returns to Stand-by mode.
When activated the RFM95/96/97/98(W) powers all remaining blocks required for reception,
processing all received data until a new user request is made to change operating mode.
When activated the RFM95/96/97/98(W) powers all remaining blocks required for reception, remains in
this state until a valid packet has been received and then returns to Stand-by mode.
When in CAD mode, the device will check a given channel to detect LoRa preamble signal
It is possible to access any mode from any other mode by changing the value in the RegOpMode register.
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4.1.4. Frequency Settings
Recalling that the frequency step is given by:
FXOSC
F STE P = --------------19
2
In order to set LO frequency values following registers are available.
Frf is a 24-bit register which defines carrier frequency. The carrier frequency relates to the register contents by following
formula:
F RF = FSTEP × Frf(23,0)
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4.1.5. LoRaTM Modem State Machine Sequences
The sequence for transmission and reception of data to and from the LoRaTM modem, together with flow charts of typical
sequences of operation, are detailed below.
Data Transmission Sequence
In transmit mode power consumption is optimized by enabling RF, PLL and PA blocks only when packet data needs to be
transmitted. Figure 8 shows a typical LoRaTM transmit sequence.
Figure 8. LoRaTM modulation transmission sequence.
Static configuration registers can only be accessed in Sleep mode, Stand-by mode or FSTX mode.
The LoRaTM FIFO can only be filled in Stand-by mode.
Data transmission is initiated by sending TX mode request.
Upon completion the TxDone interrupt is issued and the radio returns to Stand-by mode.
Following transmission the radio can be manually placed in Sleep mode or the FIFO refilled for a subsequent Tx
operation.
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LoRaTM Transmit Data FIFO Filling
In order to write packet data into FIFO user should:
1 Set FifoPtrAddr to FifoTxPtrBase.
2 Write PayloadLength bytes to the FIFO (RegFifo)
Data Reception Sequence
Figure 9 shows typical LoRaTM receive sequences for both single and continuous receiver modes of operation.
Figure 9. LoRaTM receive sequence.
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The LORA receive modem can work in two distinct mode
1.
2.
Single receive mode
Continuous receive mode
Those two modes correspond to different use cases and it is important to understand the subtle differences between them.
Single Reception Operating Mode
In this mode, the modem searches for a preamble during a given time window. If a preamble hasn’t been found at the end
of the time window, the chip generates the RxTimeout interrupt and goes back to stand-by mode . The length of the window
(in symbols) is defined by the RegSymbTimeout register and should be in the range of 4 (minimum time for the modem to
acquire lock on a preamble) up to 1023 symbols. (The default value being 5). If no preamble is detected during this window
the RxTimeout interrupt is generated and the radio goes back to stand-by mode.
At the end of the payload, the RxDone interrupt is generated together with the interrupt PayloadCrcError if the payload
CRC is not valid. However, even when the CRC is not valid, the data are written in the FIFO data buffer for post processing.
Following the RxDone interrupt the radio goes to stand-by mode.
The modem will also automatically return in stand-by mode when the interrupts RxDone or RxTimeout are generated.
Therefore, this mode should only be used when the time window of arrival of the packet is known . In other cases, the RX
continuous mode should be used.
In Rx single mode low-power is achieved by turning off PLL and RF blocks as soon as a packet has been received. The
flow is as follows:
1 Set FifoPtrAddr to FifoRxPtrBase.
2 Static configuration register device can be written in either Sleep mode, Stand-by mode or FSRX mode.
3 A single packet receive operation is initiated by selecting the operating mode RXSINGLE.
4 The receiver will then await the reception of a valid preamble. Once received, the gain of the receive chain is set.
Following the ensuing reception of a valid header, indicated by the ValidHeader interrupt in explicit mode. The packet
reception process commences. Once the reception process is complete the RxDone interrupt is set. The radio then returns
automatically to Stand-by mode to reduce power consumption.
5 The receiver status register PayloadCrcError should be checked for packet payload integrity.
6 If a valid packet payload has been received then the FIFO should be read (See Payload Data Extraction below). Should
a subsequent single packet reception need to be triggered, then the RXSINGLE operating mode must be re-selected to
launch the receive process again - taking care to reset the SPI pointer (FifoPtrAddr) to the base location in memory
(FifoRxPtrBase).
Continuous Reception Operating Mode
In continuous receive mode the modem scans the channel continuously for a preamble. Each time a preamble is detected
the modem detects and tracks it until the packet is received and then carries on waiting for the next preamble.
If the preamble length exceeds the anticipated value set by the registers RegPreambleMsb and RegPreambleLsb (measured in
symbol unit), the preamble will be dropped and the search for a preamble restarted. However, this scenario will not be
flagged by an interrupt. In continous RX mode, opposite to the single RX mode, when a timeout interrupt is generated, the
device will not go in standby mode. In this case, the user must simply clear the interrupt while the device carry on waiting
for a valid preamble.
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It is also important to note that the demodulated bytes are written in the data buffer memory in the order received. Meaning,
the first byte of a new packet is written just after the last byte of the preceding packet. The RX modem address pointer is
never reseted as long as this mode is enabled. It is therefore necessary for the controller to handle the address pointer to
make sure the FIFO data buffer is never full.
In continuous mode the received packet processing sequence is given below.
1 Whilst in Sleep or Stand-by mode select RXCONT mode.
2 Upon reception of a valid header CRC the RxDone interrupt is set. The radio remains in RXCONT mode waiting for the
next RX LoRaTM packet.
3 The PayloadCrcError flag should be checked for packet integrity.
4 If packet has been correctly received the FIFO data buffer can be read (see below).
5 The reception process (steps 2 - 4) can be repeated or receiver operating mode exited as desired.
In continuous mode status information are available only for the last packet received, i.e. the corresponding registers
should be read before the next RxDone arrives.
Payload Data Extraction from FIFO
In order to retrieve received data from FIFO the user must ensure that ValidHeader, PayloadCrcError, RxDone and
RxTimeout interrupts in the status register RegIrqFlags are not asserted to ensure that packet reception has terminated
successfully (i.e. no flags should be set).
In case of errors the steps below should be skipped and the packet discarded. In order to retrieve valid received data from
the FIFO the user must:
FifoNbRxBytes Indicates the number of bytes that have been received thus far.
RegRxDataAddr Is a dynamic pointer that indicates precisely where the Lora modem received data has been written up
to.
Set FifoPtrAddr to FifoRxCurrentAddr. This sets the FIFO pointer to the the location of the last packet received in the
FIFO. The payload can then be extracted by reading the RegFifo address RegNbRxBytes times. Alternatively, it is
possible to manually point to the location of the last packet received from the start of the current packet by setting
FifoPtrAddr to RegRxDataAddr - FifoNbRxBytes. In the same way, packet bytes can then be extracted from FIFO by
reading the RegFifo address RegNbRxBytes times.
Packet Filtering based on Preamble Start
The LoRa modem does automatically filter received packets based upon any addressing. However the
RFM95/96/97/98(W) permit software filtering of the received packets based on the contents of the first few bytes of
payload. A brief example is given below for a 4 byte address, however, the address length can be selected by the
designer.
The objective of the packet filtering process is to determine the presence, or otherwise, of a valid packet designed for the
receiver. If the packet is not for the receiver then the radio returns to sleep mode in order to improve battery life.
The software packet filtering process follows the steps below:
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Each time the RxDone interrupt is received, latch the RegFifoRxByteAddr[7:0] register content in a variable , this
variable will be called start_address. The RegFifoRxByteAddr[7:0] register of the RFM95/96/97/98(W) gives in real
time the address of the last byte written in the data buffer + 1 (or the address at which the next byte will be written) by
the receive LoRa modem . So by doing this , we make sure that the variable start_address always contains the start
address of the next packet.
Upon reception of the interrupt ValidHeader, start polling the RegFifoRxByteAddr[7:0] register until it begins to
increment. The speed at which this register will increment depends on the Spreading factor, the error correction code
and the modulation bandwidth. (Note that this interrupt is still generated in implicit mode).
As soon as RegFifoRxByteAddr[7:0] >= start address + 4, the first 4 bytes (address) are stored in the FIFO data buffer.
These can be read and tested to see if the packet is destined for the radio and either remaining in Rx mode to receive
the packet or returning to sleep mode if not.
Receiver Timeout Operation
In either single or continuous LoRaTM reception modes, a receiver timeout functionality is available that permits the receiver
to listen for a pre-determined period of time before generating an interrupt signal to indicate that no valid packets have
been received. The timer is absolute and commences as soon as the radio is placed in either single or continuous receive
mode. The interrupt itself, RxTimeout, can be found in the interrupt register RegIrqFlags. In Rx Single mode, the device will
return in Stanby mode as soon as the interrupt occurs and the interrupt needs to be cleared before to return in Rx Single
mode. In Rx Continuous mode, the interrupt will interrupt will simply be raised but the device will stay in Rx Continous
mode. It is therefore the responsability on the controller to clear the interrupt while still in Rx Continuous mode. The
programmed timeout value is expressed as a multiple of the symbol period and is given by:
TimeOut = LoraRxTimeout · Ts
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Channel Activity Detection
The use of a spread spectrum modulation technique presents challenges in determining whether the channel is already in
use by a signal that may be below the noise floor of the receiver. The use of the RSSI in this situation would clearly be
impracticable. To this end the channel activity detector is used to detect the presence of other LoRaTM signals. Figure 10
shows the channel activity detection (CAD) process:
Figure 10. LoRaTM CAD flow
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Principle of Operation
The channel activity detection mode is designed to detect a LoRa preamble on the radio channel with the best possible
power efficiency. Once in CAD mode, the RFM95/96/97/98(W) will perform a very quick scan of the band to detect a LoRa
packet preamble.
During a CAD the following operations take place:
The PLL locks
The radio receiver captures LoRa preamble symbol of data from the channel. The radio current consumption during that
phase corresponds to the specified Rx mode current
The radio receiver and the PLL turn off, and the modem digital processing starts.
The modem searches for a correlation between the radio captured samples and the ideal preamble waveform. This
correlation process takes a little bit less than a symbol period to perform. The radio current consumption during that
phase is greatly reduced.
Once the calculation is finished the modem generates the CadDone interrupt. If the correlation was successful,
CadDetected is generated simultaneously.
The chip goes back to stand-by mode.
If a preamble was detected, clear the interrupt, then initiate the reception by putting the radio in RX single mode or RX
continuous mode.
The time taken for the channel activity detection is dependent upon the LoRa modulation settings used. For a given
configuration the typical CAD detection time is shown in the graph below, expressed as a multiple of the LoRa symbol
period. Of this period the radio is in receiver mode for (2SF + 32) / BW seconds. For the remainder of the CAD cycle the
radio is in a reduced consumption state.
Figure 11. Channel activity detection (CAD) time as a function of spreading factor
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To illustrate this process and the respective consumption in each mode, the CAD process follows the sequence of events
outlined below:
Figure 12. Consumption Profile of the LoRa CAD Process
The receiver is then in full receiver mode for just over half of the activity detection, followed by a reduced consumption
processing phase where the consumption varies with the LoRa bandwidth as shown in the table below.
Table 62 LoRa CAD Consumption Figures
Bandwidth
(kHz)
7.8
10.4
15.6
20.8
31.2
41.7
62.5
125
250
500
Full Rx, IDDR_L
(mA)
Processing, IDDC_L
(mA)
To be
confirmed
10.8
11.6
13
5.6
6.5
8
4.1.5.1. Digital IO Pin Mapping
Six of RFM95/96/97/98(W)’s general purpose IO pins are available used in LoRaTM mode. Their mapping is shown
below and depends upon the configuration of registers RegDioMapping1 and RegDioMapping2.
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Table 63 DIO Mapping LoRaTM Mode
Operating
Mode
DIOx
Mapping
ALL
00
01
10
11
DIO5
DIO4
DIO3
DIO2
ModeReady
ClkOut
DIO1
DIO0
CadDetected
CadDone
PllLock
ValidHeader
FhssChangeChannel
RxTimeout
RxDone
FhssChangeChannel
FhssChangeChannel
ClkOut
PllLock
TxDone
PayloadCrcError
FhssChangeChannel
CadDetected
CadDone
-
-
-
-
-
-
4.2. FSK/OOK Modem
4.2.1. Bit Rate Setting
The bitrate setting is referenced to the crystal oscillator and provides a precise means of setting the bit rate (or equivalently
chip) rate of the radio. In continuous transmit mode (Section 3.2.2) the data stream to be transmitted can be input directly
to the modulator via pin 9 (DIO2/DATA) in an asynchronous manner, unless Gaussian filtering is used, in which case the
DCLK signal on pin 10 (DIO1/DCLK) is used to synchronize the data stream. See section 4.2.2.3 for details on the
Gaussian filter.
In Packet mode or in Continuous mode with Gaussian filtering enabled, the Bit Rate (BR) is controlled by bits Bitrate in
RegBitrateMsb and RegBitrateLsb
FXOSC
Bi tR ate = ------------------------------------------------------------------------itrateFrac
Bi tR ate(15,0) + ------------------------------16
Note:
BitrateFrac bits have no effect (i.e may be considered equal to 0) in OOK modulation mode.
The quantity BitrateFrac is hence designed to allow very high precision (max. 250 ppm programing resolution) for any
bitrate in the programmable range. Table 64 below shows a range of standard bitrates and the accuracy to within which
they may be reached.
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Table 64 Bit Rate Examples
Type
Classical modem baud rates
(multiples of 1.2 kbps)
Classical modem baud rates
(multiples of 0.9 kbps)
Round bit rates
(multiples of 12.5, 25 and
50 kbps)
Watch Xtal frequency
BitRate
(15:8)
BitRate
(7:0)
(G)FSK
(G)MSK
OOK
Actual BR
(b/s)
0x68
0x2B
1.2 kbps
1.2 kbps
1200.015
0x34
0x15
2.4 kbps
2.4 kbps
2400.060
0x1A
0x0B
4.8 kbps
4.8 kbps
4799.760
0x0D
0x05
9.6 kbps
9.6 kbps
9600.960
0x06
0x83
19.2 kbps
19.2 kbps
19196.16
0x03
0x41
38.4 kbps
38415.36
0x01
0xA1
76.8 kbps
76738.60
0x00
0xD0
153.6 kbps
153846.1
0x02
0x2C
57.6 kbps
57553.95
0x01
0x16
115.2 kbps
115107.9
0x0A
0x00
12.5 kbps
12.5 kbps
12500.00
0x05
0x00
25 kbps
25 kbps
25000.00
0x80
0x00
50 kbps
50000.00
0x01
0x40
100 kbps
100000.0
0x00
0xD5
150 kbps
150234.7
0x00
0xA0
200 kbps
200000.0
0x00
0x80
250 kbps
250000.0
0x00
0x6B
300 kbps
299065.4
0x03
0xD1
32.768 kbps
32.768 kbps
32753.32
4.2.2. FSK/OOK Transmission
4.2.2.1. FSK Modulation
FSK modulation is performed inside the PLL bandwidth, by changing the fractional divider ratio in the feedback loop of the
PLL. The high resolution of the sigma-delta modulator, allows for very narrow frequency deviation. The frequency deviation
FDEV is given by:
F DEV = F STEP × Fdev(13,0)
To ensure correct modulation, the following limit applies:
R
F DE V + ------- ≤ (250 )kHz
2
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No constraint applies to the modulation index of the transmitter, but the frequency deviation must be set between
600 Hz and 200 kHz.
4.2.2.2. OOK Modulation
OOK modulation is applied by switching on and off the power amplifier. Digital control and ramping are available to improve
the transient power response of the OOK transmitter.
4.2.2.3. Modulation Shaping
Modulation shaping can be applied in both OOK and FSK modulation modes, to improve the narrowband response of the
transmitter. Both shaping features are controlled with PaRamp bits in RegPaRamp.
In FSK mode, a Gaussian filter with BT = 0.5 or 1 is used to filter the modulation stream, at the input of the sigma-delta
modulator. If the Gaussian filter is enabled when the RFM95/96/97/98(W) is in Continuous mode, DCLK signal on pin
10 (DIO1/DCLK) will trigger an interrupt on the uC each time a new bit has to be transmitted. Please refer to section
5.4.2 for details.
When OOK modulation is used, the PA bias voltages are ramped up and down smoothly when the PA is turned on and
off, to reduce spectral splatter.
Note The transmitter must be restarted if the ModulationShaping setting is changed, in order to recalibrate the built-in
filter.
4.2.3. FSK/OOK Reception
4.2.3.1. FSK Demodulator
The FSK demodulator of the RFM95/96/97/98(W) is designed to demodulate FSK, GFSK, MSK and GMSK modulated
signals. It is most efficient when the modulation index of the signal is greater than 0.5 and below 10:
2 × FDEV
0.5 ≤ β = ---------------------- ≤ 10
BR
The output of the FSK demodulator can be fed to the Bit Synchronizer to provide the companion processor with a
synchronous data stream in Continuous mode.
4.2.3.2. OOK Demodulator
The OOK demodulator performs a comparison of the RSSI output and a threshold value. Three different threshold modes
are available, configured through bits OokThreshType in RegOokPeak.
The recommended mode of operation is the “Peak” threshold mode, illustrated in Figure 13:
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RSSI
[dBm]
‘’Peak -6dB’’ Threshold
‘’Floor’’ threshold defined by
OokFixedThresh
Noise floor of
receiver
Time
Zoom
Decay in dB as defined in
OokPeakThreshStep
Fixed 6dB difference
Period as defined in
OokPeakThreshDec
Figure 13. OOK Peak Demodulator Description
In peak threshold mode the comparison threshold level is the peak value of the RSSI, reduced by 6dB. In the absence of
an input signal, or during the reception of a logical ‘0’, the acquired peak value is decremented by one OokPeakThreshStep
every OokPeakThreshDec period.
When the RSSI output is null for a long time (for instance after a long string of “0” received, or if no transmitter is present),
the peak threshold level will continue falling until it reaches the “Floor Threshold”, programmed in OokFixedThresh.
The default settings of the OOK demodulator lead to the performance stated in the electrical specification. However, in
applications in which sudden signal drops are awaited during a reception, the three parameters should be optimized
accordingly.
Optimizing the Floor Threshold
OokFixedThresh determines the sensitivity of the OOK receiver, as it sets the comparison threshold for weak input signals
(i.e. those close to the noise floor). Significant sensitivity improvements can be generated if configured correctly.
Note that the noise floor of the receiver at the demodulator input depends on:
The noise figure of the receiver.
The gain of the receive chain from antenna to base band.
The matching - including SAW filter if any.
The bandwidth of the channel filters.
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It is therefore important to note that the setting of OokFixedThresh will be application dependant. The following procedure
is recommended to optimize OokFixedThresh.
Set RFM96/7/8 in OOK Rx mode
Adjust Bit Rate, Channel filter BW
Default OokFixedThresh setting
No input signal
Continuous Mode
Monitor DIO2/DATA pin
Increment
OokFixedThresh
Glitch activity
on DATA ?
Optimization complete
Figure 14. Floor Threshold Optimization
The new floor threshold value found during this test should be used for OOK reception with those receiver settings.
Optimizing OOK Demodulator for Fast Fading Signals
A sudden drop in signal strength can cause the bit error rate to increase. For applications where the expected signal drop
can be estimated, the following OOK demodulator parameters OokPeakThreshStep and OokPeakThreshDec can be
optimized as described below for a given number of threshold decrements per bit. Refer to RegOokPeak to access those
settings.
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Alternative OOK Demodulator Threshold Modes
In addition to the Peak OOK threshold mode, the user can alternatively select two other types of threshold detectors:
Fixed Threshold: The value is selected through OokFixedThresh
Average Threshold: Data supplied by the RSSI block is averaged, and this operation mode should only be used with
DC-free encoded data.
4.2.3.3. Bit Synchronizer
The bit synchronizer provides a clean and synchronized digital output based upon timing recovery information gleaned
from the received data edge transitions. Its output is made available on pin DIO1/DCLK in Continuous mode and can be
disabled through register settings. However, for optimum receiver performance, especially in Continuous receive mode, its
use is strongly advised.
The Bit Synchronizer is automatically activated in Packet mode. Its bit rate is controlled by BitRateMsb and BitRateLsb in
RegBitrate.
Raw demodulator
output
(FSK or OOK)
DATA
BitSync Output To
pin DATA and
DCLK in continuous
mode
DCLK
Figure 15. Bit Synchronizer Description
To ensure correct operation of the Bit Synchronizer, the following conditions have to be satisfied:
A preamble (0x55 or 0xAA) of at least 12 bits is required for synchronization, the longer the synchronization phase is the
better the ensuing packet detection rate will be.
The subsequent payload bit stream must have at least one edge transition (either rising or falling) every 16 bits during
data transmission.
The absolute error between transmitted and received bit rate must not exceed 6.5%.
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4.2.3.4. Frequency Error Indicator
This frequency error indicator measures the frequency error between the programmed RF centre frequency and the carrier
frequency of the modulated input signal to the receiver. When the FEI is performed, the frequency error is measured and
the signed result is loaded in FeiValue in RegFei, in 2’s complement format. The time required for an FEI evaluation is 4 bit
periods.
To ensure correct operation of the FEI:
The measurement must be launched during the reception of preamble.
The sum of the frequency offset and the 20 dB signal bandwidth must be lower than the base band filter bandwidth. i.e.
The whole modulated spectrum must be received.
The 20 dB bandwidth of the signal can be evaluated as follows (double-side bandwidth):
BW 20 dB = 2 × ⎛ F DEV + -------⎞
⎝
2⎠
The frequency error, in Hz, can be calculated with the following formula:
FEI = F STEP × FeiValue
RFM96/7/8 in Rx mode
Preamble-modulated input signal
Signal level > Sensitivity
Set FeiStart
=1
FeiDone
=1
No
Yes
Read
FeiValue
Figure 16. FEI Process
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4.2.3.5. AFC
The AFC is based on the FEI measurement, therefore the same input signal and receiver setting conditions apply. When
the AFC procedure is performed the AfcValue is directly subtracted from the register that defines the frequency of
operation of the chip, FRF. The AFC is executed each time the receiver is enabled, if AfcAutoOn = 1.
When the AFC is enabled (AfcAutoOn = 1), the user has the option to:
Clear the former AFC correction value, if AfcAutoClearOn = 1. Allowing the next frequency correction to be performed
from the initial centre frequency.
Start the AFC evaluation from the previously corrected frequency. This may be useful in systems in which the centre
frequency experiences cumulative drift - such as the ageing of a crystal reference.
The RFM95/96/97/98(W) offers an alternate receiver bandwidth setting during the AFC phase allowing the
accommodation of larger frequency errors. The setting RegAfcBw sets the receive bandwidth during the AFC process. In
a typical receiver application the, once the AFC is performed, the radio will revert to the receiver communication or
channel bandwidth (RegRxBw) for the ensuing communication phase.
Note that the FEI measurement is valid only during the reception of preamble. The provision of the PreambleDetect flag
can hence be used to detect this condition and allow a reliable AFC or FEI operation to be triggered. This process can be
performed automatically by using the appropriate options in StartDemodOnPreamble found in the RegRxConfig register.
A detailed description of the receiver setup to enable the AFC is provided in section 4.2.6.
4.2.3.6. Preamble Detector
The Preamble Detector indicates the reception of a carrier modulated with a 0101...sequence. It is insensitive to the
frequency offset, as long as the receiver bandwidth is large enough. The size of detection can be programmed from 1 to 3
bytes with PreambleDetectorSize in RegPreambleDetect as defined in the next table.
Table 65 Preamble Detector Settings
PreambleDetectorSize
# of Bytes
00
1
01
2 (recommended)
10
3
11
reserved
For normal operation, PreambleDetectTol should be set to be set to 10 (0x0A), with a qualifying preamble size of 2 bytes.
The PreambleDetect interrupt (either in RegIrqFlags1 or mapped to a specific DIO) then goes high every time a valid
preamble is detected, assuming PreambleDetectorOn=1.
The preamble detector can also be used as a gate to ensure that AFC and AGC are performed on valid preamble. See
section 4.2.6. for details.
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4.2.3.7. Image Rejection Mixer
The RFM95/96/97/98(W) employs an image rejection mixer (IRM) which, uncalibrated, 35 dB image rejection. A low phase
noise
PLL is used to perform calibration of the receiver chain. This increases the typical image rejection to 48 dB.
4.2.3.8. Image and RSSI Calibration
An automatic calibration process is used to calibrate the phase and gain of both I and Q receive paths. This calibration
allows enhanced image frequency rejection and improves the RSSI precision. This Calibration process is launched under
the following circumstances:
Automatically at Power On Reset or after a Manual Reset of the chip (refer to section 7.2). For applications where the
temperature remains stable, or if the Image Rejection is not a major concern, this single calibration will suffice.
Automatically when a pre-defined temperature change is observed.
Upon User request, by setting bit ImageCalStart in RegImageCal, when the device is in Standby mode. Note that in
LoRaTM mode the calibration command is inaccessible. To perform the calibration, the radio must be returned
temporarily to FSK/OOK mode for the calibration process.
A selectable temperature change, set with TempThreshold (5, 10, 15 or 20°C), is detected and reported in TempChange, if
the temperature monitoring is turned On with TempMonitorOff=0.
This interrupt flag can be used by the application to launch a new image calibration at a convenient time if
AutoImageCalOn=0, or immediately when this temperature variation is detected, if AutoImageCalOn=1.
The calibration process takes approximately 10ms.
4.2.3.9. Timeout Function
The RFM95/96/97/98(W) includes a Timeout function, which allows it to automatically shut-down the receiver after a
receive sequence and therefore save energy.
Timeout interrupt is generated TimeoutRxRssi x 16 x Tbit after switching to Rx mode if the Rssi flag does not raise
within this time frame (RssiValue > RssiThreshold)
Timeout interrupt is generated TimeoutRxPreamble x 16 x Tbit after switching to Rx mode if the PreambleDetect flag
does not raise within this time frame
Timeout interrupt is generated TimeoutSignalSync x 16 x Tbit after switching to Rx mode if the SyncAddress flag does
not raise within this time frame
This timeout interrupt can be used to warn the companion processor to shut down the receiver and return to a lower power
mode. To become active, these timeouts must also be enabled by setting the correct RxTrigger parameters in
RegRxConfig:
Table 66 RxTrigger Settings to Enable Timeout Interrupts
Receiver
Triggering Event
None
Rssi Interrupt
PreambleDetect
Rssi Interrupt & PreambleDetect
RxTrigger
(2:0)
000
001
110
111
Timeout on
Rssi
Off
Active
Off
Active
Timeout on
Preamble
Off
Off
Active
Active
Timeout on
SyncAddress
Active
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4.2.4. Operating Modes in FSK/OOK Mode
The RFM95/96/97/98(W) has several working modes, manually programmed in RegOpMode. Fully automated mode
selection, packet transmission and reception is also possible using the Top Level Sequencer described in Section 4.2.8.
Table 67 Basic Transceiver Modes
Mode
Selected mode
Symbol
Enabled blocks
000
Sleep mode
Sleep
None
001
Standby mode
Stdby
Top regulator and crystal oscillator
010
Frequency synthesiser to Tx
frequency
FSTx
Frequency synthesizer at Tx frequency (Frf)
011
Transmit mode
Tx
Frequency synthesizer and transmitter
100
Frequency synthesiser to Rx
frequency
FSRx
Frequency synthesizer at frequency for reception (Frf-IF)
101
Receive mode
Rx
Frequency synthesizer and receiver
When switching from a mode to another the sub-blocks are woken up according to a pre-defined optimized sequence.
4.2.5. Startup Times
The startup time of the transmitter or the receiver is dependant upon which mode the transceiver was in at the beginning.
For a complete description, Figure 17 below shows a complete startup process, from the lower power mode “Sleep”.
Current
Drain
IDDR (Rx) or IDDT (Tx)
IDDFS
IDDST
IDDSL
0
Timeline
TS_OSC
TS_OSC
+TS_FS
FSTx
Sleep
mode
TS_OSC
+TS_FS
+TS_TR
TS_OSC
+TS_FS
+TS_RE
Transmit
Stdby
mode
FSRx
Receive
Figure 17. Startup Process
TS_OSC is the startup time of the crystal oscillator which depends on the electrical characteristics of the crystal. TS_FS is
the startup time of the PLL including systematic calibration of the VCO.
Typical values of TS_OSC and TS_FS are given in Section 2.3.
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4.2.5.1. Transmitter Startup Time
The transmitter startup time, TS_TR, is calculated as follows in FSK mode:
1
TS _ TR = 5μs +1.25 × PaRamp + ×Tbit
2
,
where PaRamp is the ramp-up time programmed in RegPaRamp and Tbit is the bit time.
In OOK mode, this equation can be simplified to the following:
1
TS _ TR = 5μs + ×Tbit
2
4.2.5.2. Receiver Startup Time
The receiver startup time, TS_RE, only depends upon the receiver bandwidth effective at the time of startup. When AFC is
enabled (AfcAutoOn=1), AfcBw should be used instead of RxBw to extract the receiver startup time:
Table 68 Receiver Startup Time Summary
RxBw if AfcAutoOn=0
RxBwAfc if AfcAutoOn=1
2.6 kHz
3.1 kHz
3.9 kHz
5.2 kHz
6.3 kHz
7.8 kHz
10.4 kHz
12.5 kHz
15.6 kHz
20.8 kHz
25.0 kHz
31.3 kHz
41.7 kHz
50.0 kHz
62.5 kHz
83.3 kHz
100.0 kHz
125.0 kHz
166.7 kHz
200.0 kHz
250.0 kHz
TS_RE
(+/-5%)
2.33 ms
1.94 ms
1.56 ms
1.18 ms
984 us
791 us
601 us
504 us
407 us
313 us
264 us
215 us
169 us
144 us
119 us
97 us
84 us
71 us
85 us
74 us
63 us
TS_RE or later after setting the device in Receive mode, any incoming packet will be detected and demodulated by the
transceiver.
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4.2.5.3. Time to RSSI Evaluation
The first RSSI sample will be available TS_RSSI after the receiver is ready, in other words TS_RE + TS_RSSI after the
receiver was requested to turn on.
Timeline
0
TS_RE
FSRx
TS_RE
+TS_RSSI
Rx
Rssi IRQ
Rssi sample
ready
Figure 18. Time to Rssi Sample
TS_RSSI depends on the receiver bandwidth, as well as the RssiSmoothing option that was selected. The formula used to
calculate TS_RSSI is provided in section 2.5.4.
4.2.5.4. Tx to Rx Turnaround Time
Timeline
0
TS_HOP
+TS_RE
Tx Mode
1. set new Frf (*)
2. set Rx mode
Rx Mode
(*) Optional
Figure 19. Tx to Rx Turnaround
Note
The SPI instruction times are omitted, as they can generally be very small as compared to other timings (up to
10MHz SPI clock).
4.2.5.5. Rx to Tx
Timeline
0
TS_HOP
+TS_TR
Rx Mode
1. set new Frf (*)
2. set Tx mode
Tx Mode
(*) Optional
Figure 20. Rx to Tx Turnaround
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4.2.5.6. Receiver Hopping, Rx to Rx
Two methods are possible:
First method
Timeline
0
TS_HOP
+TS_RE
Rx Mode,
Channel A
Rx Mode,
Channel B
1. set new Frf
2. set RestartRxWithPllLock
Second method
Timeline
0
~TS_HOP
Rx Mode,
Channel A
1. set FastHopOn=1
2. set new Frf (*)
3. wait for TS_HOP
Rx Mode,
Channel B
(*) RegFrfLsb must be written to
trigger a frequency change
Figure 21. Receiver Hopping
The second method is quicker, and should be used if a very quick RF sniffing mechanism is to be implemented.
4.2.5.7. Tx to Tx
Timeline
~PaRamp
+TS_HOP
0
Tx Mode,
Channel A
1. set new Frf (*)
2. set FSTx mode
FSTx
~PaRamp
+TS_HOP
+TS_TR
Set Tx mode
Tx Mode,
Channel B
Figure 22. Transmitter Hopping
4.2.6. Receiver Startup Options
The RFM95/96/97/98(W) receiver can automatically control the gain of the receive chain (AGC) and adjust the
receiver LO
frequency (AFC). Those processes are carried out on a packet-by-packet basis. They occur:
When the receiver is turned On.
When the Receiver is restarted upon user request, through the use of trigger bits RestartRxWithoutPllLock or
RestartRxWithPllLock, in RegRxConfig.
When the receiver is automatically restarted after the reception of a valid packet, or after a packet collision.
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Automatic restart capabilities are detailed in Section 4.2.7.
The receiver startup options available in RFM95/96/97/98(W) are described in Table 69.
Table 69 Receiver Startup Options
AgcAutoOn
AfcAutoOn
None
AGC
AGC & AFC
AGC
AGC & AFC
AGC
0
1
1
1
1
1
0
0
1
0
1
0
RxTrigger
(2:0)
000
001
001
110
110
111
AGC & AFC
1
1
111
Triggering Event Realized Function
None
Rssi Interrupt
PreambleDetect
Rssi Interrupt
&
PreambleDetect
When AgcAutoOn=0, the LNA gain is manually selected by choosing LnaGain bits in RegLna.
4.2.7. Receiver Restart Methods
The options for restart of the receiver are covered below. This is typically of use to prepare for the reception of a new signal
whose strength or carrier frequency is different from the preceding packet to allow the AGC or AFC to be re-evaluated.
4.2.7.1. Restart Upon User Request
In Receive mode the user can request a receiver restart - this can be useful in conjunction with the use of a Timeout
interrupt following a period of inactivity in the channel of interest. Two options are available:
No change in the Local Oscillator upon restart: the AFC is disabled, and the Frf register has not been changed through
SPI before the restart instruction: set bit RestartRxWithoutPllLock in RegRxConfig to 1.
Local Oscillator change upon restart: if AFC is enabled (AfcAutoOn=1), and/or the Frf register had been changed during
the last Rx period: set bit RestartRxWithPllLock in RegRxConfig to 1.
Note
ModeReady must be at logic level 1 for a new RestartRx command to be taken into account.
4.2.7.2. Automatic Restart after valid Packet Reception
The bits AutoRestartRxMode in RegSyncConfig control the automatic restart feature of the RFM95/96/97/98(W) receiver,
when a valid packet has been received:
If AutoRestartRxMode = 00, the function is off, and the user should manually restart the receiver upon valid packet
reception (see section 4.2.7.1).
If AutoRestartRxMode = 01, after the user has emptied the FIFO following a PayloadReady interrupt, the receiver will
automatically restart itself after a delay of InterPacketRxDelay, allowing for the distant transmitter to ramp down, hence
avoiding a false RSSI detection on the ‘tail’ of the previous packet.
If AutoRestartRxMode = 10 should be used if the next reception is expected on a new frequency, i.e. Frf is changed
after the reception of the previous packet. An additional delay is systematically added, in order for the PLL to lock at a
new frequency.
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4.2.7.3. Automatic Restart when Packet Collision is Detected
In receive mode the RFM95/96/97/98(W) is able to detect packet collision and restart the receiver. Collisions are detected
by a sudden rise in received signal strength, detected by the RSSI. This functionality can be useful in network
configurations where many asynchronous slaves attempt periodic communication with a single a master node.
The collision detector is enabled by setting bit RestartRxOnCollision to 1.
The decision to restart the receiver is based on the detection of RSSI change. The sensitivity of the system can be adjusted
in 1 dB steps by using register RssiCollisionThreshold in RegRxConfig.
4.2.8. Top Level Sequencer
Depending on the application, it is desirable to be able to change the mode of the circuit according to a predefined
sequence without access to the serial interface. In order to define different sequences or scenarios, a user-programmable
state machine, called Top Level Sequencer (Sequencer in short), can automatically control the chip modes.
NOTE THAT THIS FUNCTIONALITY IS ONLY AVAILABLE IN FSK/OOK MODE.
The Sequencer is activated by setting the SequencerStart bit in RegSeqConfig1 to 1 in Sleep or Standby mode (called
initial mode).
It is also possible to force the Sequencer off by setting the Stop bit in RegSeqConfig1 to 1 at any time.
Note
SequencerStart and Stop bit must never be set at the same time.
4.2.8.1. Sequencer States
As shown in the table below, with the aid of a pair of interrupt timers (T1 and T2), the sequencer can take control of the chip
operation in all modes.
Table 70 Sequencer States
Sequencer
State
SequencerOff State
Description
The Sequencer is not activated. Sending a SequencerStart command will launch it.
When coming from LowPowerSelection state, the Sequencer will be Off, whilst the chip will
return to its initial mode (either Sleep or Standby mode).
Idle State
The chip is in low-power mode, either Standby or Sleep, as defined by IdleMode in
RegSeqConfig1. The Sequencer waits only for the T1 interrupt.
Transmit State
The transmitter in on.
Receive State
The receiver in on.
PacketReceived
The receiver is on and a packet has been received. It is stored in the FIFO.
LowPowerSelection
Selects low power state (SequencerOff or Idle State)
RxTimeout
Defines the action to be taken on a RxTimeout interrupt.
RxTimeout interrupt can be a TimeoutRxRssi, TimeoutRxPreamble or TimeoutSignalSync
interrupt.
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4.2.8.2. Sequencer Transitions
The transitions between sequencer states are listed in the forthcoming table.
Table 71 Sequencer Transition Options
Transition
Variable
IdleMode
Selects the chip mode during Idle state:
0: Standby mode
1: Sleep mode
FromStart
Controls the Sequencer transition when the SequencerStart bit is set to 1 in Sleep or Standby mode:
00: to LowPowerSelection
01: to Receive state
10: to Transmit state
11: to Transmit state on a FifoThreshold interrupt
LowPowerSelection
Selects Sequencer LowPower state after a to LowPowerSelection transition
0: SequencerOff state with chip on Initial mode
1: Idle state with chip on Standby or Sleep mode depending on IdleMode
Note: Initial mode is the chip LowPower mode at Sequencer start.
FromIdle
Controls the Sequencer transition from the Idle state on a T1 interrupt:
0: to Transmit state
1: to Receive state
FromTransmit
Controls the Sequencer transition from the Transmit state:
0: to LowPowerSelection on a PacketSent interrupt
1: to Receive state on a PacketSent interrupt
FromReceive
Controls the Sequencer transition from the Receive state:
000 and 111: unused
001: to PacketReceived state on a PayloadReady interrupt
010: to LowPowerSelection on a PayloadReady interrupt
011: to PacketReceived state on a CrcOk interrupt. If CRC is wrong (corrupted packet, with CRC on but
CrcAutoClearOn is off), the PayloadReady interrupt will drive the sequencer to RxTimeout state.
100: to SequencerOff state on a Rssi interrupt
101: to SequencerOff state on a SyncAddress interrupt
110: to SequencerOff state on a PreambleDetect interrupt
Irrespective of this setting, transition to LowPowerSelection on a T2 interrupt
FromRxTimeout
Controls the state-machine transition from the Receive state on a RxTimeout interrupt (and on
PayloadReady if FromReceive = 011):
00: to Receive state via ReceiveRestart
01: to Transmit state
10: to LowPowerSelection
11: to SequencerOff state
Note: RxTimeout interrupt is a TimeoutRxRssi, TimeoutRxPreamble or TimeoutSignalSync interrupt.
FromPacketReceived
Controls the state-machine transition from the PacketReceived state:
000: to SequencerOff state
001: to Transmit on a FifoEmpty interrupt
010: to LowPowerSelection
011: to Receive via FS mode, if frequency was changed
100: to Receive state (no frequency change)
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4.2.8.3. Timers
Two timers (Timer1 and Timer2) are also available in order to define periodic sequences. These timers are used to
generate interrupts, which can trigger transitions of the Sequencer.
T1 interrupt is generated (Timer1Resolution * Timer1Coefficient) after T2 interrupt or SequencerStart. command.
T2 interrupt is generated (Timer2Resolution * Timer2Coefficient) after T1 interrupt.
The timers’ mechanism is summarized on the following diagram.
Sequencer Start
T2
interrupt
Timer2
Timer1
T1
interrupt
Figure 23. Timer1 and Timer2 Mechanism
Note
The timer sequence is completed independently of the actual Sequencer state. Thus, both timers need to be on to
achieve periodic cycling.
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Table 72 Sequencer Timer Settings
Description
Variable
Timer1Resolution
Resolution of Timer1
00: disabled
01: 64 us
10: 4.1 ms
11: 262 ms
Timer2Resolution
Resolution of Timer2
00: disabled
01: 64 us
10: 4.1 ms
11: 262 ms
Timer1Coefficient
Multiplying coefficient for Timer1
Timer2Coefficient
Multiplying coefficient for Timer2
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4.2.8.4. Sequencer State Machine
The following graphs summarize every possible transition between each Sequencer state. The Sequencer states are
highlighted in grey. The transitions are represented by arrows. The condition activating them is described over the
transition arrow. For better readability, the start transitions are separated from the rest of the graph.
Transitory states are highlighted in light grey, and exit states are represented in red. It is also possible to force the
Sequencer off by setting the Stop bit in RegSeqConfig1 to 1 at any time.
Seq u en c er: Start tran s ition s
Sequencer Off
&
Initial mode = Sleep or Standby
On SequencerStart bit rising edge
Start
On FifoThreshold
if FromStart = 11
If FromStart = 00
If FromStart = 01 If FromStart = 10
LowPower
Selection
Receive
Transmit
Seq u en c er: State m a ch ine
Standby if IdleMode = 0
Sleep if IdleMode = 1
If LowPowerSelection = 1
LowPower
Selection
If LowPowerSelection = 0
( Mode Þ e Initial mode )
Sequencer Off
Idle
On T1 if FromIdle = 0
If FromPacketReceived = 000
On T1 if FromIdle = 1
If FromPacketReceived = 010
Packet
Received
On PayloadReady
if FromReceive = 010
On T2
On PayloadReady if FromReceive = 011
(CRC failed and CrcAutoClearOn=0)
On RxTimeout
If FromRxTimeout = 10
RxTimeout
If FromPacketReceived = 100
Via FS mode if FromPacketReceived = 011
On PayloadReady if FromReceive = 001
On CrcOk if FromReceive = 011
Receive
On Rssi if FromReceive = 100
On SyncAdress if FromReceive = 101
On Preamble if FromReceive = 110
On PacketSent
if FromTransmit = 1
Via ReceiveRestart
if FromRxTimeout = 00
If FromRxTimeout = 11
Transmit
On PacketSent
if FromTransmit = 0
Sequencer Off
If FromRxTimeout = 01
Figure 24. Sequencer State Machine
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4.2.9. Data Processing in FSK/OOK Mode
4.2.9.1. Block Diagram
Figure below illustrates the RFM95/96/97/98(W) data processing circuit. Its role is to interface the data to/from the
modulator/demodulator and the uC access points (SPI and DIO pins). It also controls all the configuration registers.
The circuit contains several control blocks which are described in the following paragraphs.
DIO0
DIO1
DIO2
DIO3
DIO4
DIO5
Tx/Rx
CONTROL
Data
Rx
SYNC
RECOG.
PACKET
HANDLER
FIFO
(+SR)
SPI
NSS
SCK
MOSI
MISO
Tx
Potential datapaths (data operation mode dependant)
Figure 25. RFM95/96/97/98(W) Data Processing Conceptual View
The RFM95/96/97/98(W) implements several data operation modes, each with their own data path through the data
processing section. Depending on the data operation mode selected, some control blocks are active whilst others remain
disabled.
4.2.9.2. Data Operation Modes
The RFM95/96/97/98(W) has two different data operation modes selectable by the user:
Continuous mode: each bit transmitted or received is accessed in real time at the DIO2/DATA pin. This mode may be
used if adequate external signal processing is available.
Packet mode (recommended): user only provides/retrieves payload bytes to/from the FIFO. The packet is automatically
built with preamble, Sync word, and optional CRC and DC-free encoding schemes The reverse operation is performed
in reception. The uC processing overhead is hence significantly reduced compared to Continuous mode. Depending on
the optional features activated (CRC, etc) the maximum payload length is limited to 255, 2047 bytes or unlimited.
Each of these data operation modes is fully described in the following sections.
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4.2.10. FIFO
Overview and Shift Register (SR)
In packet mode of operation, both data to be transmitted and that has been received are stored in a configurable FIFO
(First In First Out) device. It is accessed via the SPI interface and provides several interrupts for transfer management.
The FIFO is 1 byte wide hence it only performs byte (parallel) operations, whereas the demodulator functions serially. A
shift register is therefore employed to interface the two devices. In transmit mode it takes bytes from the FIFO and outputs
them serially (MSB first) at the programmed bit rate to the modulator. Similarly, in Rx the shift register gets bit by bit data
from the demodulator and writes them byte by byte to the FIFO. This is illustrated in figure below.
FIFO
byte1
byte0
8
Data Tx/Rx
SR (8bits)
1
MSB
LSB
Figure 26. FIFO and Shift Register (SR)
Note
When switching to Sleep mode, the FIFO can only be used once the ModeReady flag is set (quasi immediate from
all modes except from Tx)
The FIFO size is fixed to 64 bytes.
Interrupt Sources and Flags
FifoEmpty: FifoEmpty interrupt source is high when byte 0, i.e. whole FIFO, is empty. Otherwise it is low. Note that when
retrieving data from the FIFO, FifoEmpty is updated on NSS falling edge, i.e. when FifoEmpty is updated to low state
the currently started read operation must be completed. In other words, FifoEmpty state must be checked after each
read operation for a decision on the next one (FifoEmpty = 0: more byte(s) to read; FifoEmpty = 1: no more byte to
read).
FifoFull: FifoFull interrupt source is high when the last FIFO byte, i.e. the whole FIFO, is full. Otherwise it is low.
FifoOverrunFlag: FifoOverrunFlag is set when a new byte is written by the user (in Tx or Standby modes) or the SR (in
Rx mode) while the FIFO is already full. Data is lost and the flag should be cleared by writing a 1, note that the FIFO will
also be cleared.
PacketSent: PacketSent interrupt source goes high when the SR's last bit has been sent.
FifoLevel: Threshold can be programmed by FifoThreshold in RegFifoThresh. Its behavior is illustrated in figure below.
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FifoLevel
1
0
B
B+1
# of bytes in FIFO
Figure 27. FifoLevel IRQ Source Behavior
Notes - FifoLevel interrupt is updated only after a read or write operation on the FIFO. Thus the interrupt cannot be
dynamically updated by only changing the FifoThreshold parameter
- FifoLevel interrupt is valid as long as FifoFull does not occur. An empty FIFO will restore its normal operation
FIFO Clearing
Table below summarizes the status of the FIFO when switching between different modes
Table 73 Status of FIFO when Switching Between Different Modes of the Chip
From
Stdby
Sleep
Stdby/Sleep
Stdby/Sleep
Rx
Rx
Tx
To
Sleep
Stdby
Tx
Rx
Tx
Stdby/Sleep
Any
FIFO status
Not cleared
Not cleared
Not cleared
Cleared
Cleared
Not cleared
Cleared
Comments
To allow the user to write the FIFO in Stdby/Sleep before Tx
To allow the user to read FIFO in Stdby/Sleep mode after Rx
4.2.10.1. Sync Word Recognition
Overview
Sync word recognition (also called Pattern recognition) is activated by setting SyncOn in RegSyncConfig. The bit
synchronizer must also be activated in Continuous mode (automatically done in Packet mode).
The block behaves like a shift register; it continuously compares the incoming data with its internally programmed Sync
word and sets SyncAddressMatch when a match is detected. This is illustrated in Figure 28 below.
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Bit N-x =
(NRZ)
Sync_value[x]
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Bit N-1 =
Bit N =
Sync_value[1] Sync_value[0]
DCLK
SyncAddressMatch
Figure 28. Sync Word Recognition
During the comparison of the demodulated data, the first bit received is compared with bit 7 (MSB) of RegSyncValue1 and
the last bit received is compared with bit 0 (LSB) of the last byte whose address is determined by the length of the Sync
word.
When the programmed Sync word is detected the user can assume that this incoming packet is for the node and can be
processed accordingly.
SyncAddressMatch is cleared when leaving Rx or FIFO is emptied.
Configuration
Size: Sync word size can be set from 1 to 8 bytes (i.e. 8 to 64 bits) via SyncSize in RegSyncConfig. In Packet mode this
field is also used for Sync word generation in Tx mode.
Value: The Sync word value is configured in SyncValue(63:0). In Packet mode this field is also used for Sync word
generation in Tx mode.
Note
SyncValue choices containing 0x00 bytes are not allowed
Packet Handler
The packet handler is the block used in Packet mode. Its functionality is fully described in section 4.2.13.
Control
The control block configures and controls the full chip's behavior according to the settings programmed in the configuration
registers.
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4.2.11. Digital IO Pins Mapping
Six general purpose IO pins are available on the RFM95/96/97/98(W), and their configuration in Continuous or Packet
mode is controlled through RegDioMapping1 and RegDioMapping2.
Table 74 DIO Mapping, Continuous Mode
DIOx Mapping
DIO0
DIO1
DIO2
DIO3
DIO4
DIO5
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
Sleep
Standby
FSRx/Tx
-
Rx
Tx
SyncAddress
Rssi / PreambleDetect
RxReady
TxReady
TxReady
-
Dclk
Rssi / PreambleDetect
-
-
Data
Data
Data
Data
Timeout
Rssi / PreambleDetect
-
-
TempChange / LowBat
-
ClkOut if RC
ModeReady
ClkOut
-
-
ModeReady
TempChange / LowBat
TempChange / LowBat
PllLock
TimeOut
ModeReady
ClkOut
PllLock
Rssi / PreambleDetect
ModeReady
Table 75 DIO Mapping, Packet Mode
DIOx Mapping
00
DIO0
DIO1
DIO2
DIO3
DIO4
DIO5
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
Sleep
Standby
FSRx/Tx
TempChange / LowBat
FifoLevel
FifoEmpty
FifoFull
FifoFull
FifoLevel
FifoEmpty
FifoFull
FifoFull
FifoFull
FifoFull
FifoEmpty
FifoEmpty
FifoEmpty
TempChange / LowBat
ClkOut if RC
ClkOut
-
-
Tx
PacketSent
-
TempChange / LowBat
FifoLevel
FifoEmpty
FifoFull
FifoFull
RxReady
TimeOut
SyncAddress
FifoEmpty
FifoEmpty
FifoEmpty
Rx
PayloadReady
CrcOk
ModeReady
FifoFull
FifoFull
FifoEmpty
TxReady
FifoEmpty
FifoEmpty
TempChange / LowBat
PllLock
TimeOut
Rssi / PreambleDetect
ClkOut
PllLock
Data
ModeReady
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4.2.12. Continuous Mode
4.2.12.1. General Description
As illustrated in Figure 29, in Continuous mode the NRZ data to (from) the (de)modulator is directly accessed by the uC on
the bidirectional DIO2/DATA pin. The FIFO and packet handler are thus inactive.
DIO0
DIO1/DCLK
DIO2/DATA
DIO3
DIO4
DIO5
Tx/Rx
CONTROL
Data
Rx
SYNC
RECOG.
SPI
NSS
SCK
MOSI
MISO
Figure 29. Continuous Mode Conceptual View
4.2.12.2. Tx Processing
In Tx mode, a synchronous data clock for an external uC is provided on DIO1/DCLK pin. Clock timing with respect to the
data is illustrated in Figure 30. DATA is internally sampled on the rising edge of DCLK so the uC can change logic state
anytime outside the grayed out setup/hold zone.
T_DATA
T_DATA
DATA
(NRZ)
DCLK
Figure 30. Tx Processing in Continuous Mode
Note
the use of DCLK is required when the modulation shaping is enabled (see section 3.4.5).
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4.2.12.3. Rx Processing
If the bit synchronizer is disabled, the raw demodulator output is made directly available on DATA pin and no DCLK signal
is provided.
Conversely, if the bit synchronizer is enabled, synchronous cleaned data and clock are made available respectively on
DIO2/DATA and DIO1/DCLK pins. DATA is sampled on the rising edge of DCLK and updated on the falling edge as
illustrated below.
DATA (NRZ)
DCLK
Figure 31. Rx Processing in Continuous Mode
Note
In Continuous mode it is always recommended to enable the bit synchronizer to clean the DATA signal even if the
DCLK signal is not used by the uC (bit synchronizer is automatically enabled in Packet mode).
4.2.13. Packet Mode
4.2.13.1. General Description
In Packet mode the NRZ data to (from) the (de)modulator is not directly accessed by the uC but stored in the FIFO and
accessed via the SPI interface.
In addition, the RFM95/96/97/98(W) packet handler performs several packet oriented tasks such as Preamble and Sync
word generation, CRC calculation/check, whitening/dewhitening of data, Manchester encoding/decoding, address filtering,
etc. This simplifies software and reduces uC overhead by performing these repetitive tasks within the RF chip itself.
Another important feature is ability to fill and empty the FIFO in Sleep/Stdby mode, ensuring optimum power consumption
and adding more flexibility for the software.
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DIO0
DIO1
DIO2
DIO3
DIO4
DIO5
CONTROL
Data
Rx
DATASHEET
SYNC
RECOG.
PACKET
HANDLER
FIFO
(+SR)
SPI
NSS
SCK
MOSI
MISO
Tx
Figure 32. Packet Mode Conceptual View
Note
The Bit Synchronizer is automatically enabled in Packet mode.
4.2.13.2. Packet Format
Fixed Length Packet Format
Fixed length packet format is selected when bit PacketFormat is set to 0 and PayloadLength is set to any value greater
than 0.
In applications where the packet length is fixed in advance, this mode of operation may be of interest to minimize RF
overhead (no length byte field is required). All nodes, whether Tx only, Rx only, or Tx/Rx should be programmed with the
same packet length value.
The length of the payload is limited to 2047 bytes.
The length programmed in PayloadLength relates only to the payload which includes the message and the optional
address byte. In this mode, the payload must contain at least one byte, i.e. address or message byte.
An illustration of a fixed length packet is shown below. It contains the following fields:
Preamble (1010...)
Sync word (Network ID)
Optional Address byte (Node ID)
Message data
Optional 2-bytes CRC checksum
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Optional DC free data coding
CRC checksum calculation
Preamble
Sync Word
0 to 65536 bytes 0 to 8 bytes
Address
byte
Message
Up to 2047 bytes
CRC
2-bytes
Payload
(min 1 byte)
Fields added by the packet handler in Tx and processed and removed in Rx
Optional User provided fields which are part of the payload
Message part of the payload
Figure 33. Fixed Length Packet Format
Variable Length Packet Format
Variable length packet format is selected when bit PacketFormat is set to 1.
This mode is useful in applications where the length of the packet is not known in advance and can vary over time. It is then
necessary for the transmitter to send the length information together with each packet in order for the receiver to operate
properly.
In this mode the length of the payload, indicated by the length byte, is given by the first byte of the FIFO and is limited to
255 bytes. Note that the length byte itself is not included in its calculation. In this mode, the payload must contain at least 2
bytes, i.e. length + address or message byte.
An illustration of a variable length packet is shown below. It contains the following fields:
Preamble (1010...)
Sync word (Network ID)
Length byte
Optional Address byte (Node ID)
Message data
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Optional 2-bytes CRC checksum
Optional DC free data coding
CRC checksum calculation
Preamble
Sync Word
0 to 65536 bytes 0 to 8 bytes
Length
byte
Address
byte
Message
Up to 255 bytes
CRC
2-bytes
Payload
(min 2 bytes)
Fields added by the packet handler in Tx and processed and removed in Rx
Optional User provided fields which are part of the payload
Message part of the payload
Figure 34. Variable Length Packet Format
Unlimited Length Packet Format
Unlimited length packet format is selected when bit PacketFormat is set to 0 and PayloadLength is set to 0. The user can
then transmit and receive packet of arbitrary length and PayloadLength register is not used in Tx/Rx modes for counting
the length of the bytes transmitted/received.
In Tx the data is transmitted depending on the TxStartCondition bit. On the Rx side the data processing features like
Address filtering, Manchester encoding and data whitening are not available if the sync pattern length is set to zero
(SyncOn = 0). The filling of the FIFO in this case can be controlled by the bit FifoFillCondition. The CRC detection in Rx is
also not supported in this mode of the packet handler, however CRC generation in Tx is operational. The interrupts like
CrcOk & PayloadReady are not available either.
An unlimited length packet shown below is made up of the following fields:
Preamble (1010...).
Sync word (Network ID).
Optional Address byte (Node ID).
Message data
Optional 2-bytes CRC checksum (Tx only)
DC free Data encoding
Preamble
0 to 65535
bytes
Sync Word
0 to 8 bytes
Address
byte
Message
unlimited length
Payload
Fields added by the packet handler in Tx and processed and removed in Rx
Message part of the payload
Optional User provided fields which are part of the payload
Figure 35. Unlimited Length Packet Format
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4.2.13.3. Tx Processing
In Tx mode the packet handler dynamically builds the packet by performing the following operations on the payload
available in the FIFO:
Add a programmable number of preamble bytes
Add a programmable Sync word
Optionally calculating CRC over complete payload field (optional length byte + optional address byte + message) and
appending the 2 bytes checksum.
Optional DC-free encoding of the data (Manchester or whitening)
Only the payload (including optional address and length fields) is required to be provided by the user in the FIFO.
The transmission of packet data is initiated by the Packet Handler only if the chip is in Tx mode and the transmission
condition defined by TxStartCondition is fulfilled. If transmission condition is not fulfilled then the packet handler transmits a
preamble sequence until the condition is met. This happens only if the preamble length /= 0, otherwise it transmits a zero or
one until the condition is met to transmit the packet data.
The transmission condition itself is defined as:
if TxStartCondition = 1, the packet handler waits until the first byte is written into the FIFO, then it starts sending the
preamble followed by the sync word and user payload
If TxStartCondition = 0, the packet handler waits until the number of bytes written in the FIFO is equal to the number
defined in RegFifoThresh + 1
If the condition for transmission was already fulfilled i.e. the FIFO was filled in Sleep/Stdby then the transmission of
packet starts immediately on enabling Tx
4.2.13.4. Rx Processing
In Rx mode the packet handler extracts the user payload to the FIFO by performing the following operations:
Receiving the preamble and stripping it off
Detecting the Sync word and stripping it off
Optional DC-free decoding of data
Optionally checking the address byte
Optionally checking CRC and reflecting the result on CrcOk.
Only the payload (including optional address and length fields) is made available in the FIFO.
When the Rx mode is enabled the demodulator receives the preamble followed by the detection of sync word. If fixed
length packet format is enabled then the number of bytes received as the payload is given by the PayloadLength
parameter.
In variable length mode the first byte received after the sync word is interpreted as the length of the received packet. The
internal length counter is initialized to this received length. The PayloadLength register is set to a value which is greater
than the maximum expected length of the received packet. If the received length is greater than the maximum length stored
in PayloadLength register the packet is discarded otherwise the complete packet is received.
If the address check is enabled then the second byte received in case of variable length and first byte in case of fixed
length is the address byte. If the address matches to the one in the NodeAddress field, reception of the data continues
otherwise it's stopped. The CRC check is performed if CrcOn = 1 and the result is available in CrcOk indicating that the
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CRC was successful. An interrupt (PayloadReady) is also generated on DIO0 as soon as the payload is available in the
FIFO. The payload available in the FIFO can also be read in Sleep/Standby mode.
If the CRC fails the PayloadReady interrupt is not generated and the FIFO is cleared. This function can be overridden by
setting CrcAutoClearOff = 1, forcing the availability of PayloadReady interrupt and the payload in the FIFO even if the CRC
fails.
4.2.13.5. Handling Large Packets
When PayloadLength exceeds FIFO size (64 bytes) whether in fixed, variable or unlimited length packet format, in addition
to PacketSent in Tx and PayloadReady or CrcOk in Rx, the FIFO interrupts/flags can be used as described below:
For Tx:
FIFO can be prefilled in Sleep/Standby but must be refilled “on-the-fly” during Tx with the rest of the payload.
1) Pre-fill FIFO (in Sleep/Standby first or directly in Tx mode) until FifoThreshold or FifoFull is set
2) In Tx, wait for FifoThreshold or FifoEmpty to be set (i.e. FIFO is nearly empty)
3) Write bytes into the FIFO until FifoThreshold or FifoFull is set.
4) Continue to step 2 until the entire message has been written to the FIFO (PacketSent will fire when the last bit of the
packet has been sent).
For Rx:
FIFO must be unfilled “on-the-fly” during Rx to prevent FIFO overrun.
1) Start reading bytes from the FIFO when FifoEmpty is cleared or FifoThreshold becomes set.
2) Suspend reading from the FIFO if FifoEmpty fires before all bytes of the message have been read
3) Continue to step 1 until PayloadReady or CrcOk fires
4) Read all remaining bytes from the FIFO either in Rx or Sleep/Standby mode
4.2.13.6. Packet Filtering
The RFM95/96/97/98(W) packet handler offers several mechanisms for packet filtering, ensuring that only useful
packets are made available to the uC, reducing significantly system power consumption and software complexity.
Sync Word Based
Sync word filtering/recognition is used for identifying the start of the payload and also for network identification. As
previously described, the Sync word recognition block is configured (size, value) in RegSyncConfig and RegSyncValue(i)
registers. This information is used, both for appending Sync word in Tx, and filtering packets in Rx.
Every received packet which does not start with this locally configured Sync word is automatically discarded and no
interrupt is generated.
When the Sync word is detected, payload reception automatically starts and SyncAddressMatch is asserted.
Note
Sync Word values containing 0x00 byte(s) are forbidden
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Address Based
Address filtering can be enabled via the AddressFiltering bits. It adds another level of filtering, above Sync word (i.e. Sync
must match first), typically useful in a multi-node networks where a network ID is shared between all nodes (Sync word)
and each node has its own ID (address).
Two address based filtering options are available:
AddressFiltering = 01: Received address field is compared with internal register NodeAddress. If they match then the
packet is accepted and processed, otherwise it is discarded.
AddressFiltering = 10: Received address field is compared with internal registers NodeAddress and BroadcastAddress.
If either is a match, the received packet is accepted and processed, otherwise it is discarded. This additional check with
a constant is useful for implementing broadcast in a multi-node networks
Please note that the received address byte, as part of the payload, is not stripped off the packet and is made available in
the FIFO. In addition, NodeAddress and AddressFiltering only apply to Rx. On Tx side, if address filtering is expected, the
address byte should simply be put into the FIFO like any other byte of the payload.
As address filtering requires a Sync word match, both features share the same interrupt flag SyncAddressMatch.
Length Based
In variable length Packet mode, PayloadLength must be programmed with the maximum payload length permitted. If
received length byte is smaller than this maximum then the packet is accepted and processed, otherwise it is discarded.
Please note that the received length byte, as part of the payload, is not stripped off the packet and is made available in the
FIFO.
To disable this function the user should set the value of the PayloadLength to 2047.
CRC Based
The CRC check is enabled by setting bit CrcOn in RegPacketConfig1. It is used for checking the integrity of the message.
On Tx side a two byte CRC checksum is calculated on the payload part of the packet and appended to the end of the
message
On Rx side the checksum is calculated on the received payload and compared with the two checksum bytes received.
The result of the comparison is stored in bit CrcOk.
By default, if the CRC check fails then the FIFO is automatically cleared and no interrupt is generated. This filtering function
can be disabled via CrcAutoClearOff bit and in this case, even if CRC fails, the FIFO is not cleared and only PayloadReady
interrupt goes high. Please note that in both cases, the two CRC checksum bytes are stripped off by the packet handler
and only the payload is made available in the FIFO. Two CRC implementations are selected with bit CrcWhiteningType.
Table 76 CRC Description
Crc Type
CrcWhiteningType
CCITT
0 (default)
IBM
1
Polynomial
Seed Value
Complemented
+1
0x1D0F
Yes
X16 + X15 + X2 + 1
0xFFFF
No
X16
+
X12
+
X5
A C code implementation of each CRC type is proposed in Application Section 7.
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4.2.13.7. DC-Free Data Mechanisms
The payload to be transmitted may contain long sequences of 1's and 0's, which introduces a DC bias in the transmitted
signal. The radio signal thus produced has a non uniform power distribution over the occupied channel bandwidth. It also
introduces data dependencies in the normal operation of the demodulator. Thus it is useful if the transmitted data is random
and DC free.
For such purposes, two techniques are made available in the packet handler: Manchester encoding and data whitening.
Note
Only one of the two methods can be enabled at a time.
Manchester Encoding
Manchester encoding/decoding is enabled if DcFree = 01 and can only be used in Packet mode.
The NRZ data is converted to Manchester code by coding '1' as “10” and '0' as “01”.
In this case, the maximum chip rate is the maximum bit rate given in the specifications section and the actual bit rate is half
the chip rate.
Manchester encoding and decoding is only applied to the payload and CRC checksum while preamble and Sync word are
kept NRZ. However, the chip rate from preamble to CRC is the same and defined by BitRate in RegBitRate (Chip Rate =
Bit Rate NRZ = 2 x Bit Rate Manchester).
Manchester encoding/decoding is thus made transparent for the user, who still provides/retrieves NRZ data to/from the
FIFO.
1/BR ...Sync
RF chips @ BR
User/NRZ bits
Manchester OFF
User/NRZ bits
Manchester ON
1/BR
...
1
1
1
0
1
0
0
1
0
0
1
Payload...
0
1
1
0
1
0
...
...
1
1
1
0
1
0
0
1
0
0
1
0
0
1
0
...
...
1
1
1
0
1
0
0
1
0
1
0
1
1
1
t
...
Figure 36. Manchester Encoding/Decoding
Data Whitening
Another technique called whitening or scrambling is widely used for randomizing the user data before radio transmission.
The data is whitened using a random sequence on the Tx side and de-whitened on the Rx side using the same sequence.
Comparing to Manchester technique it has the advantage of keeping NRZ data rate i.e. actual bit rate is not halved.
The whitening/de-whitening process is enabled if DcFree = 10. A 9-bit LFSR is used to generate a random sequence. The
payload and 2-byte CRC checksum is then XORed with this random sequence as shown below. The data is de-whitened
on the receiver side by XORing with the same random sequence.
Payload whitening/de-whitening is thus made transparent for the user, who still provides/retrieves NRZ data to/from the
FIFO.
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L F S R P o ly n o m ia l = X 9 + X 5 + 1
X8
X7
X6
X5
X4
X3
T ra n s m it d a ta
X2
X1
X0
W h ite n e d d a ta
Figure 37. Data Whitening Polynomial
4.2.13.8. Beacon Tx Mode
In some short range wireless network topologies a repetitive message, also known as beacon, is transmitted periodically
by a transmitter. The Beacon Tx mode allows for the re-transmission of the same packet without having to fill the FIFO
multiple times with the same data.
When BeaconOn in RegPacketConfig2 is set to 1, the FIFO can be filled only once in Sleep or Stdby mode with the
required payload. After a first transmission, FifoEmpty will go high as usual, but the FIFO content will be restored when the
chip exits Transmit mode. FifoEmpty, FifoFull and FifoLevel flags are also restored.
This feature is only available in Fixed packet format, with the Payload Length smaller than the FIFO size. The control of the
chip modes (Tx-Sleep-Tx....) can either be undertaken by the microcontroller, or be automated in the Top Sequencer. See
example in section 4.2.13.8.
The Beacon Tx mode is exited by setting BeaconOn to 0, and clearing the FIFO by setting FifoOverrun to 1.
4.2.14. io-homecontrol® Compatibility Mode
The RFM95/96/97/98(W) features a io-homecontrol® compatibility mode. Please contact your local Hope RF
representative for details on its implementation.
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4.3. SPI Interface
The SPI interface gives access to the configuration register via a synchronous full-duplex protocol corresponding to
CPOL = 0 and CPHA = 0 in Motorola/Freescale nomenclature. Only the slave side is implemented.
Three access modes to the registers are provided:
SINGLE access: an address byte followed by a data byte is sent for a write access whereas an address byte is sent and
a read byte is received for the read access. The NSS pin goes low at the beginning of the frame and goes high after the
data byte.
BURST access: the address byte is followed by several data bytes. The address is automatically incremented internally
between each data byte. This mode is available for both read and write accesses. The NSS pin goes low at the
beginning of the frame and stay low between each byte. It goes high only after the last byte transfer.
FIFO access: if the address byte corresponds to the address of the FIFO, then succeeding data byte will address the
FIFO. The address is not automatically incremented but is memorized and does not need to be sent between each data
byte. The NSS pin goes low at the beginning of the frame and stay low between each byte. It goes high only after the
last byte transfer.
The figure below shows a typical SPI single access to a register.
Figure 38. SPI Timing Diagram (single access)
MOSI is generated by the master on the falling edge of SCK and is sampled by the slave (i.e. this SPI interface) on the
rising edge of SCK. MISO is generated by the slave on the falling edge of SCK.
A transfer is always started by the NSS pin going low. MISO is high impedance when NSS is high.
The first byte is the address byte. It is comprises:
A wnr bit, which is 1 for write access and 0 for read access.
Then 7 bits of address, MSB first.
The second byte is a data byte, either sent on MOSI by the master in case of a write access or received by the master on
MISO in case of read access. The data byte is transmitted MSB first.
Proceeding bytes may be sent on MOSI (for write access) or received on MISO (for read access) without a rising NSS
edge and re-sending the address. In FIFO mode, if the address was the FIFO address then the bytes will be written / read
at the FIFO address. In Burst mode, if the address was not the FIFO address, then it is automatically incremented for each
new byte received.
The frame ends when NSS goes high. The next frame must start with an address byte. The SINGLE access mode is
therefore a special case of FIFO / BURST mode with only 1 data byte transferred.
During the write access, the byte transferred from the slave to the master on the MISO line is the value of the written
register before the write operation.
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5. RFM95/96/97/98(W) Analog & RF Frontend Electronics
5.1. Power Supply Strategy
The RFM95/96/97/98(W) employs an internal voltage regulation scheme which provides stable operating voltage, and
hence device characteristics, over the full industrial temperature and operating voltage range of operation. This includes
up to
+17 dBm of RF output power which is maintained from 1.8 V to 3.7 V and +20 dBm from 2.4 V to 3.7 V.
The RFM95/96/97/98(W) can be powered from any low-noise voltage source via pins VBAT_ANA, VBAT_RF and
VBAT_DIG. Decoupling capacitors should be connected, as suggested in the reference design of the applications section
of this document, on VR_PA, VR_DIG and VR_ANA pins to ensure correct operation of the built-in voltage regulators.
5.2. Low Battery Detector
A low battery detector is also included allowing the generation of an interrupt signal in response to the supply voltage
dropping below a programmable threshold that is adjustable through the register RegLowBat. The interrupt signal can be
mapped to any of the DIO pins by programming RegDioMapping.
5.3. Frequency Synthesis
5.3.1. Crystal Oscillator
The crystal oscillator is the main timing reference of the RFM95/96/97/98(W). It is used as the reference for the PLL’s
frequency synthesis and as the clock signal for all digital processing.
The crystal oscillator startup time, TS_OSC, depends on the electrical characteristics of the crystal reference used, for
more information on the electrical specification of the crystal see Section 2.3. The crystal connects to the Pierce oscillator
on pins XTA and XTB. The RFM95/96/97/98(W) optimizes the startup time and automatically triggers the PLL when the
oscillator signal is stable.
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5.3.2. CLKOUT Output
The reference frequency, or a fraction of it, can be provided on DIO5 (pin 13) by modifying bits ClkOut in RegDioMapping2.
Two typical applications of the CLKOUT output include:
To provide a clock output for a companion processor, thus saving the cost of an additional oscillator. CLKOUT can be
made available in any operation mode except Sleep mode and is automatically enabled at power on reset.
To provide an oscillator reference output. Measurement of the CLKOUT signal enables simple software trimming of the
initial crystal tolerance.
Note
To minimize the current consumption of the RFM95/96/97/98(W), please ensure that the CLKOUT signal is
disabled when not required.
5.3.3. PLL
The local oscillator of the RFM95/96/97/98(W) is derived from two almost identical fractional-N PLLs that are referenced
to the crystal oscillator circuit. Both PLLs feature a programmable bandwidth setting where one of four discrete preset
bandwidths may be accessed.
The RFM95/96/97/98(W) PLL uses a 19-bit sigma-delta modulator whose frequency resolution, constant over the whole
frequency range, is given by:
FXOSC
F STE P = --------------19
2
The carrier frequency is programmed through RegFrf, split across addresses 0x06 to 0x08:
F RF = FSTEP × Frf(23,0)
Note
The Frf setting is split across 3 bytes. A change in the center frequency will only be taken into account when the
least significant byte FrfLsb in RegFrfLsb is written. This allows the potential for user generation of m-ary FSK at
very low bit rates. This is possible where frequency modulation is achieved by direct programming of the
programmed RF centre frequency. To enable this functionality set the FastHopOn bit of register RegPllHop.
5.3.4. RC Oscillator
All timing operations in the low-power Sleep state of the Top Level Sequencer rely on the accuracy of the internal lowpower RC oscillator. This oscillator is automatically calibrated at the device power-up not requiring any user input.
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5.4. Transmitter Description
The transmitter of RFM95/96/97/98(W) comprises the frequency synthesizer, modulator (both LoRaTM and FSK/OOK) and
power amplifier blocks, together with the DC biasing and ramping functionality that is provided through the VR_PA block.
5.4.1. Architecture Description
The architecture of the RF front end is shown in the following diagram.
Figure 40. RF Front-end Architecture Shows the Internal PA Configuration.
5.4.2. RF Power Amplifiers
PA_HF and PA_LF are high efficiency amplifiers capable of yielding RF power programmable in 1 dB steps from -4 to
+14dBm directly into a 50 ohm load with low current consumption. PA_LF covers the lower bands (up to 525 MHz), whilst
PA_HF will cover the upper bands (from 860 MHz). The output power is sensitive to the power supply voltage, and typically
their performance is expressed at 3.3V.
PA_HP (High Power), connected to the PA_BOOST pin, covers all frequency bands that the chip addresses. It permits
continuous operation at up to +17 dBm and duty cycled operation at up to +20dBm. For full details of operation at +20dBm
please consult Section 5.4.3
Table 77 Power Amplifier Mode Selection Truth Table
PaSelect
Mode
Power Range
Pout Formula
0
PA_HF or PA_LF on RFO_HF or RFO_LF
-4 to +15dBm
Pout=Pmax-(15-OutputPower)
Pmax=10.8+0.6*MaxPower [dBm]
1
PA_HP on PA_BOOST, any frequency
+2 to +17dBm
Pout=17-(15-OutputPower) [dBm]
Notes - For +20 dBm restrictions on operation please consult the following section.
- To ensure correct operation at the highest power levels ensure that the current limiter OcpTrim is adjusted to
permit delivery of the requisite supply current.
- If the PA_BOOST pin is not used it may be left floating.
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5.4.3. High Power +20 dBm Operation
The RFM95/96/97/98(W) have a high power +20 dBm capability on PA_BOOST pin, with the following settings:
Table 78 High Power Settings
Register
Address
Value for
High Power
Default value
PA_HF/LF or
+17dBm
Description
RegPaDac
0x4d
0x87
0x84
Set Pmax to +20dBm for PA_HP
Notes - High Power settings must be turned off when using PA_LF or PA_HF
- The Over Current Protection limit should be adapted to the actual power level, in RegOcp
Specific Absolute Maximum Ratings and Operating Range restrictions apply to the +20 dBm operation. They are listed in
Table 79 and Table 80.
Table 79 Operating Range, +20dBm Operation
Symbol
Description
Min
Max
Unit
DC_20dBm
Duty Cycle of transmission at +20 dBm output
-
1
%
VSWR_20dBm
Maximum VSWR at antenna port, +20 dBm output
-
3:1
-
Min
Max
Unit
2.4
3.7
V
Table 80 Operating Range, +20dBm Operation
Symbol
VDDop_20dBm
Description
Supply voltage, +20 dBm output
The duty cycle of transmission at +20 dBm is limited to 1%, with a maximum VSWR of 3:1 at antenna port, over the
standard operating range [-40;+85°C]. For any other operating condition, contact your Hope RF representative.
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5.4.4. Over Current Protection
The power amplifiers of RFM95/96/97/98(W) are protected against current over supply in adverse RF load conditions by
the over current protection block. This has the added benefit of protecting battery chemistries with limited peak current
capability and minimising worst case PA consumption in battery life calculation. The current limiter value is controlled by the
OcpTrim bits in RegOcp, and is calculated according to the following formulae:
Table 81 Trimming of the OCP Current
OcpTrim
IMAX
Imax Formula
0 to 15
45 to 120 mA
45 + 5*OcpTrim [mA]
16 to 27
130 to 240 mA
-30 + 10*OcpTrim [mA]
27+
240 mA
240 mA
Note Imax sets a limit on the current drain of the Power Amplifier only, hence the maximum current drain of the RFM96/
77/78 is equal to Imax + IFS.
5.5. Receiver Description
5.5.1. Overview
The RFM95/96/97/98(W) features a digital receiver with the analog to digital conversion process being performed directly
following the LNA-Mixers block. In addition to the LoRaTM modulation scheme the low-IF receiver is able to demodulate
ASK, OOK, (G)FSK and (G)MSK modulation. All filtering, demodulation, gain control, synchronization and packet handling
is performed digitally allowing a high degree of programmable flexibility. The receiver also has automatic gain calibration,
this improves the precision of RSSI measurement and enhances image rejection.
5.5.2. Receiver Enabled and Receiver Active States
In the receiver operating mode two states of functionality are defined. Upon initial transition to receiver operating mode the
receiver is in the ‘receiver-enabled’ state. In this state the receiver awaits for either the user defined valid preamble or RSSI
detection criterion to be fulfilled. Once met the receiver enters ‘receiver-active’ state. In this second state the received
signal is processed by the packet engine and top level sequencer. For a complete description of the digital functions of the
RFM95/96/97/98(W) receiver please see Section 4 of the datasheet.
5.5.3. Automatic Gain Control In FSK/OOK Mode
The AGC feature allows receiver to handle a wide Rx input dynamic range from the sensitivity level up to maximum input
level of 0dBm or more, whilst optimizing the system linearity.
The following table shows typical NF and IIP3 performances for the RFM95/96/97/98(W) LNA gains
available.
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Table 82 LNA Gain Control and Performances
LnaGain
Relative LNA
Gain [dB]
NF
Lower/Higher
band
[dB]
IIP3
Lower/Higher
band [dBm]
G1
‘001’
0 dB
5/7
-22/-12
AgcThresh1 < Pin = 7.
RegSyncValue8
(0x2f)
7-0
SyncValue(7:0)
rw
0x01
*
8th byte of Sync word.
Used if SyncOn is set and (SyncSize +1) = 8.
7
PacketFormat
rw
0x01
Defines the packet format used:
0 Æ Fixed length
1 Æ Variable length
6-5
DcFree
rw
0x00
Defines DC-free encoding/decoding performed:
00 Æ None (Off)
01 Æ Manchester
10 Æ Whitening
11 Æ reserved
4
CrcOn
rw
0x01
Enables CRC calculation/check (Tx/Rx):
0 Æ Off
1 Æ On
0x00
Defines the behavior of the packet handler when CRC check fails:
0 Æ Clear FIFO and restart new packet reception. No
PayloadReady interrupt issued.
1 Æ Do not clear FIFO. PayloadReady interrupt issued.
RegPacketConfig1
(0x30)
3
RegPacketConfig2
(0x31)
FSK/OOK Description
CrcAutoClearOff
rw
2-1
AddressFiltering
rw
0x00
Defines address based filtering in Rx:
00 Æ None (Off)
01 Æ Address field must match NodeAddress
10 Æ Address field must match NodeAddress or
BroadcastAddress
11 Æ reserved
0
CrcWhiteningType
rw
0x00
Selects the CRC and whitening algorithms:
0 Æ CCITT CRC implementation with standard whitening
1 Æ IBM CRC implementation with alternate whitening
7
unused
r
-
6
DataMode
rw
0x01
Data processing mode:
0 Æ Continuous mode
1 Æ Packet mode
unused
5
IoHomeOn
rw
0x00
Enables the io-homecontrol® compatibility mode
0 Æ Disabled
1 Æ Enabled
4
IoHomePowerFrame
rw
0x00
reserved - Linked to io-homecontrol® compatibility mode
3
BeaconOn
rw
0x00
Enables the Beacon mode in Fixed packet format
2-0
PayloadLength(10:8)
rw
0x00
Packet Length Most significant bits
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Name
(Address)
Bits
Variable Name
Mode
Default
value
FSK/OOK Description
RegPayloadLength
(0x32)
7-0
PayloadLength(7:0)
rw
0x40
If PacketFormat = 0 (fixed), payload length.
If PacketFormat = 1 (variable), max length in Rx, not used in Tx.
RegNodeAdrs
(0x33)
7-0
NodeAddress
rw
0x00
RegBroadcastAdrs
(0x34)
7-0
BroadcastAddress
rw
0x00
Broadcast address used in address filtering.
Defines the condition to start packet transmission:
0 Æ FifoLevel (i.e. the number of bytes in the FIFO exceeds
FifoThreshold)
1 Æ FifoEmpty goes low(i.e. at least one byte in the FIFO)
RegFifoThresh
(0x35)
7
TxStartCondition
rw
0x01
*
6
unused
r
-
5-0
FifoThreshold
rw
0x0f
Node address used in address filtering.
unused
Used to trigger FifoLevel interrupt, when:
number of bytes in FIFO >= FifoThreshold + 1
Sequencer registers
7
SequencerStart
wt
0x00
Controls the top level Sequencer
When set to ‘1’, executes the “Start” transition.
The sequencer can only be enabled when the chip is in Sleep or
Standby mode.
6
SequencerStop
wt
0x00
Forces the Sequencer Off.
Always reads ‘0’
5
IdleMode
rw
0x00
Selects chip mode during the state:
0: Standby mode
1: Sleep mode
0x00
Controls the Sequencer transition when SequencerStart is set to 1
in Sleep or Standby mode:
00: to LowPowerSelection
01: to Receive state
10: to Transmit state
11: to Transmit state on a FifoLevel interrupt
4-3
FromStart
rw
RegSeqConfig1
(0x36)
2
LowPowerSelection
rw
0x00
Selects the Sequencer LowPower state after a to
LowPowerSelection transition:
0: SequencerOff state with chip on Initial mode
1: Idle state with chip on Standby or Sleep mode depending on
IdleMode
Note:
Initial mode is the chip LowPower mode at
Sequencer Start.
1
FromIdle
rw
0x00
Controls the Sequencer transition from the Idle state on a T1
interrupt:
0: to Transmit state
1: to Receive state
0
FromTransmit
rw
0x00
Controls the Sequencer transition from the Transmit state:
0: to LowPowerSelection on a PacketSent interrupt
1: to Receive state on a PacketSent interrupt
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RFM95/96/97/98(W)
WIRELESS & SENSING
Name
(Address)
Bits
7-5
Variable Name
FromReceive
PRELIMINARY
Mode
rw
Default
value
0x00
DATASHEET
FSK/OOK Description
Controls the Sequencer transition from the Receive state
000 and 111: unused
001: to PacketReceived state on a PayloadReady interrupt
010: to LowPowerSelection on a PayloadReady interrupt
011: to PacketReceived state on a CrcOk interrupt (1)
100: to SequencerOff state on a Rssi interrupt
101: to SequencerOff state on a SyncAddress interrupt
110: to SequencerOff state on a PreambleDetect interrupt
Irrespective of this setting, transition to LowPowerSelection on a
T2 interrupt
(1) If the CRC is wrong (corrupted packet, with CRC on but
CrcAutoClearOn=0), the PayloadReady interrupt will drive the
sequencer to RxTimeout state.
RegSeqConfig2
(0x37)
4-3
FromRxTimeout
rw
0x00
Controls the state-machine transition from the Receive state on a
RxTimeout interrupt (and on PayloadReady if FromReceive =
011):
00: to Receive State, via ReceiveRestart
01: to Transmit state
10: to LowPowerSelection
11: to SequencerOff state
Note: RxTimeout interrupt is a TimeoutRxRssi,
TimeoutRxPreamble or TimeoutSignalSync interrupt
2-0
FromPacketReceived
rw
0x00
Controls the state-machine transition from the PacketReceived
state:
000: to SequencerOff state
001: to Transmit state on a FifoEmpty interrupt
010: to LowPowerSelection
011: to Receive via FS mode, if frequency was changed
100: to Receive state (no frequency change)
7-4
unused
r
-
unused
0x00
Resolution of Timer 1
00: Timer1 disabled
01: 64 us
10: 4.1 ms
11: 262 ms
3-2
Timer1Resolution
rw
RegTimerResol
(0x38)
1-0
Timer2Resolution
rw
0x00
Resolution of Timer 2
00: Timer2 disabled
01: 64 us
10: 4.1 ms
11: 262 ms
RegTimer1Coef
(0x39)
7-0
Timer1Coefficient
rw
0xf5
Multiplying coefficient for Timer 1
RegTimer2Coef
(0x3a)
7-0
Timer2Coefficient
rw
0x20
Multiplying coefficient for Timer 2
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Page 96
RFM95/96/97/98(W)
WIRELESS & SENSING
Name
(Address)
Bits
Variable Name
PRELIMINARY
Mode
Default
value
DATASHEET
FSK/OOK Description
Service registers
RegImageCal
(0x3b)
7
AutoImageCalOn
rw
0x00
*
Controls the Image calibration mechanism
0 Æ Calibration of the receiver depending on the temperature is
disabled
1 Æ Calibration of the receiver depending on the temperature
enabled.
6
ImageCalStart
wt
-
Triggers the IQ and RSSI calibration when set in Standby mode.
5
ImageCalRunning
r
0x00
4
unused
r
-
3
2-1
RegTemp
(0x3c)
TempChange
TempThreshold
r
rw
Set to 1 while the Image and RSSI calibration are running.
Toggles back to 0 when the process is completed
unused
0x00
IRQ flag witnessing a temperature change exceeding
TempThreshold since the last Image and RSSI calibration:
0 Æ Temperature change lower than TempThreshold
1 Æ Temperature change greater than TempThreshold
0x01
Temperature change threshold to trigger a new I/Q calibration
00 Æ 5 °C
01 Æ 10 °C
10 Æ 15 °C
11 Æ 20 °C
Controls the temperature monitor operation:
0 Æ Temperature monitoring done in all modes except Sleep and
Standby
1 Æ Temperature monitoring stopped.
0
TempMonitorOff
rw
0x00
7-0
TempValue
r
-
Measured temperature
-1°C per Lsb
Needs calibration for absolute accuracy
7-4
unused
r
-
unused
3
LowBatOn
rw
0x00
Low Battery detector enable signal
0 Æ LowBat detector disabled
1 Æ LowBat detector enabled
0x02
Trimming of the LowBat threshold:
000 Æ 1.695 V
001 Æ 1.764 V
010 Æ 1.835 V (d)
011 Æ 1.905 V
100 Æ 1.976 V
101 Æ 2.045 V
110 Æ 2.116 V
111 Æ 2.185 V
RegLowBat
(0x3d)
2-0
LowBatTrim
rw
Status registers
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Page 97
RFM95/96/97/98(W)
WIRELESS & SENSING
Name
(Address)
RegIrqFlags1
(0x3e)
RegIrqFlags2
(0x3f)
Bits
PRELIMINARY
Variable Name
Mode
Default
value
DATASHEET
FSK/OOK Description
7
ModeReady
r
-
Set when the operation mode requested in Mode, is ready
- Sleep: Entering Sleep mode
- Standby: XO is running
- FS: PLL is locked
- Rx: RSSI sampling starts
- Tx: PA ramp-up completed
Cleared when changing the operating mode.
6
RxReady
r
-
Set in Rx mode, after RSSI, AGC and AFC.
Cleared when leaving Rx.
5
TxReady
r
-
Set in Tx mode, after PA ramp-up.
Cleared when leaving Tx.
4
PllLock
r
-
Set (in FS, Rx or Tx) when the PLL is locked.
Cleared when it is not.
3
Rssi
rwc
-
Set in Rx when the RssiValue exceeds RssiThreshold.
Cleared when leaving Rx or setting this bit to 1.
2
Timeout
r
-
Set when a timeout occurs
Cleared when leaving Rx or FIFO is emptied.
1
PreambleDetect
rwc
-
Set when the Preamble Detector has found valid Preamble.
bit clear when set to 1
0
SyncAddressMatch
rwc
-
Set when Sync and Address (if enabled) are detected.
Cleared when leaving Rx or FIFO is emptied.
This bit is read only in Packet mode, rwc in Continuous mode
7
FifoFull
r
-
Set when FIFO is full (i.e. contains 66 bytes), else cleared.
6
FifoEmpty
r
-
Set when FIFO is empty, and cleared when there is at least 1 byte
in the FIFO.
5
FifoLevel
r
-
Set when the number of bytes in the FIFO strictly exceeds
FifoThreshold, else cleared.
4
FifoOverrun
rwc
-
Set when FIFO overrun occurs. (except in Sleep mode)
Flag(s) and FIFO are cleared when this bit is set. The FIFO then
becomes immediately available for the next transmission /
reception.
3
PacketSent
r
-
Set in Tx when the complete packet has been sent.
Cleared when exiting Tx
2
PayloadReady
r
-
Set in Rx when the payload is ready (i.e. last byte received and
CRC, if enabled and CrcAutoClearOff is cleared, is Ok). Cleared
when FIFO is empty.
1
CrcOk
r
-
Set in Rx when the CRC of the payload is Ok. Cleared when FIFO
is empty.
0
LowBat
rwc
-
Set when the battery voltage drops below the Low Battery
threshold. Cleared only when set to 1 by the user.
IO control registers
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Page 98
RFM95/96/97/98(W)
WIRELESS & SENSING
Name
(Address)
RegDioMapping1
(0x40)
RegDioMapping2
(0x41)
PRELIMINARY
DATASHEET
Bits
Variable Name
Mode
Default
value
7-6
Dio0Mapping
rw
0x00
5-4
Dio1Mapping
rw
0x00
3-2
Dio2Mapping
rw
0x00
1-0
Dio3Mapping
rw
0x00
See Table 23 for mapping in LoRa mode
7-6
Dio4Mapping
rw
0x00
5-4
Dio5Mapping
rw
0x00
See Table 27 for mapping in Continuous mode
See table 28 for mapping in Packet mode
3-1
reserved
rw
0x00
reserved. Retain default value
0x00
Allows the mapping of either Rssi Or PreambleDetect to the DIO
pins, as summarized on Table 27 and Table 28
0 Æ Rssi interrupt
1 Æ PreambleDetect interrupt
0
MapPreambleDetect
rw
FSK/OOK Description
Mapping of pins DIO0 to DIO5
Version register
RegVersion
(0x42)
7-0
Version
r
0x11
Version code of the chip. Bits 7-4 give the full revision number;
bits 3-0 give the metal mask revision number.
Additional registers
RegPllHop
(0x44)
RegTcxo
(0x4b)
RegPaDac
(0x4d)
RegFormerTemp
(0x5b)
RegBitrateFrac
(0x5d)
7
FastHopOn
rw
0x00
Bypasses the main state machine for a quick frequency hop.
Writing RegFrfLsb will trigger the frequency change.
0 Æ Frf is validated when FSTx or FSRx is requested
1 Æ Frf is validated triggered when RegFrfLsb is written
6-0
reserved
rw
0x2d
reserved
7-5
reserved
rw
0x00
reserved. Retain default value
4
TcxoInputOn
rw
0x00
Controls the crystal oscillator
0 Æ Crystal Oscillator with external Crystal
1 Æ External clipped sine TCXO AC-connected to XTA pin
3-0
reserved
rw
0x09
Reserved. Retain default value.
7-3
reserved
rw
0x10
reserved. Retain default value
2-0
PaDac
rw
0x04
Enables the +20dBm option on PA_BOOST pin
0x04 Æ Default value
0x07 Æ +20dBm on PA_BOOST when OutputPower=1111
7-0
FormerTemp
rw
-
Temperature saved during the latest IQ (RSSI and Image)
calibrated. Same format as TempValue in RegTemp.
7-4
unused
r
0x00
unused
Fractional part of the bit rate divider (Only valid for FSK)
If BitRateFrac> 0 then:
3-0
BitRateFrac
rw
0x00
FXOSC
BitRate = ------------------------------------------------------------------------B itrate Frac
Bi tR ate(15,0) + ------------------------------16
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Page 99
RFM95/96/97/98(W)
WIRELESS & SENSING
Name
(Address)
RegAgcRef
(0x61)
PRELIMINARY
Bits
Variable Name
Mode
Default
value
7-6
unused
r
-
DATASHEET
FSK/OOK Description
unused
Sets the floor reference for all AGC thresholds:
AGC Reference[dBm]=
-174dBm+10*log(2*RxBw)+SNR+AgcReferenceLevel
SNR = 8dB, fixed value
5-0
AgcReferenceLevel
rw
0x19
RegAgcThresh1
(0x62)
7-5
unused
r
-
4-0
AgcStep1
rw
0x0c
Defines the 1st AGC Threshold
RegAgcThresh2
(0x63)
7-4
AgcStep2
rw
0x04
Defines the 2nd AGC Threshold:
3-0
AgcStep3
rw
0x0b
Defines the 3rd AGC Threshold:
RegAgcThresh3
(0x64)
7-4
AgcStep4
rw
0x0c
Defines the 4th AGC Threshold:
3-0
AgcStep5
rw
0x0c
Defines the 5th AGC Threshold:
unused
6.3. Band Specific Additional Registers
The registers in the address space from 0x61 to 0x73 are specific for operation in the lower frequency bands (below 525
MHz), or in the upper frequency bands (above 860 MHz). Their programmed value may differ, and are retained when
switching from lower to high frequency and vice-versa. The access to the band specific registers is granted by enabling or
disabling the bit 3 LowFrequencyModeOn of the RegOpMode register. By default, the bit LowFrequencyModeOn is at ‘1’
indicating that the registers are configured for the low frequency band.
Table 87 Low Frequency Additional Registers
Name
(Address)
RegAgcRefLf
(0x61)
Bits
Variable Name
Mode
Default
value
7-6
unused
r
-
Low Frequency Additional Registers
unused
Sets the floor reference for all AGC thresholds:
AGC Reference[dBm]=
-174dBm+10*log(2*RxBw)+SNR+AgcReferenceLevel
SNR = 8dB, fixed value
5-0
AgcReferenceLevel
rw
0x19
RegAgcThresh1Lf
(0x62)
7-5
unused
r
-
4-0
AgcStep1
rw
0x0c
Defines the 1st AGC Threshold
RegAgcThresh2Lf
(0x63)
7-4
AgcStep2
rw
0x04
Defines the 2nd AGC Threshold:
3-0
AgcStep3
rw
0x0b
Defines the 3rd AGC Threshold:
RegAgcThresh3Lf
(0x64)
7-4
AgcStep4
rw
0x0c
Defines the 4th AGC Threshold:
3-0
AgcStep5
rw
0x0c
Defines the 5th AGC Threshold:
RegPllLf
(0x70)
7-6
PllBandwidth
rw
0x03
Controls the PLL bandwidth:
00 Æ 75 kHz
10 Æ 225 kHz
01 Æ 150 kHz
11 Æ 300 kHz
5-0
reserved
rw
0x10
reserved. Retain default value
unused
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RFM95/96/97/98(W)
WIRELESS & SENSING
PRELIMINARY
DATASHEET
Table 88 High Frequency Additional Registers
Name
(Address)
RegAgcRefHf
(0x61)
Bits
Variable Name
Mode
Default
value
7-6
unused
r
-
Low Frequency Additional Registers
unused
Sets the floor reference for all AGC thresholds:
AGC Reference[dBm]=
-174dBm+10*log(2*RxBw)+SNR+AgcReferenceLevel
SNR = 8dB, fixed value
5-0
AgcReferenceLevel
rw
0x1c
RegAgcThresh1Hf
(0x62)
7-5
unused
r
-
4-0
AgcStep1
rw
0x0e
Defines the 1st AGC Threshold
RegAgcThresh2Hf
(0x63)
7-4
AgcStep2
rw
0x05
Defines the 2nd AGC Threshold:
3-0
AgcStep3
rw
0x0b
Defines the 3rd AGC Threshold:
RegAgcThresh3Hf
(0x64)
7-4
AgcStep4
rw
0x0c
Defines the 4th AGC Threshold:
3-0
AgcStep5
rw
0x0c
Defines the 5th AGC Threshold:
RegPllHf
(0x70)
7-6
PllBandwidth
rw
0x03
Controls the PLL bandwidth:
00 Æ 75 kHz
10 Æ 225 kHz
01 Æ 150 kHz
11 Æ 300 kHz
5-0
reserved
rw
0x10
reserved. Retain default value
unused
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Page 101
RFM95/96/97/98(W)
WIRELESS & SENSING
PRELIMINARY
DATASHEET
6.4. LoRaTM Mode Register Map
This section details the RFM95/96/97/98(W) register mapping and the precise contents of each register in LoRaTM
mode.
It is essential to understand that the LoRa modem is controlled independently of the FSK modem. Therefore, care should
be taken when accessing the registers, especially as some register may have the same name in LoRa or FSK mode.
The LoRa registers are only accessible when the device is set in Lora mode (and, in the same way, the FSK register are
only accessible in FSK mode). However, in some cases, it may be necessary to access some of the FSK register while in
LoRa mode. To this aim, the AccesSharedReg bit was created in the RegOpMode register. This bit, when set to ‘1’, will
grant access to the FSK register 0x0D up to the register 0x3F. Once the setup has been done, it is strongly recommended
to clear this bit so that LoRa register can be accessed normally.
Convention: r: read, w: write, c : set to clear and t: trigger.
Name
(Address)
RegFifo
(0x00)
Variable Name
Bits
7-0
Fifo
Mode
Reset
rw
0x00
LoRaTM Description
LoRaTM base-band FIFO data input/output. FIFO is cleared an
not accessible when device is in SLEEP mode
Common Register Settings
0 Æ FSK/OOK Mode
7
RegOpMode
(0x01)
LongRangeMode
rw
0x0
1 Æ LoRaTM Mode
This bit can be modified only in Sleep mode. A write operation on
other device modes is ignored.
6
AccessSharedReg
rw
0x0
This bit operates when device is in Lora mode; if set it allows
access to FSK registers page located in address space
(0x0D:0x3F) while in LoRa mode
0 Æ Access LoRa registers page 0x0D: 0x3F
1 Æ Access FSK registers page (in mode LoRa) 0x0D: 0x3F
5-4
reserved
r
0x00
reserved
3
LowFrequencyModeOn
rw
0x01
Access Low Frequency Mode registers
0 Æ High Frequency Mode (access to HF test registers)
1 Æ Low Frequency Mode (access to LF test registers)
2-0
Mode
rwt
0x01
Device modes
000 Æ SLEEP
001 Æ STDBY
010 Æ Frequency synthesis TX (FSTX)
011 Æ Transmit (TX)
100 Æ Frequency synthesis RX (FSRX)
101 Æ Receive continuous (RXCONTINUOUS)
110 Æ receive single (RXSINGLE)
111 Æ Channel activity detection (CAD)
(0x02)
7-0
reserved
r
0x00
-
(0x03)
7-0
reserved
r
0x00
-
(0x04)
7-0
reserved
rw
0x00
-
(0x05)
7-0
reserved
r
0x00
-
RegFrMsb
(0x06)
7-0
Frf(23:16)
rw
0x6c
MSB of RF carrier frequency
RegFrMid
(0x07)
7-0
Frf(15:8)
rw
0x80
MSB of RF carrier frequency
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Page 102
RFM95/96/97/98(W)
WIRELESS & SENSING
Name
(Address)
Bits
Variable Name
PRELIMINARY
Mode
DATASHEET
LoRaTM Description
Reset
LSB of RF carrier frequency
RegFrLsb
(0x08)
7-0
Frf(7:0)
rwt
· Fr f
(XOS C
----)------------f RF = -----------------19
2
0x00
Resolution is 61.035 Hz if F(XOSC) = 32 MHz. Default value is
0x6c8000 = 434 MHz. Register values must be modified only
when device is in SLEEP or STAND-BY mode.
Registers for RF blocks
RegPaConfig
(0x09)
7
PaSelect
rw
0x00
Selects PA output pin
0 Æ RFO pin. Output power is limited to +14 dBm.
1 Æ PA_BOOST pin. Output power is limited to +20 dBm
6-4
MaxPower
rw
0x04
Select max output power: Pmax=10.8+0.6*MaxPower [dBm]
3-0
OutputPower
rw
0x0f
Pout=Pmax-(15-OutputPower) if PaSelect = 0 (RFO pin)
Pout=17-(15-OutputPower)
if PaSelect = 1 (PA_BOOST pin)
7-5
unused
r
-
unused
4
reserved
rw
0x00
reserved
3-0
PaRamp(3:0)
rw
0x09
Rise/Fall time of ramp up/down in FSK
0000 Æ 3.4 ms
0001 Æ 2 ms
0010 Æ 1 ms
0011 Æ 500 us
0100 Æ 250 us
0101 Æ 125 us
0110 Æ 100 us
0111 Æ 62 us
1000 Æ 50 us
1001 Æ 40 us
1010 Æ 31 us
1011 Æ 25 us
1100 Æ 20 us
1101 Æ 15 us
1110 Æ 12 us
1111 Æ 10 us
7-6
unused
r
0x00
unused
5
OcpOn
rw
0x01
Enables overload current protection (OCP) for PA:
0 Æ OCP disabled
1 Æ OCP enabled
0x0b
Trimming of OCP current:
Imax = 45+5*OcpTrim [mA] if OcpTrim
