LVMDM-45G

LVMDM-45G

  • 厂商:

    RHOMBUS-IND

  • 封装:

  • 描述:

    LVMDM-45G - LVMDM Series LVC Low Voltage Logic Buffered 5-Tap Delay SMD Modules - Rhombus Industries...

  • 详情介绍
  • 数据手册
  • 价格&库存
LVMDM-45G 数据手册
LVMDM Series LVC Low Voltage Logic Buffered 5-Tap Delay SMD Modules Low Profile 8-Pin Package Two Surface Mount Versions Low Voltage CMOS 74LVC Logic Buffered 5 Equal Delay Taps Operating Temp. -40OC to +85OC LVMDM 8-Pin Schematic Vcc 8 Tap1 Tap3 Tap5 7 6 5 Inputs accept voltages up to 5.5 V 74LVC type input can be driven from either 3.3V or 5V devices. This allows delay module to serve as a translator in a mixed 3.3V / 5V system environment. 1 IN 2 3 4 GND Tap2 Tap4 Electrical Specifications at 25OC LVC 5 Tap Tap 1 Tap 2 Tap 3 Tap 4 Tap 5 Tap-to-Tap ( ns ) ( ns ) ( ns ) ( ns ) ( ns ) (ns) SMD P/N LVMDM-7G 3.0 ± 1.0 4.0 ± 1.0 5.0 ± 1.0 6.0 ± 1.0 7 ± 1.0 1.0 ± 0.4 LVMDM-9G 3.0 ± 1.0 4.5 ± 1.0 6.0 ± 1.0 7.5 ± 1.0 9 ± 1.0 1.5 ± 0.5 LVMDM-11G 3.0 ± 1.0 5.0 ± 1.0 7.0 ± 1.0 9.0 ± 1.0 11 ± 1.5 2.0 ± 0.6 LVMDM-13G 3.0 ± 1.0 5.5 ± 1.0 8.0 ± 1.0 10.5 ± 1.0 13 ± 1.5 2.5 ± 0.8 LVMDM-15G 3.0 ± 1.0 6.0 ± 1.0 9.0 ± 1.0 12.0 ± 1.5 15 ± 1.5 3.0 ± 1.0 LVMDM-20G 4.0 ± 1.0 8.0 ± 1.2 12.0 ± 1.5 16.0 ± 1.5 20 ± 2.0 4.0 ± 1.0 LVMDM-25G 5.0 ± 1.0 10.0 ± 1.5 15.0 ± 1.5 20.0 ± 2.0 25 ± 2.0 5.0 ± 1.5 LVMDM-30G 6.0 ± 1.0 12.0 ± 1.5 18.0 ± 1.5 24.0 ± 2.0 30 ± 2.0 6.0 ± 1.5 LVMDM-35G 7.0 ± 1.0 14.0 ± 1.5 21.0 ± 2.0 28.0 ± 2.0 35 ± 2.0 7.0 ± 1.8 LVMDM-40G 8.0 ± 1.0 16.0 ± 1.5 24.0 ± 2.0 32.0 ± 2.0 40 ± 2.0 8.0 ± 2.0 LVMDM-45G 9.0 ± 1.0 18.0 ± 1.5 27.0 ± 2.0 36.0 ± 2.0 45 ± 2.25 9.0 ± 2.0 LVMDM-50G 10.0 ± 1.5 20.0 ± 2.0 30.0 ± 2.0 40.0 ± 2.0 50 ± 2.5 10 ± 2.0 LVMDM-60G 12.0 ± 1.5 24.0 ± 2.0 36.0 ± 2.0 48.0 ± 2.4 60 ± 3.0 12 ± 2.0 LVMDM-75G 15.0 ± 2.0 30.0 ± 2.0 45.0 ± 2.25 60.0 ± 3.0 75 ± 3.75 15 ± 2.5 LVMDM-80G 16.0 ± 2.0 32.0 ± 2.0 48.0 ± 2.4 64.0 ± 3.2 80 ± 4.0 16 ± 2.5 LVMDM-100G 20.0 ± 2.0 40.0 ± 2.0 60.0 ± 3.0 80.0 ± 2.0 100 ± 5.0 20 ± 3.0 ** These part numbers do not have 5 equal taps. Tap-to-Tap Delays reference Tap 1. TEST CONDITIONS -- Low Voltage CMOS, LVC VCC Supply Voltage ................................................ 3.30VDC Input Pulse Voltage ................................................... 2.70V Input Pulse Rise Time ....................................... 3.0 ns max. Input Pulse Width / Period ........................... 1000 / 2000 ns 1. Measurements made at 25OC 2. Delay Times measured at 1.50V level of leading edge. 3. Rise Times measured from 0.75V to 2.40V. 4. 50pf probe and fixture load on output under test. Dimensions in Inches (mm) .505 (12.83) MAX. .285 (7.24) MAX. .020 (0.51) .250 TYP. (6.35) MAX. .120 (3.05) MIN. .020 .050 (0.51) (1.27) TYP. TYP. .100 (2.54) TYP. DIP DIP .010 (0.25) TYP. .300 (7.62) .365 (9.27) MAX. OPERATING SPECIFICATIONS Supply Voltage, VCC .......................................... 3.3 ± 0.3 VDC Supply Current, ICC ........................... 10 mA typ., 30 mA max. Supply Current, ICCL : VIN = GND ......................... 22 mA max. Supply Current, ICCH : VIN = VCC ............................. 10 µA max. Input Voltage, VI ..................................... 0 V min., 5.5 V max. Logic “1” Input, VIH .................................................. 2.0 V min. Logic “0” Input, VIL ................................................. 0.8 V max. Logic “1” Out, VOH: VCC = 3V & IOH = -24 mA ............ 2.0 V min. Logic “0” Out, VOL: VCC = 3V & IOL = 24 mA ......... 0.55 V max. Input Capacitance, CI ............................................. 5 pF, typ. Input Pulse Width, PWI .............................. 40% of Delay min. Operating Temperature Range ......................... -40O to +85OC Storage Temperature Range ........................ -65O to +150OC .505 (12.83) MAX. .285 (7.24) MAX. .250 (6.35) MAX. .015 (0.38) TYP. G-SMD G-SMD .030 (0.76) TYP. .430 (10.92) .400 (10.16) .285 (7.24) MAX. .008 R (0.20) .010 (0.25) TYP. .020 .050 (0.51) (1.27) TYP. TYP. .100 (2.54) TYP. P/N Description LVMDM - XXX X .505 (12.83) MAX. LVC Buffered 5 Tap Delay Molded Package Series: 8-pin DIP: LVMDM Total Delay in nanoseconds (ns) Lead Style: Blank = Thru-hole G = “Gull Wing” SMD J = “J” Bend SMD Examples: LVMDM-25G = 25ns (5ns per tap) 74LVC, 8-Pin G-SMD LVMDM-100 = 100ns (20ns per tap) 74LVC, 8-Pin DIP J-SMD .265 (6.73) MAX. .030 (0.76) TYP. J-SMD .285 (7.24) .260 (6.60) .330 (8.38) MAX. .020 R (0.51) .020 .050 (0.51) (1.27) TYP. TYP. .100 (2.54) TYP. 6SHFLILFDWLRQV VXEMHFW WR FKDQJH ZLWKRXW QRWLFH www.rhombus-ind.com UKRPEXV LQGXVWULHV LQF )RU RWKHU YDOXHV &XVWRP 'HVLJQV FRQWDFW IDFWRU\ sales@rhombus-ind.com 18 TEL: (714) 898-0960 FAX: (714) 896-0971 LVMDM 2001-01
LVMDM-45G
1. 物料型号: - 型号列表包括LVMD-7G、LVMD-9G、LVMD-11G、LVMD-13G、LVMD-15G、LVMD-20G、LVMD-25G、LVMD-30G、LVMD-35G、LVMD-40G、LVMD-45G、LVMD-50G、LVMD-60G、LVMD-75G、LVMD-80G、LVMD-100G等。

2. 器件简介: - LVMDM系列是低压CMOS 74LVC逻辑缓冲5分延迟SMD模块,具有8引脚封装、两种表面贴装版本,操作温度范围为-40°C至+85°C。

3. 引脚分配: - 8引脚SMD封装图提供了各引脚的分配,但具体引脚图未在文本中给出。

4. 参数特性: - 包括5个相等延迟的分接点,延迟时间从3.0ns至100ns不等,具体值因型号而异。 - 每个型号的分接点延迟时间(Tap 1至Tap 5)以及分接点之间的延迟差异(Tap-to-Tap)也有所列出。

5. 功能详解: - LVMDM系列模块可以接受高达5.5V的输入电压,74LVC型输入可以从3.3V或5V设备驱动,可用于3.3V/5V混合系统环境。

6. 应用信息: - 该模块可以作为不同电压系统间的翻译器使用。

7. 封装信息: - 提供了8引脚DIP和8引脚SMD两种封装选项。 - 封装风格包括直插(Thru-hole)、“海鸥翼”SMD(Gull Wing)和“J”弯SMD(J Bend)。
LVMDM-45G 价格&库存

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