R7779AGS

R7779 Burst Triple-Mode PWM Controller with Integrated HV Start-up Device for Zero Power Monitor Application General Description Features The R7779 is a high-performance current mode PWM controller with integrated HV start-up device inside. During start-up, a current source through integrated HV device to charge VDD capacitor for quick start-up while it dissipates no loss in normal operation. l The R7779 provides the users a superior AC/DC power application of higher efficiency, low external component counts, and low cost solution. It features frequency jitter, Under Voltage LockOut (UVLO), Leading Edge Blanking (LEB), internal slope compensation in the tiny SOP-8 package. It offers complete protection coverage with Over Temperature Protection (OTP), Over Load Protection (OLP) and Over Voltage Protection (OVP). l l l l l l l l l l l l l Moreover, it also provides a special interface for zero power application when the converter is in sleeping mode. EN/ DIS pin receives ON/OFF signal from secondary scalar controller. During turning off, the controller will be shutdown completely with pretty low power consumption. l l Integrated HV Start-up Device UVLO : 9V/16.5V Current Mode Control Built-in 65kHz Operation Frequency Jittering Frequency Internal PWM Leading Edge Blanking Internal Slope Compensation Compensated Burst Triple-Mode PWM Cycle-by-Cycle Current Limit Internal Auto Recovery OVP Internal Auto Recovery OLP Internal Auto Recovery OTP Secondary Rectifier Short Protection Soft Driving for Reducing EMI Noise High Noise Immunity RoHS Compliant and Halogen Free Applications l l Switching AC/DC Adaptor and Battery Charger TV and Monitor Application Typical Application Circuit VO+ AC Mains (90V to 265V) VO- R7779 EN/DIS HV VDD OPTO1 COMP # LDO # GATE GND CS OPTO2 OPTO1 GPIO Scalar # See Application Information OPTO2 R7779-04 July 2009 1 R7779 Ordering Information R7779 Package Type S : SOP-8 Operating Temperature Range G : Green (Halogen Free with Commercial Standard) Note : Richpower Green products are : } RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. } Suitable for use in SnPb or Pb-free soldering processes. Marking Information For marking information, contact our sales representative directly or through a Richpower distributor located in your area, otherwise visit our website for detail. Pin Configurations (TOP VIEW) EN/DIS 8 HV COMP 2 7 NC CS GND 3 6 VDD 4 5 GATE SOP-8 Functional Pin Description Pin No. 1 2 Pin Name EN/DIS Enable function pin. Pin Function Voltage feedback pin. By connecting a opto-coupler to close control loop and 2 COMP 3 CS Current sensing pin. 4 GND Ground. 5 GATE Gate drive output to drive the external MOSFET. 6 VDD Power supply pin. 7 8 NC HV No connection. 500V high voltage device for start-up. achieve the regulation. R7779-04 July 2009 R7779 Function Block Diagram HV 8 EN/DIS 1 6 VDD OVP Secondary Rectifier Short Protection - - 1.7V + Shutdown Logic + UVLO + - Brownout Sensing Bias & Bandgap COMP Open Sensing Oscillator SS Constant Power Dmax Soft Driver S COMP 2 Slope Ramp CS 3 R7779-04 July 2009 9/16.5V Counter OLP LEB 27V POR OTP X3 + PWM Comparator 5 GATE Q R COMP Burst Triple Mode& TP Compensation VBURH VBURL VDD 3 R7779 Absolute Maximum Ratings l l l l l l l l l l (Note 1) HV Pin ----------------------------------------------------------------------------------------------------------------Supply Input Voltage, VDD ----------------------------------------------------------------------------------------GATE Pin -------------------------------------------------------------------------------------------------------------EN/DIS, COMP, CS Pin -------------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C SOP-8 -----------------------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2) SOP-8, θJA -----------------------------------------------------------------------------------------------------------Junction Temperature ----------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------Storage Temperature Range --------------------------------------------------------------------------------------ESD Susceptibility (Note 3) HBM (Human Body Mode) ----------------------------------------------------------------------------------------MM (Machine Mode) ------------------------------------------------------------------------------------------------ Recommended Operating Conditions l l −0.3V to 500V −0.3V to 30V −0.3V to 20V −0.3V to 6.5V 0.4W 160°C/W 150°C 260°C −65°C to 150°C 4kV 200V (Note 4) Supply Input Voltage, VDD ----------------------------------------------------------------------------------------- 12V to 25V Ambient Temperature Range -------------------------------------------------------------------------------------- −40°C to 85°C Electrical Characteristics (VDD = 15V, TA = 25°C, unless otherwise specified) Parameter Symbol Conditions Min Typ Max Unit VDD < VTH_ON ,HV = 500V 1 -- -- mA VDD = VTH_OFF, HV = 500V -- -- 25 µA HV Section HV start up current IJEFT_ST Off State Leakage Current VDD Section On Threshold Voltage V TH_ON 15.5 16.5 17.5 V Off Threshold Voltage V TH_OFF 8 9 10 V V DD Zener Clamp VZ 29 -- -- V Operating Current IDD_OP VDD = 15V, 65kHz COMP pin, GATE pin open -- 550 1000 µA VDD Holdup Mode End Point V DD_HYS VCOMP < 1.6V -- 10.5 -- V VDD Holdup Mode Entry Point V DD_LOW VCOMP < 1.6V -- 10 -- V V DD Over Voltage Protection Level V OVP 25.5 27 28.5 V To be continued 4 R7779-04 July 2009 R7779 Parameter Symbol Conditions Min Typ Max Unit Oscillator Section Normal PWM Frequency fOSC 60 65 70 kHz Maximum Duty Cycle DCYMAX 70 75 80 % PWM Frequency Jitter Range △f -- ±7 -- % PWM Frequency Jitter Period TJIT For 65kHz -- 4 -- ms Frequency Variation Versus V DD Deviation fDV VDD = 12V to 25V -- -- 2 % Frequency Variation Versus Temp. Deviation fDT TA = -30°C to 105°C -- -- 5 % COMP Input Section Open Loop Voltage VCOMP_OP COMP pin open 5.5 5.75 6 V COMP Open 56ms Protection VCOMP_56 5.25 -- -- V COMP Open-loop Protection Delay Time T OLP -- 56 -- ms Short Circuit COMP Current IZERO -- 1.3 2.5 mA 0.72 0.75 0.78 V VCOMP = 0V Current-Sense Section Initial Current Limit Offset VCSTH Leading Edge Blanking Time T LEB (Note 5) 150 250 350 ns Internal Propagation Delay Time TPD (Note 5) -- 100 -- ns Minimum On Time T ON_MIN 250 350 450 ns GATE Section Gate Output Clamping Voltage VCLAMP VDD = 25V -- 14 -- V Rising Time TR VDD = 15V, CL = 1nF -- 125 -- ns Falling Time TF VDD = 15V, CL = 1nF -- 45 -- ns 0.8 1 1.2 V -- -- 30 µA EN/DIS Interface Section Enable Threshold VEN_TH EN/DIS Pin Max Clamping Current Note 1. Stresses beyond those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note 2. θJA is measured in the natural convection at TA = 25°C on a low effective single layer thermal conductivity test board of JEDEC 51-3 thermal measurement standard. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. Leading edge blanking time and internal propagation delay time are guaranteed by design. R7779-04 July 2009 5 R7779 Typical Operating Characteristics VTH_ON vs. Temperature 18.0 9.6 17.6 VTH_ON (V) VTH_OFF (V) VTH_OFF vs. Temperature 10.0 9.2 8.8 8.4 17.2 16.8 16.4 8.0 16.0 -50 0 50 100 150 -50 0 20.0 66.0 16.0 VCLAMP (V) 68.0 64.0 62.0 12.0 8.0 0.0 58.0 -50 0 50 100 8 150 10 12 14 16 18 20 22 24 26 VDD (V) Temperature (°C) Oscillation Frequency (fOSC) vs. VDD Operating Current (IDD_OP) vs. VDD 1000.0 70.0 800.0 68.0 f OSC (kHz) IDD_OP (µA) 150 4.0 60.0 600.0 400.0 200.0 66.0 64.0 62.0 0.0 60.0 8 10 12 14 16 18 VDD (V) 6 100 Gate Output Clamp Voltage (VCLAMP) vs. VDD Oscillation Frequency (fOSC) vs. Temperature f OSC (kHz) 50 Temperature (°C) Temperature (°C) 20 22 24 26 8 10 12 14 16 18 20 22 24 26 VDD (V) R7779-04 July 2009 R7779 Comp Short Current (IZERO) vs. Temperature Gate Output Clamp Voltage (VCLAMP) vs. Temperature 20.0 2.0 18.0 I ZERO (mA) VCLAMP (V) 1.6 16.0 14.0 12.0 1.2 0.8 0.4 0.0 10.0 -50 0 50 100 -50 150 0 100 150 Over Voltage Protection Level (VOVP) vs. Temperature 6.5 30.0 6.1 29.0 VOVP (V) VCOMP_OP (V) Comp Open Voltage (VCOMP_OP) vs. Temperature 5.7 5.3 4.9 28.0 27.0 26.0 4.5 25.0 -50 0 50 100 150 -50 0 50 100 150 Temperature (°C) Temperature (°C) Initial Current Limit Offset (VCSTH) vs. Temperature Operating Supply Current (IDD_OP) vs. Temperature 0.77 1000 800 IDD_OP (µA) 0.76 VCSTH (V) 50 Temperature (°C) Temperature (°C) 0.75 0.74 600 400 200 0 0.73 -50 0 50 Temperature (°C) R7779-04 July 2009 100 150 -50 0 50 100 150 Temperature (°C) 7 R7779 HV Startup Current vs. Temperature Enable Threshold Voltage (VEN_TH) vs. Temperature 3 2.5 1.8 I JFET_ST (mA) Enable Threshold Voltage (V) 2.4 1.2 2 1.5 1 0.6 0.5 0 0.0 -50 0 50 100 -50 150 0 50 100 150 Temperature (°C) Temperature (°C) DMAX vs. Temperature Startup Current vs. Temperature 80 40 78 DMAX (%) I DD_ST (µA) 30 20 10 74 72 70 0 -50 0 50 100 Temperature (°C) 8 76 150 -50 0 50 100 150 Temperature (°C) R7779-04 July 2009 R7779 Application Information gets light, the feedback signal drops and touches VBURL. Clock signal will be blanked and system ceases switching. After VOUT drops and feedback signal goes back to VBURH, the system will restart switching again. The burst mode entry points of high and low line are compensated to reduce audio noise at high line and get better efficiency at low line. This kind of operation, shown in the timing diagram of Figure 1. The R7779 is specially designed for advanced monitor application. The proprietary ON/OFF control pin completely shuts down the controller after receiving downstream scalar signal from secondary side. (It achieves almost zero power under sleeping mode.) HV Start-up Device An in-house design 500V start-up device is integrated in the controller to further minimize loss and enhance performance. The HV start-up device will be turned on during start-up and be pulled low during normal operation. It guarantees fast start-up time and no power loss in this path after start-up. Burst Triple Mode The R7779 applies Burst Triple Mode for light load operation, because it's reliable, simple and has no patent infringement issues. Refer to Figure 1 for details. l PWM Mode : For most of load condition, the circuit will run at traditional PWM current mode. l Burst Mode : During light load, switching loss will dominate the power efficiency calculation. This mode can reduce the switching loss. When the output load Normal Operation Light Load l VDD Holdup Mode : When VDD drops down to VDD turn off threshold voltage ,the system will be shut down. During shutdown period , controller does nothing to any load change and might cause VOUT down. To avoid this, when VDD drops to a setting threshold, 10V, the hysteresis comparator will bypass PWM and burst mode loop and force switching at a very low level to supply energy to VDD pin. VDD holdup mode is also improved to holdup VDD by less switching cycles. This mode is very useful in reducing start-up resistor loss while still getting start up time in spec.. It's not likely for VDD to touch UVLO turn off threshold during any light load condition. This will also makes bias winding design easier. No Load (VDD Holdup Mode) Load VDD VDD_HIGH VDD_LOW VCOMP VBURH VBURL VGATE Figure 1. Burst Triple-Mode R7779-04 July 2009 9 R7779 Oscillator 20µs. The internal bias current of EN/DIS is 2µA. For low To guarantee precise frequency , it is trimmed to 7% power consumption, it's a high impedance pin. Therefore, tolerance. It also generates slope compensation saw-tooth, 75% maximum duty cycle pulse and overload protection slope. It can typically operate at built-in 65kHz center frequency and feature frequency jittering function. Its jittering depth is 7% with about 4ms envelope frequency at 65kHz. proper layout is necessary for noise immunity. If capacitor is unavoidable, capacitor value should be carefully calculated and not to influence system operation. Gate Driver A totem pole gate driver is fine tuned to meet both EMI and efficiency requirement in low power application . An internal pull low circuit is activated after pretty low VDD to prevent external MOSFET from accidental turning-on during UVLO. #Typical application circuits are suggested adding resistance least 10Ω between GATE pin and MOSFET. Protection The R7779 provides fruitful protection functions that intend to protect system from being damaged. All the protection functions can be listed as below. l Cycle-by-Cycle Current Limit : This is a basic but very useful function and it can be implemented easily in current mode controller. l Over Load Protection : Long time cycle-by-cycle current limit will lead to system thermal stress. To further protect system, system will be shut down after about 56ms (3840 clock cycles) in 67kHz operation. After shutdown, system will resume and behave as hiccup. Through our proprietary prolong turn off period as hiccup, the power loss and thermal during OLP will be averaged to an acceptable level over the ON/OFF cycle of the IC. This will last until fault is removed. Tight Current Limit Tolerance Generally, the saw current limit is applied to low cost flyback controller because of simple design. However, saw current limit is hard to test in mass production. Therefore, it's generally "guarantee by design". The variation of process and package will make its tolerance wider. It will leads to 20% to 30% variation when doing OLP test at certain line voltage.This will cause yield loss in power supply mass protection. Through well foundry control, design and test/trim mode in final test, the R7779 current limit tolerance is tight enough to make design easier. # It's highly recommended to add a resistor in parallel with opto-coupler. To provide sufficient bias current to make TL-431 regulate properly, 1.2kΩ resistor is suggested. l EN/DIS pin The R7779 features an enable/disable circuit. If the voltage on the EN/DIS pin is greater than enable threshold voltage or EN/DIS pin is floating, the controller is enabled and switching will occur. If the voltage on the EN/DIS pin falls below enable threshold voltage, the controller will be shut down and consume almost zero power. When the voltage of EN/DIS pin exceeds 1.2V or EN/DIS pin is floating, the system will be start-up. When the voltage of EN/DIS pin falls below 0.8V, the system will be shut down. For low standby power application, it's important to make current in this path as small as possible. The deglitch delay time of the disable function is about 10 l OVP : Output voltage can be roughly sensed by VDD pin. If the sensed voltage reaches 27V threshold, system will be shut down after 20µs deglitch delay. This will last until fault is removed. OTP : Internal 110/140°C hysteresis comparator will provide Over Temperature Protection (OTP) for controller itself. It's not suggested to use the function as precise OTP. OTP will not shut down system. It stops the system from switching until the temperature is under 110°C. Meanwhile, if VDD touches VDD turn off threshold voltage, system will hiccup. l Feedback Open and Opto Short : This will trigger OVP or 56ms delay protection. It depends on which one occurs first. l CS Pin Open Protection : When CS pin is opened, the system will be shut down and into auto recovery R7779-04 July 2009 R7779 after couples of cycle. It could pass CS pin open test easier. l Secondary Rectifier Short Protection : As shown in Figure 2. The current spike during secondary rectifier short test is extremely high because of the saturated main transformer. Meanwhile, the transformer acts like a leakage inductance. During high line, the current in power FET is sometimes too high to wait for a 56ms OLP delay time. To offer better and easier protection design, the R7779 shuts down the controller after couples of cycles before fuse is blown up. Secondary Rectifier Short VDD V COMP V CS Figure 2. Secondary Rectifier Short Protection R7779-04 July 2009 11 R7779 PCB Layout Guide A proper PCB layout can abate unknown noise interference It is good for reducing noise, output ripple and EMI issue and EMI issue in the switching power supply. Please refer to the guidelines when you want to design PCB layout for switching power supply: to separate ground traces of bulk capacitor(a),MOSFET(b), auxiliary winding(c) and IC control circuit (d). Finally, connect them together on bulk capacitor ground(a). The areas of these ground traces should be kept large. The current path (1) from bulk capacitor, transformer, MOSFET, Rcs return to bulk capacitor is a huge high frequency current loop. It must be as short as possible to decrease noise coupling and kept a space to other low voltage traces, such as IC control circuit paths, especially. Besides, the path(2) from RCD snubber circuit to MOSFET is also a high switching loop, too. So keep it as small as possible. Furthermore, the path (3) from bulk capacitor to HV pin is a high voltage loop. It is highly recommended that EN/DIS control paths will be kept as far as possible from path (1), path (2) and path (3). Placing byass capacitor for abating noise on IC is highly recommended. The bypass capacitor should be placed as close to controller as possible. To minimize reflected trace inductance and EMI minimize the area of the loop connecting the secondary winding, the output diode, and the output filter capacitor. In addition, apply sufficient copper area at the anode and cathode terminal of the diode for heatsinking. Apply a larger area at the quiet cathode terminal. A large anode area can increase high-frequency radiated EMI. CBULK AC Mains (90V to 265V) (a) (3) (2) CBULK Ground (a) R7779 HV EN/DIS VDD Trace Trace Trace COMP (c) GATE GND IC Ground (d) Auxiliary Ground (c) MOSFET Ground (b) CS (1) (b) (d) 12 R7779-04 July 2009 R7779 Outline Dimension H A M J B F C I D Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 4.801 5.004 0.189 0.197 B 3.810 3.988 0.150 0.157 C 1.346 1.753 0.053 0.069 D 0.330 0.508 0.013 0.020 F 1.194 1.346 0.047 0.053 H 0.170 0.254 0.007 0.010 I 0.050 0.254 0.002 0.010 J 5.791 6.200 0.228 0.244 M 0.400 1.270 0.016 0.050 8-Lead SOP Plastic Package RICHPOWER MICROELECTRONICS CORP. RICHPOWER MICROELECTRONICS CORP. Headquarter Taipei Office (Marketing) Room 2102, 1077 ZuChongZhi Road, Zhang Jiang Hi-TechPark, Pudong New Area, Shanghai, China 8F, No. 137, Lane 235, Paochiao Road, Hsintien City Tel: (8621)50277077 Fax: (8621)50276966 Tel: (8862)89191466 Fax: (8862)89191465 Taipei County, Taiwan, R.O.C. Email: marketing@richpower.com Information that is provided by Richpower Technology Corporation is believed to be accurate and reliable. Richpower reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richpower products into any application. No legal responsibility for any said applications is assumed by Richpower. R7779-04 July 2009 13