®
R7780A
Burst Triple Mode PWM Controller with Integrated HV
Start-up Device for Zero Power Monitor Application
General Description
Features
The R7780A is a high-performance current mode PWM
controller with integrated HV start-up device inside. During
Integrated HV Start-up Device
start-up, a current source through integrated HV device to
Current Mode Control
charge VDD capacitor for quick start-up while it dissipates
no loss in normal operation.
Built-in 65kHz Operation Frequency
Built-in Jittering Frequency
The R7780A provides users a superior AC/DC power
application of higher efficiency, few external component
Internal PWM Leading Edge Blanking
Internal Slope Compensation
count, and low cost solution. It features frequency jitter,
Under Voltage LockOut (UVLO), Leading Edge Blanking
Compensated Burst Triple Mode PWM
Cycle-by-Cycle Current Limit
(LEB), internal slope compensation in the tiny SOP-7
Internal Auto Recovery OVP
package, and offers complete protection coverage with Over
Temperature Protection (OTP), Over Load Protection (OLP)
Internal Auto Recovery OLP
Internal Auto Recovery OTP
and Over Voltage Protection (OVP).
CS Pin Open Protection
Secondary Rectifier Short Protection
Ordering Information
Soft Driving for Reducing EMI Noise
R7780A
Package Type
S : SOP-7
N : DIP-8
Lead Plating System
G : Green (Halogen Free and Pb Free)
Note :
UVLO: 9V/16.5V
High Noise Immunity
RoHS Compliant and Halogen Free
Applications
Switching AC/DC Adaptor
TV and Monitor Application
Low Standby Power Home Appliance
Richtek products are :
RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.
Pin Configurations
(TOP VIEW)
Suitable for use in SnPb or Pb-free soldering processes.
NC
Marking Information
R7780AGS
HV
3
6
VDD
4
5
GATE
2
CS
GND
R7780AGS : Product Number
R7780A
GSYMDNN
7
COMP
SOP-7
YMDNN : Date Code
HV
NC
VDD GATE
8
7
6
5
2
3
4
R7780AGN
RichTek
R7780A
GNYMDNN
R7780AGN : Product Number
YMDNN : Date Code
NC COMP CS GND
DIP-8
Copyright ©2014 Richtek Technology Corporation. All rights reserved.
R7780A-01 August 2014
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1
R7780A
Typical Application Circuit
VO+
AC Mains
(90V to 265V)
#
VOR7780A
HV
#
VDD
LDO
OPTO1
COMP
#
GATE
GND
CS
OPTO1
# See Application Information
GPIO
Scalar
OPTO2
Functional Pin Description
Pin No.
SOP-7
DIP-8
1
1, 7
2
Pin Name
Pin Description
NC
No Internal Connection.
2
COMP
Voltage Feedback. By connecting an opto-coupler to close control loop and
achieve the regulation.
3
3
CS
Current Sense Input.
4
4
GND
Ground.
5
5
GATE
Gate Driver Output. Connect a resistor from this pin to the external power
MOSFET.
6
6
VDD
Power Supply Input.
7
8
HV
700V High Voltage Input Pin for Start-up.
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is a registered trademark of Richtek Technology Corporation.
R7780A-01 August 2014
R7780A
Function Block Diagram
HV
VDD
OVP
Secondary Rectifier Short Protection
& CS Open Protection
2.6V Shutdown
+
Logic
+
-
UVLO
+
-
Brownout
Sensing
Counter
OLP
Oscillator
SS
Dmax
Soft
Driver
S
COMP
Slope
Ramp
CS
LEB
X3
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
R7780A-01 August 2014
9/16.5V
Bias &
Bandgap
COMP Open
Sensing
Constant
Power
28V
POR
OTP
+
PWM
Comparator
Q
GATE
R
Burst Triple
Mode& TP
Compensation
COMP
VBURH
VBURL
VDD
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3
R7780A
Absolute Maximum Ratings
(Note 1)
HV ----------------------------------------------------------------------------------------------------------------------------- n0.3V to 700V
Supply Input Voltage, VDD ---------------------------------------------------------------------------------------------- n0.3V to 30V
GATE ------------------------------------------------------------------------------------------------------------------------- n0.3V to 20V
COMP, CS ------------------------------------------------------------------------------------------------------------------ n0.3V to 6.5V
Power Dissipation, PD @ TA = 25C
SOP-7 ------------------------------------------------------------------------------------------------------------------------ 0.36W
DIP-8 ------------------------------------------------------------------------------------------------------------------------- TBD
Package Thermal Resistance (Note 2)
SOP-7,
DIP-8,
JA
------------------------------------------------------------------------------------------------------------------ 276.5C/W
JA --------------------------------------------------------------------------------------------------------------------
TBD
Junction Temperature ----------------------------------------------------------------------------------------------------- 150C
Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------- 260C
Storage Temperature Range -------------------------------------------------------------------------------------------- n65C to 150C
ESD Susceptibility (Note 3)
Human Body Model (Except HV pin) --------------------------------------------------------------------------------- 6kV
Machine Model ------------------------------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions
(Note 4)
Supply Input Voltage, VDD ---------------------------------------------------------------------------------------------- 12V to 25V
Junction Temperature Range -------------------------------------------------------------------------------------------- n40C to 125C
Ambient Temperature Range -------------------------------------------------------------------------------------------- n40C to 85C
Electrical Characteristics
(VDD = 15V, TA = 25C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
VDD < VTH ON , HV = 500V
1
--
--
mA
VDD = VTH_OFF, HV = 500V
--
--
25
A
15.5
16.5
17.5
V
HV Section
HV Start-up Current
I JEFT_ST
Off State Leakage Current
VDD Section
On Threshold Voltage
VTH ON
Off Threshold Voltage
VTH_OFF
8
9
10
V
VDD Zener Clamp Voltage
VZ
30
--
--
V
Operating Current
I DD_OP
VDD = 15V, 65kHz
COMP pin , GATE pin open
--
400
700
A
VDD Holdup Mode End Point
VDD_HIGH
VCOMP < 1.6V
--
10.5
--
V
VDD Holdup Mode Entry Point
VDD_LOW
VCOMP < 1.6V
--
10
--
V
VDD Over Voltage Protection Level
VOVP
27
28
29
V
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R7780A-01 August 2014
R7780A
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Oscillator Section
Normal PWM Frequency
fOSC
60
65
70
kHz
Maximum Duty Cycle
DMAX
70
75
80
%
PWM Frequency Jitter Range
f
--
7
--
%
PWM Frequency Jitter Period
T JIT
For 65kHz
--
4
--
ms
Frequency Variation Versus V DD
f DV
VDD = 12V to 25V
--
--
2
%
Frequency Variation Versus
Temperature
f DT
TA = 30°C to 105°C (Note 5)
--
--
5
%
Open-Loop Voltage
VCOMP_OP
COMP pin open
5.5
5.75
6
V
COMP Open 56ms Protection
VCOMP_56
5.25
--
--
V
COMP Open-Loop Protection
Delay Time
tOLP
--
56
--
ms
Short Circuit COMP Current
IZERO
--
272
400
A
COMP Input Section
VCOMP = 0V
Current-Sense Section
Initial Current Limit Offset
VCSTH
0.62
0.65
0.68
V
Maximum Current Limit
VCS(MAX)
(Note 5)
0.67
0.77
0.87
V
Leading Edge Blanking Time
tLEB
(Note 6)
150
250
350
ns
Internal Propagation Delay Time
tPD
(Note 6)
--
100
--
ns
Minimum On Time
tON (MIN)
250
350
450
ns
GATE Section
Gate Output Clamping Voltage
VCLAMP
VDD = 25V
--
14
--
V
Rising Time
tR
CL = 1nF
--
125
--
ns
Falling Time
tF
CL = 1nF
--
45
--
ns
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2.
JA
is measured in natural convection (still air) at TA = 25C with the component mounted on a low effective single layer
thermal conductivity test board of JEDEC 51-3 thermal measurement standard.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. Guaranteed by design.
Note 6. Leading edge blanking time and internal propagation delay time are guaranteed by design.
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
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5
R7780A
Typical Operating Characteristics
Start-up Current (IDD_ST) vs. Temperature
HV Start-up Current (IJFET_ST) vs. Temperature
4.0
50
40
3.0
30
2.0
20
1.0
10
0
0.0
-40
0
40
80
-40
120
0
40
80
120
Temperature (C)
Temperature (C)
On Threshold Voltage (VTH_ON ) vs. Temperature
Off Threshold Voltage (VTH_OFF) vs. Temperature
18.0
10.0
17.6
9.6
17.2
9.2
16.8
8.8
16.4
8.4
16.0
8.0
-40
0
40
80
120
-40
0
40
80
120
Temperature (C)
Temperature (C)
Normal PWM Frequency (fOSC) vs. Temperature
Normal PWM Frequency (fOSC) vs. VDD
68
68
66
66
64
64
62
62
60
60
58
58
-40
0
40
80
Temperature (C)
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6
120
10
15
20
25
VDD (V)
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R7780A-01 August 2014
R7780A
Gate Output Clamping Voltage (VCLAMP) vs. Temperature
Gate Output Clamping Voltage (VCLAMP) vs. VDD
20
20
18
16
16
12
14
8
12
4
10
0
-40
0
40
80
10
120
15
Temperature (C)
20
25
VDD (V)
Operating Supply Current (IDD_OP) vs. Temperature
Operating Supply Current (IDD_OP) vs. VDD
1000
1000
800
800
600
600
400
400
200
200
0
0
-40
0
40
80
120
10
12.5
15
Temperature (°C)
17.5
20
22.5
25
VDD (V)
Open-Loop Voltage (VCOMP_OP) vs. Temperature
Short Circuit COMP Current (IZERO) vs. Temperature
0.5
6.3
0.4
6.0
0.3
5.7
0.2
5.4
0.1
0.0
5.1
-40
0
40
80
Temperature (C)
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
R7780A-01 August 2014
120
-40
0
40
80
120
Temperature (C)
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7
R7780A
Initial Current Limiting Offset (VCS_TH) vs.
Temperature
0.68
VDD Over Voltage Protection Level (VOVP) vs.
Temperature
31
0.67
30
0.66
29
0.65
28
0.64
27
0.63
0.62
26
-50
-25
0
25
50
75
100
125
-40
0
40
80
120
Temperature (C)
Temperature (°C)
Maximum Duty Cycle (DCYMAX) vs. Temperature
80
78
76
74
72
70
-40
0
40
80
120
Temperature (C)
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R7780A-01 August 2014
R7780A
Application Information
HV Start-up Device
will be blanked and system ceases switching. After VOUT
An in-house design 700V start-up device is integrated in
drops and feedback signal goes back to VBURH, the
system will restart switching again. The burst mode
the controller to further minimize loss and enhance
performance. The HV start-up device will be turned on
entry points of high and low line are compensated to
during start-up and be pulled low during normal operation.
reduce audio noise at high line and get better efficiency
It guarantees fast start-up time and no power loss in this
at low line. This kind of operation, is shown in the timing
path after start-up.
diagram of Figure 1.
#
VDD Holdup Mode
A 10k resistor is recommended to be connected in
series with HV pin.
Under light load or load transient moment, feedback
signal will drop and touch VBURL. Then PWM signal will
Burst Triple Mode
The R7780A applies Burst Triple Mode for light load
operation, because it's reliable, simple and no patent
infringement issues. Refer to Figure 1 for details.
PWM Mode
be blanked and system ceases to switch. VDD could
drop down to turn off threshold voltage. To avoid this,
when VDD drops to a setting threshold, 10V, the
hysteresis comparator will bypass PWM and burst mode
For most of load, the circuit will run at traditional PWM
loop and force switching at a very low level to supply
energy to VDD pin. VDD holdup mode is also improved
current mode.
to hold up VDD by less switching cycles. It is not likely
#
for VDD to touch UVLO turn off threshold during any light
It's highly recommended to add a resistor in parallel
with the photo-coupler. To provide sufficient bias current
to make TL-431 regulate properly, a 1.2k
resistor is
load condition. This will also makes bias winding design
and transient design easier.
Furthermore, VDD holdup mode is only designed to
prevent VDD from touching turn off threshold voltage under
suggested.
Burst Mode
light load or load transient moment. Relative to burst
During light load, switching loss will dominate the power
mode, switching loss will increase on the system at
efficiency calculation. This mode can reduce the
switching loss. When the output load gets light, the
VDD holdup mode, so it is highly recommended that
feedback signal drops and touches VBURL. Clock signal
Light
Load
Normal
Operation
the system should avoid operating at this mode during
light load or no load condition, normally.
No Load
(VDD Holdup Mode)
Load
VDD
VDD_HIGH
VDD_LOW
VCOMP
VBURH
VBURL
VGATE
Figure 1. Burst Triple Mode
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9
R7780A
Oscillator
be shut down after about 56ms. After shutdown, system
To guarantee precise frequency, it is trimmed to 5%
will resume and behave as hiccup mode operation.
Through our proprietary prolong turn off period in hiccup
tolerance. It also generates slope compensation saw-tooth,
slope. It typically operates at built-in 65kHz center
mode, the power loss and thermal during OLP will be
averaged to an acceptable level over the ON/OFF cycle
frequency and features frequency jittering function. Its
of the IC. This will last until fault is removed.
jittering depth is 7% with about 4ms envelope frequency
Over Voltage Protection
75% maximum duty cycle pulse and overload protection
at 65kHz.
Gate Driver
Output voltage can be roughly sensed by VDD pin. If
the sensed voltage reaches 28V threshold, system will
be shut down after 20s deglitch delay. This will last
A totem pole gate driver is fine tuned to meet both EMI
and efficiency requirement in low power application. An
until fault is removed.
internal pull low circuit is activated after pretty low VDD to
Over Temperature Protection
prevent external MOSFET from accidental turning-on
Internal 110/140C hysteresis comparator provides Over
during UVLO.
#
Temperature Protection (OTP) for controller. It is not
suggested to use the function as precise OTP. When
drive loop.
the junction temperature exceeds 140C, the R7780A
stops switching until the temperature is under 110C.
Typical application circuits are suggested adding at least
10 GATE pin resistor to alleviate ringing spike of gate
Meanwhile , if VDD touches VDD turn off threshold voltage,
Tight Current Limit Tolerance
system will operate in hiccup mode.
Generally, the saw current limit is applied to low cost
Feedback Open and Opto short
flyback controller because of simple design. However, saw
current limit is hard to test in mass production. Therefore,
it's generally "guarantee by design". The variation of
process and package will make its tolerance wider. It will
leads to 20% to 30% variation when doing OLP test at
This will trigger OVP or 56ms delay protection. It
depends on which one occurs first.
CS Pin Open Protection
certain line voltage. This will cause yield loss in power
When CS pin is opened, the system will be shut down
and into auto recovery after couples of cycles. It could
supply mass production. Through well foundry control,
pass CS pin open test easier.
design and test/trim mode in final test, the R7780A current
limit tolerance is tight enough to make design and mass
Secondary Rectifier Short Protection
production easier.
As shown in Figure 2. The current spike during
secondary rectifier short test is extremely high because
Protection
of saturated main transformer. Meanwhile, the
The R7780A provides complete protection functions that
transformer acts like a leakage inductance. During high
intend to protect system from being damaged. All the
protection functions are listed below.
line, the current in power FET is sometimes too high to
Cycle-by-Cycle Current Limit
This is a basic but very useful function and it can be
implemented easily in current mode controller.
wait for a 56ms OLP delay time. To offer better and
easier protection design, the R7780A shuts down the
controller after couples of cycles before fuse is blown
up.
Over Load Protection
Long time cycle-by-cycle current limit will lead to system
thermal stress. To further protect system, system will
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R7780A-01 August 2014
R7780A
Layout Considerations
A proper PCB layout can abate unknown noise interference
and EMI issue in the switching power supply. Please refer
to the guidelines when you want to design PCB layout for
switching power supply :
The current path(1) from bulk capacitor, transformer,
MOSFET, Rcs return to bulk capacitor is a huge high
frequency current loop. The path(2) from gate pin,
MOSFET, Rcs return to bulk capacitor is also a huge
high frequency current loop. They must be as short as
Figure 2. Secondary Rectifier Short Protection
Negative Voltage Spike on Each Pin
Negative voltage (< n0.3V) on each pin will cause substrate
possible to decrease noise coupling and kept a space
to other low voltage traces, such as IC control circuit
paths, especially. Besides, the path(3) between
MOSFET ground(b) and IC ground(d) is recommend to
be as short as possible, too.
injection. It leads to controller damage or circuit false
trigger. Generally, it happens at CS pin due to negative
The path(4) from RCD snubber circuit to MOSFET is a
high switching loop. Keep it as small as possible.
spike because of improper layout or inductive current
sense resistor. Therefore, it is highly recommended to
It is good for reducing noise, output ripple and EMI issue
add a R-C filter to avoid CS pin damage, as shown in
Figure 3. Proper layout and careful circuit design should
be done to guarantee yield rate in mass production.
AC Mains
(90V to 265V)
#
to separate ground traces of bulk capacitor(a),
MOSFET(b), auxiliary winding(c) and IC control circuit
(d). Finally, connect them together on bulk capacitor
ground(a). The areas of these ground traces should be
kept large.
Placing bypass capacitor for abating noise on IC is highly
recommended. The bypass capacitor should be placed
as close to controller as possible.
HV
To minimize reflected trace inductance and EMI minimize
VDD
the area of the loop connecting the secondary winding,
the output diode, and the output filter capacitor. In
R7780A
#
GATE
CS
R-C Filter
addition, apply sufficient copper area at the anode and
cathode terminal of the diode for heatsinking. Apply a
larger area at the quiet cathode terminal. A large anode
area can increase high-frequency radiated EMI.
Figure 3. R-C Filter on CS Pin
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R7780A
CBULK
AC Mains
(90V to 265V)
(a)
(4)
CBULK Ground (a)
R7780A HV
VDD
Trace
Trace
Trace
COMP
GND
IC
Ground (d)
(c)
GATE
Auxiliary
Ground (c)
MOSFET
Ground (b)
CS
(1)
(2)
(d)
(b)
(3)
Figure 4. PCB Layout Guide
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R7780A-01 August 2014
R7780A
Outline Dimension
Symbol
Dimensions In Millimeters
Dimensions In Inches
Min.
Max.
Min.
Max.
A
4.801
5.004
0.189
0.197
B
3.810
3.988
0.150
0.157
C
1.346
1.753
0.053
0.069
D
0.330
0.510
0.013
0.020
F
1.194
1.346
0.047
0.053
F1
2.464
2.616
0.097
0.103
H
0.100
0.254
0.004
0.010
I
0.050
0.254
0.002
0.010
J
5.791
6.200
0.228
0.244
M
0.400
1.270
0.016
0.050
7-Lead SOP Plastic Package
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13
R7780A
Symbol
Dimensions In Millimeters
Dimensions In Inches
Min
Max
Min
Max
A
3.700
4.320
0.146
0.170
A1
0.381
0.710
0.015
0.028
A2
3.200
3.600
0.126
0.142
b
0.360
0.560
0.014
0.022
b1
1.143
1.778
0.045
0.070
D
9.050
9.550
0.356
0.376
E
6.200
6.600
0.244
0.260
E1
7.620
8.255
0.300
0.325
e
L
2.540
3.000
0.100
3.600
0.118
0.142
8-Lead DIP Plastic Package
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
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R7780A-01 August 2014
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