RT1710SGQW

RT1710S Cable ID for USB Type-C Cables General Description Features The RT1710S is a Type-C cable ID for active and passive cables. All USB Full-Featured Type-C cables shall be electronically marked. Electronically marked cables shall support USB Power Delivery Structured VDM Discover Identity command directed to SOP’. This provides a method to determine the characteristics of the cable, e.g. its current carrying capability, its performance, vendor identification, etc. This may be referred to as the USB Type-C Cable ID function.  The RT1710S is available in a WDFN-8L 2x2 package. Ordering Information RT1710S     Support SOP’ Communication Integrated Transceiver (BMC PHY) Embedded Both Side RA Resistor Embedded Both Side ISO Diode Embedded MTP  Support Multi-Time Writable Memory to Store VDM Data  Support 4V to 5.5V Operation on VCON1/VCON2 Pin  Built-in Slew Rate Control for BMC Signal to Reduce the Effect of EMI Support Custom Structured VDM Writing Through CC Pin Support I2C Bus for Programming VDM Data 8-Lead WDFN Package   Package Type QW : WDFN-8L 2x2 (W-Type)  Lead Plating System G : Green (Halogen Free and Pb Free) Applications Note :  USB Full-Featured Type-C Cables Pin Configuration Richtek products are : requirements of IPC/JEDEC J-STD-020.  (TOP VIEW) RoHS compliant and compatible with the current Suitable for use in SnPb or Pb-free soldering VCON2 GND SCL SDA 1 2 3 4 GND  9 8 7 6 5 VCON1 CCIN NC(DG0) NC(DG1) processes. Marking Information 42W 42 : Product Code W : Date Code Copyright © 2017 Richtek Technology Corporation. All rights reserved. DS1710S-00 WDFN-8L 2x2 February 2017 is a registered trademark of Richtek Technology Corporation. www.richtek.com 1 RT1710S Typical Application Circuit VBUS VBUS CC PIN CC PIN VCONN RT1710S NC VCON1 NC CCIN SCL 3 VCON2 SDA 4 GND 8 7 1 2, 9 (Exposed Pad) VCONN 0.1μF 0.1μF Test pad Test pad GND GND Electronically Marked Cable with VCONN connected through the cable VBUS VBUS CC PIN CC PIN VCONN RT1710S 8 NC VCON1 NC 7 CCIN SCL 3 1 VCON2 4 2, GND SDA 9 (Exposed Pad) VCONN 0.1μF 0.1μF Test pad Test pad 0.1μF 0.1μF RT1710S 8 NC VCON1 7 NC CCIN 3 SCL 1 VCON2 4 2, GND SDA 9 (Exposed Pad) Test pad Test pad GND GND Electronically Marked Cable with SOP’ at both ends Functional Pin Description Pin No. Pin Name Pin Function 1 VCON2 The input pin supplied from another side VCONN. 2 GND Ground. 3 SCL This pin is only used for debug. No internal connection. 4 SDA This pin is only used for debug. No internal connection. 5 NC (DG1) No internal connection. 6 NC (DG0) No internal connection. 7 CCIN Configuration channel pin used in the discovery, configuration and management of connections. 8 VCON1 The input pin supplied from VCONN. GND Power ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. 9 (Exposed Pad) Copyright © 2017 Richtek Technology Corporation. All rights reserved. www.richtek.com 2 is a registered trademark of Richtek Technology Corporation. DS1710S-00 February 2017 RT1710S Functional Block Diagram SCL SDA I2C Controller MTP Internal Bus DG0 Cable Policy Engine MUX Control DG1 Register Block Protocol Layer Detection Voltage Regulator USB PD Physical Layer VCON1 RA RA GND VCON2 CCIN Operation SOP’ Communication is recognized by electronics in one Cable Plug (which may be attached to either the Both SOP Communication and SOP’ Communication take place over a single wire (CC pin). For a product UFP or DFP). SOP Communication between the Port Partners is not recognized by the Cable Plug. the term Cable Plug in the SOP’ Communication case is used to represent a logical entity (RT1710S) in the cable which is capable of PD Communication. which does not recognize SOP’ Packets, this will look like a non-idle channel. Copyright © 2017 Richtek Technology Corporation. All rights reserved. DS1710S-00 February 2017 is a registered trademark of Richtek Technology Corporation. www.richtek.com 3 RT1710S Absolute Maximum Ratings (Note1)  VCON1/VCON2-------------------------------------------------------------------------------------------------------- 0.3V to 6V  Power Dissipation, PD @ TA = 25C WDFN-8L 2x2 ---------------------------------------------------------------------------------------------------------- 2.19W  Package Thermal Resistance (Note 2) WDFN-8L 2x2, JA ---------------------------------------------------------------------------------------------------- 45.5°C/W WDFN-8L 2x2, JC ---------------------------------------------------------------------------------------------------- 11.5°C/W  Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------------- 260C  Junction Temperature ------------------------------------------------------------------------------------------------ 150C  Storage Temperature Range --------------------------------------------------------------------------------------- 65C to 150C  ESD Susceptibility (Note 3) HBM (Human Body Model) ----------------------------------------------------------------------------------------- 8kV MM (Machine Model) ------------------------------------------------------------------------------------------------- 200V Recommended Operating Conditions (Note 4)  Supply Input Voltage ------------------------------------------------------------------------------------------------- 4V to 5.5V  Ambient Temperature Range--------------------------------------------------------------------------------------- 40C to 85C  Junction Temperature Range -------------------------------------------------------------------------------------- 40C to 125C Electrical Characteristics (VDD = 5V, TA = 25C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit 270 300 330 Kbps pBitRate -- -- 0.25 % tInterFrameGap 25 -- -- s tStartDrive 1 -- 1 s -- -- 23 s 300 -- -- ns 1 -- -- s 300 -- -- ns Common Normative Signaling Requirements Bit rate f BitRate Common Normative Signaling Requirements for Transmitter Maximum difference between the bit-rate during the part of the packet following the Preamble and the reference bit-rate. Time from the end of last bit of a Frame until the start of the first bit of the next Preamble. Time before the start of the first bit of the Preamble when the transmitter shall start driving the line. BMC Common Normative Requirements Time to cease driving the line after the end of the last bit of the Frame. tEndDriveBMC Fall Time tFall Time to cease driving the line after the final high-to-low transition tHoldLowBMC Rise Time tRise Copyright © 2017 Richtek Technology Corporation. All rights reserved. www.richtek.com 4 is a registered trademark of Richtek Technology Corporation. DS1710S-00 February 2017 RT1710S Parameter Symbol Test Conditions Min Typ Max Unit Voltage Swing vSwing 1.05 1.125 1.2 V Transmitter Output Impedance zDriver 33 -- 75  RA 800 -- 1200  tTransitionWindow 12 -- 20 s zBmcRx 10 -- -- M BMC Receiver Normative Requirements Cable Termination Time Window for Detecting Non-Idle Receiver Input Impedance Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. JA is measured under natural convection (still air) at TA = 25°C with the component mounted on a high effective-thermal-conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard. JC is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Preamble 0 1 0 1 0 1 Sync-1 0 1 0 0 0 Sync-1 1 1 0 0 0 1 1 Data In BMC BMC Example Bus driven after end of Frame End of Frame Bus driven before Preamble Preamble tInterFrameGap tEndDriveBFSK or tStartDrive tEndDriveBMC Inter-Frame Gap Timings 0 1 0 1 1UI 1UI 1UI 0 etc 1 High Impedance (level set by Rp/Rd) 1UI 1UI 1UI tStartDrive BMC Encoded Start of Preamble Copyright © 2017 Richtek Technology Corporation. All rights reserved. DS1710S-00 February 2017 is a registered trademark of Richtek Technology Corporation. www.richtek.com 5 RT1710S Final bit of frame 0 Preamble for next frame Trailing edge of final bit 0 High Impedance (level set by Rp/Rd) 1UI min tHoldLowBMC max tEndDriveBMC tInterFrameGap Transmitting or Receiving BMC Encoded Frame Terminated BMC TC Mask Definition, X values Parameter Left Edge of Mask X2Tx point X3Tx point X4Tx point Symbol X1Tx X2Tx X3Tx X4Tx Typ 0.015 0.07 0.15 0.25 X5Tx point X6Tx point X7Tx point X8Tx point X9Tx point X10Tx point X5Tx X6Tx X7Tx X8Tx X9Tx X10Tx 0.35 0.43 0.485 0.515 0.57 0.65 UI UI UI UI UI UI X11Tx point X12Tx point X13Tx point Right Edge of Mask X11Tx X12Tx X13Tx X14Tx 0.75 0.85 0.93 0.985 UI UI UI UI Copyright © 2017 Richtek Technology Corporation. All rights reserved. www.richtek.com 6 Test Conditions Min Max Units UI UI UI UI is a registered trademark of Richtek Technology Corporation. DS1710S-00 February 2017 RT1710S BMC TC Mask Definition, Y values Parameter Symbol Test Conditions Min Typ Max Units Lower bound of Outer mask Y1Tx -0.075 V Lower bound of inner mask Y2Tx 0.075 V Y3Tx point Y3Tx 0.15 V Y4Tx point Y4Tx 0.325 V Inner mask vertical midpoint Y5Tx 0.5625 V Y6Tx point Y6Tx 0.8 V Y7Tx point Y7Tx 0.975 V Y8Tx point Y8Tx 1.04 V Upper Bound of Outer mask Y9Tx 1.2 V 1UI Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 X1 X2 X3 X4 X5 X6X7 X8 X9 X10 X11 X12 0.5UI X14 X13 BMC Tx ‘ONE’ Mask 1UI Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 X1 X2 X3 X4 X12 0.5UI X14 X13 BMC Tx ‘ZERO’ Mask Copyright © 2017 Richtek Technology Corporation. All rights reserved. DS1710S-00 February 2017 is a registered trademark of Richtek Technology Corporation. www.richtek.com 7 RT1710S Application Information Setting the VDM Type field to 1 (Structured VDM) Start of Packet Sequence Prime (SOP’) The SOP’ ordered set is defined as: two Sync-1 K-codes followed by two Sync-3 K-codes K-code number 1 2 3 4 K-code in code table Sync-1 Sync-1 Sync-3 Sync-3 defines the use of bits Bit[14:0] in the Structured VDM Header. The fields in the Structured VDM Header are defined in Table. The following rules apply to the use of Structured VDM messages:  A Cable Plug capable of SOP’ Communications shall only detect and communicate with packets starting with SOP’. A DFP or Source needing to communicate with a Cable Plug capable of SOP’ Communications, attached between a Port Pair will be able to communicate using both packets starting with SOP’ to communicate with the Cable Plug and starting with SOP to communicate with its Port Partner. The DFP or Source shall co-ordinate SOP and SOP’ Communication so as to avoid collisions.      Structured VDMs shall only be used when an Explicit Contract is in place with the following exception : Prior to establishing an Explicit Contract a Source may issue Discover Identity messages, to a Cable Plug using SOP’ Packets, as an Initiator. Only the DFP shall be an Initiator of Structured VDMs except for the Attention Command that shall only be initiated by the UFP. Only the UFP or a Cable Plug shall be a Responder to Structured VDMs. Structured VDMs shall not be initiated or responded to under any other circumstances. A DFP or UFP which does not support Structured VDMs shall ignore any Structured VDMs received. A Command sequence shall be interruptible e.g. due to the need for a message sequence using SOP Packets. Structured VDM Bit(s) Field Description Bit[31:16] Standard or Vendor ID (SVID) Unique 16 bit unsigned integer, assigned by the USB-IF Bit[15] VDM Type 1 = Structured VDM Bit[14:13] Structured VDM Version Version Number of the Structured VDM (not this specification Version): Version 1.0 = 0 Values 1-3 are reserved Bit[12:11] Reserved Shall be set to 0 and shall be ignored Object Position For the Enter Mode and Exit Mode Commands: 000b = Reserved 001b..110b = Index into the list of VDOs to identify the desired Mode VDO 111b = Exit all Modes (equivalent of a power on reset). Shall not be used with the Enter Mode Command. Bit[10:8] Bit[7:6] Command Type Bit[5] Reserved 00b = Initiator 01b = Responder ACK 10b = Responder NAK 11b = Responder BUSY Shall be set to 0 and shall be ignored Copyright © 2017 Richtek Technology Corporation. All rights reserved. www.richtek.com 8 is a registered trademark of Richtek Technology Corporation. DS1710S-00 February 2017 RT1710S Bit(s) Field Description 0 = Reserved, shall not be used 1 = Discover Identity 2 = Discover SVIDs 3 = Discover Modes Bit[4:0] Command (note 1) 4 = Enter Mode 5 = Exit Mode 6 = Attention 7-15 = Reserved, shall not be used 16..31 = SVID Specific Commands Note 1: In the case where a SID is used the modes are defined by a standard. When a VID is used the modes are defined by the Vendor. Discover Identity The Discover Identity Command is provided to enable an Initiator (DFP) to identify its Port Partner and for an Initiator (Source or DFP) to identify the attached Cable Plug (Responder). The SVID in the Discover SVIDs Command shall be set to the PD SID by both the Initiator and the Responder for this Command. The Discover Identity Command sent back by the Responder contains an ID Header, a Cert Stat VDO and some Type specific VDOs which depend on the Product Type. This specification defines the following Type specific VDOs: Header No. of Data Objects = 4-71 VDM Header ID Header Cert Stat VDO Product VDO 0..32 Product Type VDO(s) ID Header The ID Header contains the Vendor ID corresponding to the Power Delivery Product. Bit(s) Description Data Capable as USB Host : Shall be set to one if the product is capable of enumerating USB Devices.  Shall be set to zero otherwise Bit[31]  Bit[30]  Data Capable as a USB Device : Shall be set to one if the product is capable of enumerating as a USB Device.  Shall be set to zero otherwise Bit[29:27] Product Type : 000b – Undefined  001b – Hub  010b – Peripheral  011b – Passive Cable  100b – Active Cable  101b – Alternate Mode Adapter (AMA)  111b..110b – Reserved, shall not be used. Bit[26]   Modal Operation Supported : Shall be set to one if the product supports Modal Operation.  Shall be set to zero otherwise Bit[25:16] Reserved. Shall be set to zero. Bit[15:0] 16-bit unsigned integer. USB Vendor ID Copyright © 2017 Richtek Technology Corporation. All rights reserved. DS1710S-00 February 2017 is a registered trademark of Richtek Technology Corporation. www.richtek.com 9 RT1710S Cert Stat VDO The Cert Stat VDO contains the Test ID (TID) allocated by USB-IF during certification. Bit(s) Description Bit[31:20] Reserved, shall be set to zero. Bit[19:0] 20-bit unsigned integer, TID Product VDO The Product VDO contains identity information relating to the product. Bit(s) Bit[31:16] Description 16-bit unsigned integer. USB Product ID Bit[15:0] 16-bit unsigned integer. bcdDevice Cable VDO The Cable VDO defined in this section shall be sent when the Product Type is given as Passive or Active Cable. Bit(s) Bit[31:28] Field Cable HW Version Description 0000b..1111b assigned by the VID owner Bit[27:24] Cable Firmware Version 0000b..1111b assigned by the VID owner Bit[23:20] Reserved Shall be set to zero. Bit[19:18] Type-C to Type-A/B/C 00b = Type-A 01b = Type-B 10b = Type-C 11b = Captive Bit[17] Type-C to Plug/Receptacle 0 = Plug 1 = Receptacle (not valid when B19..18 set to Type-C or Captive) Cable Latency 0000b – reserved 0001b –