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Reference
Design
®
RT2568
DDR Termination Regulator
General Description
Features
The RT2568 is a sink/source tracking termination regulator.
It is specifically designed for low-cost and low-external
component count systems. The RT2568 possesses a high
speed operating amplifier that provides fast load transient
response and only requires a minimum 10μF x 3 ceramic
output capacitor. The RT2568 supports remote sensing
functions and all features required to power the DDRIII
and Low Power DDRIII / DDRIV VTT bus termination
according to the JEDEC specification. In addition, the
RT2568 provides an open-drain PGOOD signal to monitor
the output regulation and an EN signal that can be used
to discharge VTT during S3 (suspend to RAM) for DDR
applications.
The RT2568 is available in the thermal efficient package,
WDFN-10L 3x3.
VIN Input Voltage Range : 1.1V to 3.5V
VCNTL Input Voltage Range : 2.9V to 5.5V
Support Ceramic Capacitors
Power Good Indicator
10mA Source/Sink Reference Output
Meet DDRI, DDRII JEDEC Spec
Support DDRI, DDRII, DDRIII and Low Power DDRIII/
DDRIV VTT Applications
Soft-Start Function
UVLO and OCP Protection
Thermal Shutdown
Applications
Notebook/Desktop/Server
Telecom/Datacom, GSM Base Station, LCD-TV/PDPTV, Copier/Printer, Set-Top Box
Simplified Application Circuit
RT2568
VIN
VIN
C1
R2
REFOUT
Chip Enable
VOUT
SENSE
EN
Copyright © 2020 Richtek Technology Corporation. All rights reserved.
September 2020
C5
Power Good Indicator
PGOOD
C3
REFOUT
C4
DS2568-06
R3
REFIN
C2
VCNTL
VCNTL
R1
VOUT
C6
C7
C8
PGND
GND
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RT2568
Ordering Information
Pin Configuration
RT2568
Package Type
QW : WDFN-10L 3x3 (W-Type)
REFIN
VIN
VOUT
PGND
SENSE
Lead Plating System
G : Green (Halogen Free and Pb Free)
RT2568
1
2
3
4
5
PAD
(TOP VIEW)
10
9
11
8
7
6
VCNTL
PGOOD
GND
EN
REFOUT
WDFN-10L 3x3
Pin 1 Orientation***
(2) : Quadrant 2, Follow EIA-481-D
Package Type
QW : WDFN-10L 3x3 (W-Type)
Lead Plating System
G : Green (Halogen Free and Pb Free)
Marking Information
5W= : Product Code
5W=YM
DNN
YMDNN : Date Code
Note :
***Empty means Pin1 orientation is Quadrant 1
Richtek products are :
RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.
Suitable for use in SnPb or Pb-free soldering processes.
Functional Pin Description
Pin No.
Pin Name
Pin Function
1
REFIN
Reference input.
2
VIN
Power input of the regulator.
3
VOUT
Power output of the regulator.
4
PGND
Power ground of the regulator.
5
SENSE
Voltage sense input for the regulator. Connect to positive terminal of the output
capacitor or the load.
6
REFOUT
Reference output. Connect to GND through a 0.1F ceramic capacitor.
7
EN
Enable control input. For DDR VTT application, connect EN to SLP_S3. For
other applications, use EN as the ON/OFF function.
9
PGOOD
Power good open-drain output. Connect a pull-up resistor between this pin and
VCNTL pin.
10
VCNTL
Control voltage input. Connect this pin to the 3.3V or 5V power supply. A
ceramic decoupling capacitor with a value 4.7F is required.
8
GND
Analog ground. Connect to negative terminal of the output capacitor.
11 (Exposed Pad) PAD
Exposed pad. The exposed pad is internally unconnected and must be
soldered to a large PGND plane. Connect this PGND plane to other layers with
thermal vias to help dissipate heat from the device.
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is a registered trademark of Richtek Technology Corporation.
DS2568-06
September 2020
RT2568
Functional Block Diagram
EN VCNTL
REFIN
Control
Logic
Thermal
Protection
Buffer
VIN
+
OCP
-
REFOUT
VOUT
SENSE
OP
+
PGOOD
Power
Good
Driver
+
OCP
-
GND
PGND
Operation
The RT2568 is a linear sink/source DDR termination
regulator with current capability up to 3A. The RT2568
builds in a high-side N-MOSFET which provides current
sourcing and a low-side N-MOSFET which provides current
sinking. All the control circuits are supplied by the power
VCNTL. In normal operation, the error amplifier OP adjusts
the gate driving voltage of the power MOSFET to achieve
SENSE voltage well tracking the REFIN voltage.
Both the source and sink currents are detected by the
internal sensing resistor, and the OCP function will work
to limit the current to a designed value when overload
happens. Furthermore, the current will be folded back to
be one half if VOUT is out of the power good window.
Buffer
This function provides REFOUT output equal to VREFIN
with 10mA source/sink current capability.
Power Good
When the SENSE voltage is in the power good window
and lasts for a certain delay time, then the PGOOD pin
will be high impedance and the PGOOD voltage will be
pulled high by the external resistor.
Over-Current Protection
The device continuously monitors the output current to
protect the pass transistor against abnormal operations.
The current limit (ILIM) level reduces to one-third when the
output voltage is not within the powergood window. This
reduction is a non-latch protection.
Control Logic
This block includes VCNTL UVLO, REFIN UVLO and
Enable/Disable functions, and provides logic control to
the whole chip.
Thermal Protection
Both the high-side and low-side power MOSFETs will be
turned off when the junction temperature is higher than
typically 160°C, and be released to normal operation when
junction temperature falls below 120°C typically.
Copyright © 2020 Richtek Technology Corporation. All rights reserved.
DS2568-06
September 2020
is a registered trademark of Richtek Technology Corporation.
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3
RT2568
Absolute Maximum Ratings
(Note 1)
Supply Voltage, VIN, VCNTL ------------------------------------------------------------------------------------------Input Voltage, EN, REFIN, SENSE ----------------------------------------------------------------------------------Output Voltage, VOUT, REFOUT, PGOOD -------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C
WDFN-10L 3x3 ------------------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2)
WDFN-10L 3x3, θJA ------------------------------------------------------------------------------------------------------WDFN-10L 3x3, θJC ------------------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------Junction Temperature ----------------------------------------------------------------------------------------------------Storage Temperature Range -------------------------------------------------------------------------------------------ESD Susceptibility (Note 3)
HBM (Human Body Model) ---------------------------------------------------------------------------------------------MM (Machine Model) ----------------------------------------------------------------------------------------------------CDM (Charged Device Model) ------------------------------------------------------------------------------------------
Recommended Operating Conditions
−0.3V to 6V
−0.3V to 6V
−0.3V to 6V
2.5W
40°C/W
7.5°C/W
260°C
150°C
−65°C to 150°C
2kV
200V
2kV
(Note 4)
Control Input Voltage, VCNTL ------------------------------------------------------------------------------------------ 2.9V to 5.5V
Supply Input Voltage, VIN ----------------------------------------------------------------------------------------------- 1.1V to 3.5V
Junction Temperature Range -------------------------------------------------------------------------------------------- −40°C to 125°C
Electrical Characteristics
(VIN = 1.5V, VEN = VCNTL = 3.3V, VREFIN = VSENSE = 0.75V, COUT = 10μF x 3, TA = −40°C to 85°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
VEN = VCNTL, no load
--
0.7
1
mA
VEN = 0V, VREFIN = 0V, no load
--
65
80
VEN = 0V, VREFIN > 0.4V, no load
--
200
400
Supply Current
VCNTL Supply Current
IVCNTL
VCNTL Shutdown Current
ISHDN_VCNTL
VIN Supply Current
IVIN
VEN = VCNTL, no load
--
1
50
A
VIN Shutdown Current
ISHDN_VIN
VEN = 0V, no load
--
0.1
50
A
VIN = 1.5V, VREFIN = 0.75V,
IOUT = 0A
--
0.75
--
VIN = 1.35V, VREFIN = 0.675V,
IOUT = 0A
--
0.675
--
VIN = 1.2V, VREFIN = 0.6V,
IOUT = 0A
--
0.6
--
IOUT < ±2A, VLDOIN = 1.5V,
VOUT_OS = VOUT VOUTO
25
--
25
IOUT < ±2A, VLDOIN = 1.35V,
VOUT_OS = VOUT VOUTO
25
--
25
IOUT < ±2A, VLDOIN = 1.2V,
VOUT_OS = VOUT VOUTO
25
--
25
A
Output
VTT Output Voltage
VTT Output Voltage Offset
VOUTO
VOUT_OS
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V
mV
is a registered trademark of Richtek Technology Corporation.
DS2568-06
September 2020
RT2568
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
VOUT Source Current Limit ILIM_VOUT_SR
VOUT in PGOOD window
3
4.5
--
A
VOUT Sink Current Limit
ILIM_VOUT_SK
VOUT in PGOOD window
3
4.5
--
A
VOUT Discharge
Resistance
RDISCHARGE
VREFIN = 0V, VOUT = 0.3V,
VEN = 0V
--
18
25
VSENSE lower threshold with
respect to REFOUT
--
20
--
VSENSE upper threshold with
respect to REFOUT
--
20
--
PGOOD hysteresis
--
5
--
Power Good Comparator
PGOOD Threshold
VTH_PGOOD
%
PGOOD Start-Up Delay
TPGDELAY1
Start-up rising delay, VSENSE
within PGOOD range
--
2
--
ms
Output Low Voltage
VLOW_PGOOD
IPGOOD = 4mA
--
--
0.4
V
PGOOD Falling Delay
TPGDELAY2
Falling delay, VSENSE is out of
PGOOD range
--
10
--
s
Leakage Current
VSENSE = VREFIN (PGOOD high
ILEAKAGE _PGOOD impedance),
VPGOOD = VCNTL + 0.2V
--
--
1
A
REFIN Input Current
IREFIN
--
--
1
A
REFIN Voltage Range
VREFIN
0.5
--
1.8
V
REFIN Under-Voltage
Lockout
VUVLO_REFIN
360
390
420
--
20
--
10mA < IREFOUT < 10mA,
VREFIN = 0.75V
15
--
15
10mA < IREFOUT < 10mA,
VREFIN = 0.675V
15
--
15
10mA < IREFOUT < 10mA,
VREFIN = 0.6V
15
--
15
VREFOUT = 0V
10
40
--
mA
VREFOUT = REFIN + 1V
10
40
--
mA
Rising
2.5
2.7
2.85
V
--
120
--
mV
REFIN and REFOUT
REFOUT Voltage Tolerance
VTOL_REFOUT
to VREFIN
REFOUT Source Current
ILIM_REFOUT_SR
Limit
REFOUT Sink Current Limit ILIM_REFOUT_SK
VEN = VCNTL
REFIN rising
Hysteresis
mV
mV
UVLO/EN
UVLO Threshold
EN Input
Voltage
VUVLO_VCNTL
Hysteresis
Logic-High
VIN_H
1.7
--
--
Logic-Low
VIN_L
--
--
0.3
--
160
--
--
15
--
V
Thermal Shutdown
Thermal Shutdown
Threshold
TSD
Shutdown temperature
Hysteresis
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DS2568-06
September 2020
(Note 5)
(Note 5)
°C
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RT2568
Note 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. Guarantee by design.
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is a registered trademark of Richtek Technology Corporation.
DS2568-06
September 2020
RT2568
Typical Application Circuit
RT2568
2
VIN
R1
10k
C1
C2
10µF 10µF
1
R2
10k
C4
0.1µF
Chip Enable
7
VCNTL
10
REFIN
PGOOD
C3
1nF
6
REFOUT
VIN
9
3
VOUT
5
SENSE
REFOUT
PGND
EN
4
R3
100k
C5
4.7µF
VCNTL
Power Good Indicator
VOUT
C6
10µF
C7
10µF
C8
10µF
GND 8
Table 1. Recommended External Components
Component
Description
Vendor P/N
C1, C2, C6, C7, C8
10F, 6.3V, X7R, 0805
GRM21BR70J106KE76L (Murata)
CGA4J1X7R0J106K125AC (TDK)
C3
1nF, 50V, X7R, 0603
GCD188R71H102KA01D (Murata)
CGA3E2X7R1H102K080AA (TDK)
C4
0.1F, 16V, X7R, 0603
GCJ188R71C104KA01D (Murata)
C5
4.7F, 6.3V, X5R, 0603
GRT188R60J475ME01D (Murata)
CGB3B3X5R0J475M055AB(TDK)
Copyright © 2020 Richtek Technology Corporation. All rights reserved.
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September 2020
is a registered trademark of Richtek Technology Corporation.
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RT2568
Typical Operating Characteristics
Load Regulation
0.65
0.63
0.63
0.61
0.61
Output Voltage (V)
Output Voltage (V)
Load Regulation
0.65
0.59
0.57
85°C
25°C
−40°C
0.55
0.53
0.51
0.49
85°C
25°C
−40°C
0.59
0.57
0.55
0.53
0.51
0.49
0.47
VIN = VDDQSNS = 1.1V, VOUT = 0.55V,
VCNTL = 3.3V
0.47
VIN = VDDQSNS = 1.1V, VOUT = 0.55V, VCNTL = 5V
0.45
0.45
-3
-2
-1
0
1
2
3
-3
-2
Output Current (A)
0.68
0.68
0.66
0.66
0.64
0.62
85°C
25°C
−40°C
0.58
0.56
1
2
3
85°C
25°C
−40°C
0.64
0.62
0.60
0.58
0.56
0.54
0.54
0.52
0.52
VIN = VDDQSNS = 1.2V, VOUT = 0.6V, VCNTL = 5V
VIN = VDDQSNS = 1.2V, VOUT = 0.6V, VCNTL = 3.3V
0.50
0.50
-3
-2
-1
0
1
2
-3
3
-2
Output Current (A)
0.755
0.755
0.735
0.735
Output Voltage (V)
0.775
0.715
0.695
85°C
25°C
−40°C
0.655
0
1
2
3
Load Regulation
0.775
0.675
-1
Output Current (A)
Load Regulation
Output Voltage (V)
0
Load Regulation
0.70
Output Voltage (V)
Output Voltage (V)
Load Regulation
0.70
0.60
-1
Output Current (A)
0.635
0.615
85°C
25°C
−40°C
0.715
0.695
0.675
0.655
0.635
0.615
0.595
VIN = VDDQSNS = 1.35V, VOUT = 0.675V,
VCNTL = 3.3V
0.595
VIN = VDDQSNS = 1.35V, VOUT = 0.675V, VCNTL = 5V
0.575
0.575
-3
-2
-1
0
1
2
Output Current (A)
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3
-3
-2
-1
0
1
2
3
Output Current (A)
is a registered trademark of Richtek Technology Corporation.
DS2568-06
September 2020
RT2568
Load Regulation
0.85
0.83
0.83
0.81
0.81
Output Voltage (V)
Output Voltage (V)
Load Regulation
0.85
0.79
0.77
85°C
25°C
−40°C
0.75
0.73
0.71
0.69
85°C
25°C
−40°C
0.79
0.77
0.75
0.73
0.71
0.69
0.67
0.67
VIN = VDDQSNS = 1.5V, VOUT = 0.75V, VCNTL = 5V
0.65
VIN = VDDQSNS = 1.5V, VOUT = 0.75V, VCNTL = 3.3V
0.65
-3
-2
-1
0
1
2
3
-3
-2
-1
Output Current (A)
0.98
0.98
0.96
0.96
0.94
0.92
85°C
25°C
−40°C
0.86
0.84
85°C
25°C
−40°C
0.94
0.92
0.90
0.88
0.86
0.82
VIN = VDDQSNS = 1.8V, VOUT = 0.9V, VCNTL = 5V
0.80
VIN = VDDQSNS = 1.8V, VOUT = 0.9V, VCNTL = 3.3V
0.80
-3
-2
-1
0
1
2
3
-3
-2
-1
Output Current (A)
1.33
1.33
1.31
1.31
Output Voltage (V)
1.35
1.29
1.27
85°C
25°C
−40°C
1.23
1
2
3
Load Regulation
1.35
1.25
0
Output Current (A)
Load Regulation
Output Voltage (V)
3
0.84
0.82
1.21
1.19
VIN = VDDQSNS = 2.5V, VOUT = 1.25V, VCNTL = 3.3V
1.29
1.27
85°C
25°C
−40°C
1.25
1.23
1.21
1.19
1.17
1.17
VIN = VDDQSNS = 2.5V, VOUT = 1.25V, VCNTL = 5V
1.15
1.15
-3
-2
-1
0
1
2
Output Current (A)
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DS2568-06
2
Load Regulation
1.00
Output Voltage (V)
Output Voltage (V)
Load Regulation
0.88
1
Output Current (A)
1.00
0.90
0
September 2020
3
-3
-2
-1
0
1
2
3
Output Current (A)
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RT2568
REFOUT Voltage vs. Temperature
1.0
0.9
0.9
REFOUT Voltage (V)
Output Voltage (V)
Output Voltage vs. Temperature
1.0
0.8
0.7
0.6
0.8
0.7
0.6
VIN = VDDQSNS = 1.5V, VOUT = 0.75V,
VCNTL = 3.3V
VIN = VDDQSNS = 1.5V, VOUT = 0.75V,
VCNTL = 3.3V
0.5
0.5
-50
-25
0
25
50
75
100
125
-50
-25
0
50
75
100
125
VCNTL Shutdown Current vs. Temperature
VCNTL Supply Current vs. Temperature
500.0
350
480.0
460.0
440.0
VCNTL = 5V
420.0
400.0
380.0
360.0
VCNTL = 3.3V
340.0
320.0
VIN = VDDQSNS = 1.5V, VOUT = 0.75V
300.0
-50
-25
0
25
50
75
100
VCNTL Shutdown Current (μA)1
VCNTL Supply Current (μA)1
25
Temperature (°C)
Temperature (°C)
300
250
VCNTL = 5V
200
VCNTL = 3.3V
150
100
VIN = VDDQSNS = 1.5V, VOUT = 0.75V
50
125
-50
-25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
UVLO vs. Temperature
Sourcing Current Limit vs. Temperature
4.0
3.0
2.9
3.5
2.8
UVLO (V)
Current Limit (A)
Rising
2.7
2.6
2.5
Falling
2.4
2.3
2.2
VIN = VDDQSNS = 1.5V,
VEN = 2V, VOUT = 0.75V
2.1
2.0
-50
-25
0
25
50
75
100
Temperature (°C)
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125
3.0
2.5
2.0
1.5
VIN = VDDQSNS = 1.5V, VOUT = 0.75V,
VCNTL = 3.3V
1.0
-50
-25
0
25
50
75
100
125
Temperature (°C)
is a registered trademark of Richtek Technology Corporation.
DS2568-06
September 2020
RT2568
Power On from EN
Sinking Current Limit vs. Temperature
4.0
VEN
(2V/Div)
Current Limit (A)
3.5
3.0
VOUT
(0.5V/Div)
2.5
2.0
IOUT
(1A/Div)
1.5
VCNTL = 3.3V,
VIN = VDDQSNS = 1.5V, VOUT = 0.75V
VREFOUT
(1V/Div)
1.0
-50
-25
0
25
50
75
100
VCNTL = 3.3V, VIN = 1.5V,
VOUT = 0.75V, IOUT = 1.5A
Time (100μs/Div)
125
Temperature (°C)
0.75VOUT @ 1.5A Transient Response
Power Off from EN
VEN
(2V/Div)
VOUT
(10mV/Div)
VOUT
(0.5V/Div)
IOUT
(1A/Div)
VREFOUT
(1V/Div)
VCNTL = 3.3V, VIN = 1.5V,
VOUT = 0.75V, IOUT = 1.5A
IOUT
(1A/Div)
Source, VIN = 1.5V
Time (500μs/Div)
Time (10μs/Div)
0.75VOUT @ 1.5A Transient Response
VOUT
(10mV/Div)
IOUT
(1A/Div)
Sink, VIN = 1.5V
Time (500μs/Div)
Copyright © 2020 Richtek Technology Corporation. All rights reserved.
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September 2020
is a registered trademark of Richtek Technology Corporation.
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RT2568
Application Information
Capacitor Selection
Good bypassing is recommended from VLDOIN to GND
to help improve AC performance. A 10μF or greater input
capacitor located as close as possible to the IC is
recommended. The input capacitor must be located at a
distance of less than 0.5 inches from the VLDOIN pin of
the IC.
WDFN-10L 3x3 package, the thermal resistance, θJA, is
40°C/W on a standard JEDEC 51-7 four-layer thermal test
board. The maximum power dissipation at TA = 25°C can
be calculated by the following formula :
P D(MAX) = (125°C − 25°C) / (40°C/W) = 2.5W for
WDFN-10L 3x3 package
The maximum power dissipation depends on the operating
ambient temperature for fixed T J(MAX) and thermal
resistance, θJA. The derating curve in Figure 1 allows the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
3.0
Maximum Power Dissipation (W)1
The RT2568 is a 3.5A sink/source tracking termination
regulator. It is specifically designed for low-cost and lowexternal component count system such as notebook PC
applications. The RT2568 possesses a high speed
operating amplifier that provides fast load transient response
and only requires two 10μF ceramic input capacitors and
three 10μF ceramic output capacitors.
Four-Layer PCB
2.5
2.0
Adding a 1μF ceramic capacitor close to the VIN pin and
it should be kept away from any parasitic impedance from
the supply power. For stable operation, the total
capacitance of the ceramic capacitor at the VTT output
terminal must be larger than 30μF. The RT2568 is designed
specifically to work with low ESR ceramic output capacitor
in space saving and performance consideration. Larger
output capacitance can reduce the noise and improve load
transient response, stability and PSRR. The output
capacitor should be located near the VTT output terminal
pin as close as possible.
Figure 1. Derating Curve of Maximum Power Dissipation
Thermal Considerations
Layout Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
For best performance of the RT2568, the PCB layout
suggestions below are highly recommend :
1.0
0.5
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
With wide and short connection plane between
capacitors and pins for trace impedance minimization.
The ground plane connected by a wide copper surface
for good thermal dissipation, add via connection also
helps reduce the GND loop trace.
Connect the SENSE pin to the positive node of output
capacitor at VOUT terminal for output target level remote
sensing.
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
1.5
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
Copyright © 2020 Richtek Technology Corporation. All rights reserved.
www.richtek.com
12
is a registered trademark of Richtek Technology Corporation.
DS2568-06
September 2020
RT2568
Since the output voltage VOUT setting is follow the REFIN
pin input voltage level VREFIN (VOUT = VREFIN), the REFIN
pin can connected with independent voltage source for
stable input signal and good VOUT target accuracy. For
the application which VREFIN sinks the voltage source
divided from VIN power trace, with separate connection
trace between R1 and VIN terminal side for good VREFIN
signal stability also avoid the reference voltage level
shrink down caused by VIN trace loss at high load
operation.
Figure 2 shows an example for the layout reference that
reduce conduction trace loop, helping inductive parasitic
minimize, load transient reduction and good circuit stability.
VIN source
terminal
GND Plane
VIN Plane
R1
C2
R2
C3
REFIN
VIN
VOUT
C6 PGND
SENSE
C5
1
2
3
4
5
PAD
C1
11
10
9
8
7
6
VCNTL
PGOOD
GND
EN
REFOUT
C7
C8
GND Plane
VOUT Plane
C4
PGOOD reference
source input
R3
Enable
signal input
GND Plane
Add via for thermal consideration and
reduce the loop impedance of ground
plane
Figure 2. PCB Layout Guide
Copyright © 2020 Richtek Technology Corporation. All rights reserved.
DS2568-06
September 2020
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
13
RT2568
Outline Dimension
D2
D
L
E
E2
1
e
SEE DETAIL A
b
2
1
2
1
A
A1
A3
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Symbol
Dimensions In Millimeters
Dimensions In Inches
Min
Max
Min
Max
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.180
0.300
0.007
0.012
D
2.950
3.050
0.116
0.120
D2
2.300
2.650
0.091
0.104
E
2.950
3.050
0.116
0.120
E2
1.500
1.750
0.059
0.069
e
L
0.500
0.350
0.020
0.450
0.014
0.018
W-Type 10L DFN 3x3 Package
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
www.richtek.com
14
DS2568-06
September 2020
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