®
RT3662AC
Dual-Output PWM Controller with 3 Integrated Drivers for
AMD SVI2 Mobile CPU Power Supply
General Description
Features
The RT3662AC is a dual-output PWM controller with 3
integrated drivers, and it is compliant with AMD SVI2
Voltage Regulator Specification to support both CPU core
(VDD) and Northbridge portion of CPU (VDDNB). The
RT3662AC features CCRCOT (Constant Current Ripple
Constant On-Time) with G-NAVP (Green-Native AVP),
which is Richtek’ s proprietary topology. G-NAVP makes
it an easy setting controller to meet all AMD AVP (Adaptive
Voltage Positioning) VDD/VDDNB requirements. The droop
is easily programmed by setting the DC gain of the error
amplifier. With proper compensation, the load transient
response can achieve optimized AVP performance. The
controller also uses the interface to issue VOTF Complete
and to send digitally encoded voltage and current values
for the VDD/VDDNB domains. The RT3662AC can operate
in diode emulation mode to enhance the light load
efficiency. And it provides the current gain adjustment
capability by pin setting. The RT3662AC provides power
good indication, thermal indication (VRHOT_L), and it
features complete fault protection functions including over
current, over voltage and under voltage.
Applications
Ordering Information
RT3662AC
Package Type
QW : WQFN-40L 5x5 (W-Type)
Lead Plating System
G : Green (Halogen Free and Pb Free)
Note :
2/1-Phase (VDD) + 1/0-Phase (VDDNB) PWM
Controller
3 Embedded MOSFET Drivers
G-NAVPTM Topology
Support Dynamic Load-Line and Zero Load-Line
Diode Emulation Mode at Light Load Condition
SVI2 Interface to Comply with AMD Power
Management Protocol
Adjustable Current Gain Capability
DVID Enhancement
0.5% DAC Accuracy
Differential Remote Voltage Sensing
Build-in ADC for Pin Setting Programming, Thermal
Indication and VOUT, IOUT Reporting
Fast Transient Response
Power Good Indicator
Thermal Indicator (VRHOT_L)
OVP, UVP and UVLO
Over Current Protection
AMD SVI2 Mobile CPU
Laptop Computer
Marking Information
RT3662ACGQW : Product Number
RT3662AC
GQW
YMDNN
YMDNN : Date Code
Richtek products are :
RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.
Suitable for use in SnPb or Pb-free soldering processes.
Simplified Application Circuit
RT3662AC
PHASE1
VRHOT_L
To CPU
SVC
SVD
SVT
Copyright © 2017 Richtek Technology Corporation. All rights reserved.
DS3662AC-04 July 2017
MOSFET
PHASE2
MOSFET
PHASE_NB
MOSFET
VVDD
VVDDNB
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
1
RT3662AC
Pin Configuration
PHASE2
LGATE2
BOOT1
UGATE1
PHASE1
LGATE1
PVCC
LGATE_NB
PHASE_NB
UGATE_NB
(TOP VIEW)
40 39 38 37 36 35 34 33 32 31
UGATE2
BOOT2
PGOOD
RGND
COMP
FB
ISEN2P
VSEN
ISEN1P
ISEN1N
1
30
2
29
3
28
4
27
5
26
GND
6
25
24
7
8
41
9
23
22
21
10
BOOT_NB
EN
VIN
COMP_NB
FB_NB
ISENP_NB
ISENN_NB
TSEN_NB
VDDIO
SVT
VRHOT_L
TSEN
SET1
IMON
VREF_PINSET
IMON_NB
VCC
PWROK
SVC
SVD
11 12 13 14 15 16 17 18 19 20
WQFN-40L 5x5
Functional Pin Description
Pin No
Pin Name
Pin Function
Upper gate driver output of Phase 2 for VDD controller. Connect this pin to the
gate input of high side MOSFET.
Bootstrap supply of VDD controller for Phase 2 high side MOSFET. This pin
powers high side MOSFET driver.
Power good indicator for the VDD and VDDNB controller. This pin is an open
drain output.
Return ground of VDD and VDDNB controllers. This pin is the common negative
input of output voltage differential remote sense of VDD and VDDNB controllers.
1
UGATE2
2
BOOT2
3
PGOOD
4
RGND
5
COMP
Error amplifier output pin of the VDD controller.
6
FB
Output voltage feedback input of VDD controller. This pin is the negative input of
the error amplifier for the VDD controller.
7
ISEN2P
Positive current sense input of Phase 2 for VDD controller.
8
VSEN
9
ISEN1P
10
ISEN1N
11
VRHOT_L
12
TSEN
VDD controller voltage sense input. This pin is connected to the terminal of VDD
controller output voltage.
Positive current sense input of Phase 1 for VDD controller.
Common negative current sense input of Phase1 and Phase 2 for VDD
controller.
Thermal indicator. This pin is an open drain output. (Active low)
This pin provides two functions: platform setting, platform can use this pin to set
frequency of VDD and VDDNB controllers, initial offset and per-phase OCP
threshold of VDD controller. The other function is thermal sense input for
VRHOT indicator. Connect the NTC network for thermal sensing to this pin.
Copyright © 2017 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS3662AC-04 July 2017
RT3662AC
Pin No
Pin Name
13
SET1
14
IMON
15
VREF_PINSET
16
IMON_NB
17
VCC
18
PWROK
19
SVC
Pin Function
Platform setting pin. Platform can use this pin to set the Ai gain of VDD and
VDDNB controllers, VDDNB voltage reporting compensation bit1 to bit3 and
VDD Controller QRTH.
Current monitor output for the VDD controller. This pin outputs a voltage
proportional to the output current.
This pin provides two functions: The 3.2V power supply for pin setting function
divided resistors. The other function is fixed 0.8V output reference voltage,
and the voltage is only used to offset the output voltage of IMON and
IMON_NB pins. Connect a RC circuit from this pin to GND. The recommended
resistor is from 3.9 to 10, and the capacitor is 0.47F.
Current monitor output for the VDDNB controller. This pin outputs a voltage
proportional to the output current.
Controller power supply. Connect this pin to 5V and place a decoupling
capacitor 2.2F at least. The decoupling capacitor is as close controller as
possible.
System power good input. If PWROK is low, the SVI interface is disabled and
VR returns to BOOT-VID state with initial load-line slope and initial offset. If
PWROK is high, the SVI interface is running and the DAC decodes the
received serial VID codes to determine the output voltage.
Serial VID clock input.
20
SVD
Serial VID data input. This pin is a serial data line.
21
SVT
Serial VID telemetry output from VR. This pin is a push-pull output.
22
VDDIO
23
TSEN_NB
24
ISENN_NB
Negative current sense input for VDDNB controller.
25
ISENP_NB
26
FB_NB
Positive current sense input for VDDNB controller.
Output voltage feedback input of VDDNB controller. This pin is the negative
input of the error amplifier for the VDDNB controller.
27
COMP_NB
Error amplifier output pin of the VDDNB controller.
28
VIN
VIN input pin. Connect a low pass filter to this pin.
29
EN
Controller enable input pin.
30
BOOT_NB
31
UGATE_NB
32
PHASE_NB
33
LGATE_NB
34
PVCC
Processor memory interface power rail and serves as the reference for
PWROK, SVD, SVC and SVT. This pin is used by the VR to reference the SVI
pins.
This pin provides two functions: platform setting, platform can use this pin to
set initial offset, BOOT VID, voltage reporting compensation bit0 and perphase OCP threshold of VDDNB controller. The other function is thermal
sense input for VRHOT indicator. Connect the NTC network for thermal
sensing to this pin.
Bootstrap supply of VDDNB controller for high side MOSFET. This pin powers
high side MOSFET driver.
Upper gate driver output of VDDNB controller. Connect this pin to the gate
input of high side MOSFET.
Switch nodes of high side driver for VDDNB controller. Connect this pin to
high side MOSFET source together with the low side MOSFET drain and the
inductor.
Lower gate driver output of VDDNB controller. Connect this pin to the gate
input of low side MOSFET.
Driver power supply. Connect this pin to GND by the 2.2F ceramic capacitor
at least. The decoupling capacitor is as close controller as possible.
Copyright © 2017 Richtek Technology Corporation. All rights reserved.
DS3662AC-04 July 2017
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
3
RT3662AC
Pin No
Pin Name
35
LGATE1
36
PHASE1
37
UGATE1
38
BOOT1
39
LGATE2
40
PHASE2
41
(Exposed Pad)
GND
Pin Function
Lower gate driver output of Phase 1 for VDD controller. Connect this pin to
the gate input of low side MOSFET.
Phase 1 switch nodes of high side driver for VDD controller. Connect this pin
to high side MOSFET source together with the low side MOSFET drain and
the inductor.
Upper gate driver output of Phase 1 for VDD controller. Connect this pin to
the gate input of high side MOSFET.
Bootstrap supply of VDD controller for Phase 1 high side MOSFET. This pin
powers high side MOSFET driver.
Lower gate driver output of Phase 2 for VDD controller. Connect this pin to
the gate input of low side MOSFET.
Phase 2 switch nodes of high side driver for VDD controller. Connect this pin
to high side MOSFET Source together with the low side MOSFET drain and
the inductor.
Ground. The exposed pad must be soldered to a large PCB and connected
to GND for maximum power dissipation.
Copyright © 2017 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS3662AC-04 July 2017
RT3662AC
VRHOT_L
PGOOD
VCC
EN
PWROK
VDDIO
SVT
SVD
SVC
TSEN_NB
TSEN
IMONI_NB
IMONI
ISENN_NB
SET1
VSEN
Functional Block Diagram
UVLO
GND
MUX
From Control Logic
RGND
SVI2 Interface
Configuration Registers
Control Logic
ADC
DAC
Soft Start &
Slew Rate Control
VSET
+
ERROR
AMP
AI_VDD, AI_VDDNB
QR_TH
TONSET
OFFSET
PHOCP_TH
VDDNB Voltage
Reporting Compensation
Offset
Cancellation
FB
-
COMP
PWM
CMP
ISEN1N
-
0.75 x AI_VDD
IB1
BOOTx
PWM2 Driver
UGATEx
PHASEx
LGATEx
RAMP
TONSET
+
1.867m
ISEN2P
PWM1
TON
GEN
QR_TH
1.867m
+
VIN
+
+
ISEN1P
Loop Control
Protection
Logic
-
Current
Balance
IB2
+
VSEN
IMON
IMONI
IB1
Driver
POR
IB2
OV/UV
VREF_PINSET
PVCC
From Control Logic
+
RGND
OCP_SPIKE
DAC
Soft Start&
Slew Rate Control
ERROR
AMP
VSET_NB
OC
To Protection Logic
-
VIN
Offset
Cancellation
+
-
+
-
+
FB_NB
PWM
CMP
TON
GEN
COMP_NB
ISENP_NB
+
-
BOOT_NB
Driver
UGATE_NB
PHASE_NB
TONSET
1.867m
ISENN_NB
PWM
_NB
LGATE_NB
RAMP
0.75 x AI_VDDNB
+
VREF_PINSET
-
IMON_NB
IMONI_NB
ISENN_NB
OV/UV
+ OC_NB
OCP_SPIKE_NB
Copyright © 2017 Richtek Technology Corporation. All rights reserved.
DS3662AC-04 July 2017
-
To Protection Logic
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
5
RT3662AC
Operation
The RT3662AC adopts G-NAVPTM (Green Native AVP)
which is Richtek’ s proprietary topology derived from finite
DC gain of EA amplifier with current mode control, making
it easy to set the droop to meet all AMD CPU requirements
of AVP (Adaptive Voltage Positioning). The G-NAVPTM
controller is one type of current mode constant on-time
control with DC offset cancellation. The approach can not
only improve DC offset problem for increasing system
accuracy but also provide fast transient response. When
current feedback signal reaches COMP signal, it
generates an on-time width to achieve PWM modulation.
Error Amplifier
MUX and ADC
Current Balance
The MUX supports the inputs from SET1, TSEN,
TSEN_NB, IMONI, IMONI_NB, ISENN_NB and VSEN. The
ADC converts these analog signals to digital codes for
reporting or performance adjustment.
Each phase current sense signal is sent to the current
balance circuit which adjusts the on-time of each phase
to optimize current sharing.
SVI2 Interface/Configuration Registers/Control Logic
The PWM comparator compares COMP signal (COMP/
COMP_NB) and current feedback signal to generate a
signal for TONGEN.
The SVI2 interface uses the SVC, SVD, and SVT pins to
communicate with CPU. The configuration registers save
the digital data from ADC output for reporting or
performance adjustment. The Control Logic controls the
ADC timing and generates the digital code of the VID for
VDD/VDDNB voltage.
Error amplifier generates COMP/COMP_NB signal by the
difference between VSET/VSET_NB and FB/FB_NB.
Offset Cancellation
This block cancels the output offset voltage from voltage
ripple and current ripple to achieve accurate output voltage.
UVLO
Detect the VCC pin voltage for under voltage lockout
protection and power on reset operation.
PWM CMP
TONGEN
This block generates an on-time pulse which high interval
is based on the on-time setting.
Loop Control Protection Logic
RAMP
Loop control protection logic detects EN and UVLO signals
to initiate the soft-start function, and the PGOOD and
VRHOT_L will be controlled after the soft-start is finished.
When VRHOT indication event occurs, the VRHOT_L pin
voltage will be pulled low.
The Ramp generator is designed to improve noise immunity
and reduce jitter.
OC/OV/UV
Output voltage and output current are sensed for over
current, over voltage and under voltage protection.
DAC
The DAC receives VID codes from the SVI2 control logic
to generate an internal reference voltage (VSET/VSET_NB)
for controller.
Soft-Start and Slew-Rate Control
This block controls the slew rate of the internal reference
voltage when output voltage changes.
Copyright © 2017 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS3662AC-04 July 2017
RT3662AC
Table 1. Serial VID Codes
SVID [7:0] Voltage (V)
SVID [7:0]
Voltage (V)
SVID [7:0]
Voltage (V)
SVID [7:0]
Voltage (V)
0000_0000
1.55000
0010_0111
1.30625
0100_1110
1.06250
0111_0101
0.81875
0000_0001
1.54375
0010_1000
1.30000
0100_1111
1.05625
0111_0110
0.81250
0000_0010
1.53750
0010_1001
1.29375
0101_0000
1.05000
0111_0111
0.80625
0000_0011
1.53125
0010_1010
1.28750
0101_0001
1.04375
0111_1000
0.80000
0000_0100
1.52500
0010_1011
1.28125
0101_0010
1.03750
0111_1001
0.79375
0000_0101
1.51875
0010_1100
1.27500
0101_0011
1.03125
0111_1010
0.78750
0000_0110
1.51250
0010_1101
1.26875
0101_0100
1.02500
0111_1011
0.78125
0000_0111
1.50625
0010_1110
1.26250
0101_0101
1.01875
0111_1100
0.77500
0000_1000
1.50000
0010_1111
1.25625
0101_0110
1.01250
0111_1101
0.76875
0000_1001
1.49375
0011_0000
1.25000
0101_0111
1.00625
0111_1110
0.76250
0000_1010
1.48750
0011_0001
1.24375
0101_1000
1.00000
0111_1111
0.75625
0000_1011
1.48125
0011_0010
1.23750
0101_1001
0.99375
1000_0000
0.75000
0000_1100
1.47500
0011_0011
1.23125
0101_1010
0.98750
1000_0001
0.74375
0000_1101
1.46875
0011_0100
1.22500
0101_1011
0.98125
1000_0010
0.73750
0000_1110
1.46250
0011_0101
1.21875
0101_1100
0.97500
1000_0011
0.73125
0000_1111
1.45625
0011_0110
1.21250
0101_1101
0.96875
1000_0100
0.72500
0001_0000
1.45000
0011_0111
1.20625
0101_1110
0.96250
1000_0101
0.71875
0001_0001
1.44375
0011_1000
1.20000
0101_1111
0.95625
1000_0110
0.71250
0001_0010
1.43750
0011_1001
1.19375
0110_0000
0.95000
1000_0111
0.70625
0001_0011
1.43125
0011_1010
1.18750
0110_0001
0.94375
1000_1000
0.70000
0001_0100
1.42500
0011_1011
1.18125
0110_0010
0.93750
1000_1001
0.69375
0001_0101
1.41875
0011_1100
1.17500
0110_0011
0.93125
1000_1010
0.68750
0001_0110
1.41250
0011_1101
1.16875
0110_0100
0.92500
1000_1011
0.68125
0001_0111
1.40625
0011_1110
1.16250
0110_0101
0.91875
1000_1100
0.67500
0001_1000
1.40000
0011_1111
1.15625
0110_0110
0.91250
1000_1101
0.66875
0001_1001
1.39375
0100_0000
1.15000
0110_0111
0.90625
1000_1110
0.66250
0001_1010
1.38750
0100_0001
1.14375
0110_1000
0.90000
1000_1111
0.65625
0001_1011
1.38125
0100_0010
1.13750
0110_1001
0.89375
1001_0000
0.65000
0001_1100
1.37500
0100_0011
1.13125
0110_1010
0.88750
1001_0001
0.64375
0001_1101
1.36875
0100_0100
1.12500
0110_1011
0.88125
1001_0010
0.63750
0001_1110
1.36250
0100_0101
1.11875
0110_1100
0.87500
1001_0011
0.63125
0001_1111
1.35625
0010_0110
1.11250
0110_1101
0.86875
1001_0100
0.62500
0010_0000
1.35000
0100_0111
1.10625
0110_1110
0.86250
1001_0101
0.61875
0010_0001
1.34375
0100_1000
1.10000
0110_1111
0.85625
1001_0110
0.61250
0010_0010
1.33750
0100_1001
1.09375
0111_0000
0.85000
1001_0111
0.60625
0010_0011
1.33125
0100_1010
1.08750
0111_0001
0.84375
1001_1000
0.60000
0010_0100
1.32500
0100_1011
1.08125
0111_0010
0.83750
1001_1001
0.59375
0010_0101
1.31875
0100_1100
1.07500
0111_0011
0.83125
1001_1010
0.58750
0010_0110
1.31250
0100_1101
1.06875
0111_0100
0.82500
1001_1011
0.58125
Copyright © 2017 Richtek Technology Corporation. All rights reserved.
DS3662AC-04 July 2017
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
7
RT3662AC
SVID [7:0] Voltage (V)
SVID [7:0]
Voltage (V)
SVID [7:0]
Voltage (V)
SVID [7:0]
Voltage (V)
1001_1100
0.57500
1011_0101 *
0.41875
1100_1110 *
0.26250
1110_0111*
0.10625
1001_1101
0.56875
1011_0110 *
0.41250
1100_1111 *
0.25625
1110_1000*
0.10000
1001_1110
0.56250
1011_0111 *
0.40625
1101_0000 *
0.25000
1110_1001*
0.09375
1001_1111
0.55625
1011_1000 *
0.40000
1101_0001 *
0.24375
1110_1010*
0.08750
1010_0000
0.55000
1011_1001 *
0.39375
1101_0010 *
0.23750
1110_1011*
0.08125
1010_0001
0.54375
1011_1010 *
0.38750
1101_0011 *
0.23125
1110_1100*
0.07500
1010_0010
0.53750
1011_1011 *
0.38125
1101_0100 *
0.22500
1110_1101*
0.06875
1010_0011
0.53125
1011_1100 *
0.37500
1101_0101 *
0.21875
1110_1110*
0.06250
1010_0100
0.52500
1011_1101 *
0.36875
1101_0110 *
0.21250
1110_1111*
0.05625
1010_0101
0.51875
1011_1110 *
0.36250
1101_0111 *
0.20625
1111_0000*
0.05000
1010_0110
0.51250
1011_1111 *
0.35625
1101_1000 *
0.20000
1111_0001*
0.04375
1010_0111
0.50625
1100_0000 *
0.35000
1101_1001 *
0.19375
1111_0010*
0.03750
1010_1000 *
0.50000
1100_0001 *
0.34375
1101_1010 *
0.18750
1111_0011*
0.03125
1010_1001 *
0.49375
1100_0010 *
0.33750
1101_1011 *
0.18125
1111_0100*
0.02500
1010_1010 *
0.48750
1100_0011 *
0.33125
1101_1100 *
0.17500
1111_0101*
0.01875
1010_1011 *
0.48125
1100_0100 *
0.32500
1101_1101 *
0.16875
1111_0110*
0.01250
1010_1100 *
0.47500
1100_0101 *
0.31875
1101_1110 *
0.16250
1111_0111*
0.00625
1010_1101 *
0.46875
1100_0110 *
0.31250
1101_1111 *
0.15625
1111_1000*
0.00000
1010_1110 *
0.46250
1100_0111 *
0.30625
1110_0000*
0.15000
1111_1001*
OFF
1010_1111 *
0.45625
1100_1000 *
0.30000
1110_0001*
0.14375
1111_1010*
OFF
1011_0000 *
0.45000
1100_1001 *
0.29375
1110_0010*
0.13750
1111_1011*
OFF
1011_0001 *
0.44375
1100_1010 *
0.28750
1110_0011*
0.13125
1111_1100*
OFF
1011_0010 *
0.43750
1100_1011 *
0.28125
1110_0100*
0.12500
1111_1101*
OFF
1011_0011 *
0.43125
1100_1100 *
0.27500
1110_0101*
0.11875
1111_1110*
OFF
1011_0100 *
0.42500
1100_1101 *
0.26875
1110_0110*
0.11250
1111_1111*
OFF
* Indicates TOB is 80mV for this VID code; unconditional VR controller stability required at all VID codes
Copyright © 2017 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS3662AC-04 July 2017
RT3662AC
Table 2. SET1 Pin Setting for VDD Controller AI Gain Ratio and VDDNB Voltage Reporting Offset
SET1 Pin Setting Voltage
RD
VSET1_DIV 3.2
RU RD
AI_VDD
VDDNB_RPT_OFS
[3:1] bits
Min
Typical
Max
Unit
6.75
25
43.25
mV
000
57.25
75
92.75
mV
001
107.75
125
142.25
mV
010
158.25
175
191.75
mV
208.75
225
241.25
mV
259.25
275
290.75
mV
101
309.75
325
340.25
mV
110
360.25
375
389.75
mV
111
410.75
425
439.25
mV
000
461.25
475
488.75
mV
001
511.75
525
538.25
mV
010
562.25
575
587.75
mV
612.75
625
637.25
mV
663.25
675
686.75
mV
101
713.75
725
736.25
mV
110
764.25
775
785.75
mV
111
814.75
825
835.25
mV
000
865.25
875
884.75
mV
001
915.75
925
934.25
mV
010
966.25
975
983.75
mV
1016.75
1025
1033.25
mV
1067.25
1075
1082.75
mV
101
1117.75
1125
1132.25
mV
110
1168.25
1175
1181.75
mV
111
1218.75
1225
1231.25
mV
000
1269.25
1275
1280.75
mV
001
1319.75
1325
1330.25
mV
010
1370.25
1375
1379.75
mV
1420.75
1425
1429.25
mV
1471.25
1475
1478.75
mV
101
1521.75
1525
1528.25
mV
110
1572.25
1575
1577.75
mV
111
25%
50%
100%
0LL
011
100
011
100
011
100
011
100
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9
RT3662AC
Table 3. SET1 Pin Setting for VDDNB Controller AI Gain Ratio, VDD Controller QR Threshold
SET1 Pin Setting Voltage VSET1_IR 80μ
RU RD
RU RD
AI_VDDNB
QR Threshold
(VDD)
Min
Typical
Max
Unit
7.84
50
92.16
213.2
250
286.8
315.88
350
384.12
25mV
418.56
450
481.44
Disable
623.92
650
676.08
726.6
750
773.4
829.28
850
870.72
1034.64
1050
1065.36
1137.32
1150
1162.68
25mV
1240
1250
1260
Disable
1445.36
1450
1454.64
1548.04
1550
1551.96
Disable
20mV
25%
20mV
50%
25mV
mV
Disable
20mV
100%
20mV
0LL
25mV
Table 4. TSEN Pin Setting for the Frequency of VDD/VDDNB Controller, VDD Controller Initial Offset and
PHOCP Setting Ratio
TSEN Pin Setting Voltage
RD
VTSEN_DIV 3.2
RU RD
Min
Typical
Max
Unit
6.75
25
43.25
mV
57.25
75
92.75
mV
208.75
225
241.25
mV
259.25
275
290.75
mV
410.75
425
439.25
mV
461.25
475
488.75
mV
612.75
625
637.25
mV
663.25
675
686.75
mV
814.75
825
835.25
mV
865.25
875
884.75
mV
1016.75
1025
1033.25
mV
1067.25
1075
1082.75
mV
1218.75
1225
1231.25
mV
1269.25
1275
1280.75
mV
1420.75
1425
1429.25
mV
1471.25
1475
1478.75
mV
PHOCP_TH = OCP_SPIKE × (PHOCP Setting Ratio) / M
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VDD PHOCP
Frequency
Initial Offset Setting Ratio
(VDD/VDDNB)
(VDD)
(Percentage of
OCP_SPIKE)
25mV
0mV
300kHz
25mV
50mV
25mV
0mV
400kHz
25mV
50mV
150%
200%
150%
200%
150%
200%
150%
200%
150%
200%
150%
200%
150%
200%
150%
200%
(M : Phase Number)
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DS3662AC-04 July 2017
RT3662AC
Table 5. TSEN_NB Pin Setting for VDDNB Controller Initial Offset, Voltage Reporting Offset and PHOCP
Setting Ratio
TSEN_NB Pin Setting Voltage
RD
VTSEN_NB_DIV 3.2
RU RD
Initial Offset
(VDDNB)
Min
Typical
Max
Unit
6.75
25
43.25
mV
57.25
75
92.75
mV
107.75
125
142.25
mV
158.25
175
191.75
mV
208.75
225
241.25
mV
259.25
275
290.75
mV
309.75
325
340.25
mV
360.25
375
389.75
mV
410.75
425
439.25
mV
461.25
475
488.75
mV
511.75
525
538.25
mV
562.25
575
587.75
mV
612.75
625
637.25
mV
663.25
675
686.75
mV
713.75
725
736.25
mV
764.25
775
785.75
mV
814.75
825
835.25
mV
865.25
875
884.75
mV
915.75
925
934.25
mV
966.25
975
983.75
mV
1016.75
1025
1033.25
mV
1067.25
1075
1082.75
mV
1117.75
1125
1132.25
mV
1168.25
1175
1181.75
mV
1218.75
1225
1231.25
mV
1269.25
1275
1280.75
mV
1319.75
1325
1330.25
mV
1370.25
1375
1379.75
mV
1420.75
1425
1429.25
mV
1471.25
1475
1478.75
mV
1521.75
1525
1528.25
mV
1572.25
1575
1577.75
mV
25mV
(PS0)
VDDNB_RPT
_OFS [0]
0
1
0
0mV
(PS0)
1
0
25mV
(PS0)
1
0
50mV
(PS0)
1
0
Fixed 1.5V
(PS2)
1
0
Fixed 1.35V
(PS2)
1
0
Fixed 1.25V
(PS2)
1
0
0mV
(PS2)
1
VDDNB PHOCP
Setting Ratio
(Percentage of
OCP_SPIKE_NB)
150%
200%
150%
200%
150%
200%
150%
200%
150%
200%
150%
200%
150%
200%
150%
200%
150%
200%
150%
200%
150%
200%
150%
200%
150%
200%
150%
200%
150%
200%
150%
200%
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RT3662AC
Table 6. VDDNB Voltage Reporting Offset Table
VDDNB_RPT_OFS [3:0]
VDDNB Voltage Reporting Offset
(VDDNB_RPT_OFS) (Bits)
0000
DIMON_NB x 1/128
0001
DIMON_NB x 2/128
0010
DIMON_NB x 3/128
0011
DIMON_NB x 4/128
0100
DIMON_NB x 5/128
0101
DIMON_NB x 6/128
0110
DIMON_NB x 7/128
0111
DIMON_NB x 8/128
1000
DIMON_NB x 9/128
1001
DIMON_NB x 10/128
1010
DIMON_NB x 11/128
1011
DIMON_NB x 12/128
1100
DIMON_NB x 13/128
1101
DIMON_NB x 14/128
1110
DIMON_NB x 15/128
1111
DIMON_NB x 16/128
DIMON_NB
VIMON_NB 0.8
255 (Bits)
0.8
DIMON_NB : VDDNB Current Reporting Digital Code
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is a registered trademark of Richtek Technology Corporation.
DS3662AC-04 July 2017
RT3662AC
Absolute Maximum Ratings
(Note 1)
VCC to GND ------------------------------------------------------------------------------------------------------- −0.3V to 6.5V
PVCC to GND ----------------------------------------------------------------------------------------------------- −0.3V to 6V
RGND to GND----------------------------------------------------------------------------------------------------- −0.3V to 0.3V
BOOTx to PHASEx --------------------------------------------------------------------------------------------- −0.3V to 6V
PHASEx to GND
DC ------------------------------------------------------------------------------------------------------------------- −0.3V to 32V
2V, the IC will enter start-up sequence for both VDD and
VDDNB rail. If the voltage of VCC and EN pin drop below
low threshold, the IC will enter power down sequence and
all the functions will be disabled. Normally, connecting
system power to the EN pin is recommended. The SVID
will be ready in 2ms (max) after the chip has been enabled.
All the protection latches (OVP, OCP, UVP) will be cleared
only after POR = low. The condition of VEN = low will not
clear these latches.
VCC
4.54V
PVCC
4.1V
EN
2V
+ CMP
CMP
+
Table 7. 2-Bit Boot VID Code
Initial Startup VID (Boot VID)
+ CMP
-
Figure 1. Power Ready (POR) Detection
T2
VDD/VDDNB Output Voltage (V)
0
0
1.1
0
1
1.0
1
0
0.9
1
1
0.8
After EN goes high, the RT3662AC starts up and operates
according to the initial settings. Figure 2 shows the
simplified sequence timing diagram. The detailed operation
is described in the following.
Chip EN
T1
SVD
Start-Up Sequence
POR
-
T0
SVC
T3
T4
T5
T6
T7
T8
T9
T10
T11
VIN
VDDIO
PVCC, VCC
SVID
Send
Byte
SVC
SVID
Send
Byte
SVD
VOTF
Complete
VOTF
Complete
SVT
EN
PWROK
CCM
Boot VID
CCM
VDD/
VDDNB
VID
CCM
Boot VID
CCM CCM
VID
CCM
CCM
PGOOD
Figure 2. Simplified Sequence Timing Diagram
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RT3662AC
Description of Figure 2 :
T0: When the VIN power is ready, the RT3662AC will wait
for VCC and PVCC POR.
T1: VDDIO power is ready, and the BOOT VID can be set
by SVC pin and SVD pin, and latched at EN rising edge.
SVT is driven high by the RT3662AC.
T2: The enable signal goes high and all output voltages
ramp up to the Boot VID in CCM. The soft-start slew rate
is 2.5mV/ms.
T3: All output voltages are within the regulation limits and
the PGOOD signal goes high.
T4: The PWROK pin goes high and the SVI2 interface
starts running. The RT3662AC waits for SVID command
from processor.
T5: A valid SVID command transaction occurs between
the processor and the RT3662AC.
T6: The RT3662AC starts VOTF (VID on-the-Fly) transition
according to the received SVID command and send a
VOTF Complete if the VID is greater than BOOT VID and
reaches target VID.
T7: The PWROK pin goes low and the SVI2 interface stops
running. All output voltages go back to the Boot VID in
CCM.
T8: The PWROK pin goes high again and the SVI2
interface starts running. The RT3662AC waits for SVID
command from processor.
T9: A valid SVID command transaction occurs between
the processor and the RT3662AC.
T10: The action is same with T6. The RT3662AC starts
VID on-the-Fly transition and send a VOTF Complete if
the VID up and reaches target VID.
T11: The enable signal goes low and all output voltages
enter soft-shutdown mode. The soft-shutdown slew rate
is 2.5mV/ms.
Power-Down Sequence
If the voltage at the EN pin falls below the enable falling
threshold, the controller is disabled. The voltage at the
PGOOD pin will immediately go low when EN pin signal
goes low, and the controller executes soft-shutdown
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24
operation. The internal digital circuit ramps down the
reference voltage at the same slew rate as that of in softstart, making VDD and VDDNB output voltages gradually
decrease in CCM. The Boot VID information stored in the
internal register is cleared at POR. This event forces the
RT3662AC to check the SVC and SVD inputs for a new
boot VID when the EN voltage goes high again.
PGOOD
The PGOOD is open-drain logic output. It provides the
power good signal when VDD and VDDNB output voltage
are within the regulation limits and no protection is
triggered. The pin is typically tied to 3.3V or 5V power
source through a pull-high resistor. During shutdown state
(EN = low) and the soft-start period, the PGOOD voltage
is pulled low. After a successful soft-start and VDD and
VDDNB output voltages are within the regulation limits,
the PGOOD is released high.
The voltage at the PGOOD pin will be pulled low when
any of the following events occurs : over-voltage protection,
under-voltage protection, over-current protection, and logic
low EN voltage. If one rail triggers protection, the PGOOD
will be pull low.
SVI2 Wire Protocol
The RT3662AC complies with AMD’ s Voltage Regulator
Specification, which defines the Serial VID Interface 2.0
(SVI2) protocol. With SVI2 protocol, the processor directly
controls the reference voltage level of each individual
controller channel and determines which controller
operates in power saving mode. The SVI2 interface is a
three-wire bus that connects a single master to one or
above slaves. The master initiates and terminates SVI2
transactions and drives the clock, SVC, and the data, SVD,
during a transaction. The slave drives the telemetry, SVT
during a transaction. The AMD processor is always the
master. The voltage regulator controller (RT3662AC) is
always the slave. The RT3662AC receives the SVID code
and acts accordingly. The SVI protocol supports 20MHz
high speed mode I2C, which is based on SVD data packet.
Table 8 shows the SVD data packet. A SVD packet
consists of a “Start” signal, three data bytes after each
byte, and a “Stop” signal. The 8-bit serial VID codes are
listed in Table1. After the RT3662AC has received the stop
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RT3662AC
sequence, it decodes the received serial VID code and
executes the command. The controller has the ability to
sample and report voltage and current for the VDD and
VDDNB domains. The controller reports this telemetry
serially over the SVT wire which is clocked by the
processor driven SVC. A bit TFN at SVD packet along
with the VDD and VDDNB domain selector bits are used
by the processor to change the telemetry functionality.
The telemetry bit definition is listed in Figure 3. The detailed
SVI2 specification is outlined in the AMD Voltage Regulator
and Voltage Regulator Module (VRM) and Serial VID
Interface 2.0 (SVI2) Specification.
Table 8. SVD Data Packet
Bit Time
Description
1:5
8
Always 11000b
VDD domain selector bit, if set then the following two data bytes contain the VID, the PSI state,
and the load-line slope trim and offset trim state for VDD.
VDDNB domain selector bit, if set then the following two data bytes contain the VID, the PSI
state, and the load-line slope trim and offset trim state for VDDNB.
Always 0b
10
PSI0_L
6
7
11 : 17
VID Code bits [7:1]
19
VID Code bit [0]
20
PSI1_L
21
TFN (Telemetry Functionality)
22 : 24
Load Line Slope Trim [2:0]
25 : 26
Offset Trim [1:0]
Voltage and Current
Mode Selection
Bit Time…… START
1
2
3
VDDNB Voltage Bit in Voltage Only Mode;
Current Bit in Voltage and Current Mode
VDD Voltage Bits
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
STOP
SVC
SVT
Figure 3. Telemetry Bit Definition
PWROK and SVI2 Operation
ramp up/down at the same time.
The PWROK pin is an input pin, which is connected to
the global power good signal from the platform. Logic high
at this pin enables the SVI2 interface, allowing data
transaction between processor and the RT3662AC. Once
the RT3662AC receives a valid SVID code, it decodes the
information from processor to determine which output
plane is going to move to the target VID. The internal DAC
then steps the reference voltage in a controlled slew rate,
making the output voltage shift to the required new VID.
Depending on the SVID code, more than one controller
channel can be targeted simultaneously in the VID
transition. For example, VDD and VDDNB voltages can
If the PWROK input goes low during normal operation,
the SVI2 protocol stops running. The RT3662AC
immediately drives SVT high and modifies all output
voltages back to the Boot VID, which is stored in the
internal register right after the controller is enabled. The
controller does not read SVD and SVC inputs after the
loss of PWROK. If the PWROK input goes high again,
the SVI2 protocol resumes running. The RT3662AC then
waits to decode the SVID command from processor for a
new VID and acts as previously described. The SVI2
protocol is only runs when the PWROK input goes high
after the voltage at the EN pin goes high.
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RT3662AC
VID On-the-Fly Transition
Table 9. VDD VR Power State
After the RT3662AC has received a valid SVID code, it
executes the VID on-the-Fly transition by stepping up/
down the reference voltage of the required controller channel
in a controlled slew rate, hence allowing the output voltage
to ramp up/down to target VID.
During the VID on-the-Fly transition, the RT3662AC will
force CCM operation in high performance mode. If the
controller channel operates in the power-saving mode prior
to the VID on-the-Fly transition, it will change to high
performance mode and implement CCM operation when
the controller implement VID up, and then remain in high
performance mode; if the controller implement VID down
in power-saving mode, it will decay down and keep in
power-saving mode. The voltage at the PGOOD pin will
keep high during the VID on-the-Fly transition. The
RT3662AC send a VOTF complete only at the end of VID
up transition. In the event of receiving a VID off code, the
RT3662AC steps the reference voltage of required controller
channel down to zero, hence making the required output
voltage decrease to zero, and the voltage at the PGOOD
pin will remain high since the VID code is valid.
Power State Transition
The RT3662AC supports power state transition function
in VDD and VDDNB VR for the PSI[x]_L command from
AMD processor. The PSI[x]_L bit in the SVI2 protocol
controls the operating mode of the RT3662AC controller
channels. The default operation mode of VDD and VDDNB
VR is full-phase CCM.
When the VDD VR is in N phase configuration and receives
PSI0_L = 0 and PSI1_L = 0 or 1, the VDD VR will entry 1phase diode emulation mode. When the VDD VR receives
PSI0_L = 1 and PSI1_L = 0, the VDD VR remains 1-phase
diode emulation mode. In reverse, the VDD VR goes back
to N phase operation in CCM upon receiving PSI0_L = 1
and PSI1_L = 1, see Table 9. When the VDDNB VR
receives PSI0_L = 0 and PSI1_L = 0 or 1, it enters 1phase diode emulation mode. If the VDDNB VR receives
PSI0_L = 1 and PSI1_L = 0, it remains 1-phase diode
emulation mode. The VDDNB VR will go back to 1-phase
CCM operation after receiving PSI0_L = 1 and PSI1_L =
1, see Table 10.
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Full Phase
Number
PSI0_L : PSI1_L
Mode
11
2 phase CCM
10
2
01
1 phase DEM
00
11
1 phase CCM
10
1
1 phase DEM
01
00
Table 10. VDDNB VR Power State
Full Phase
PSI0_L : PSI1_L
Mode
Number
11
1 phase CCM
10
1
01
1 phase DEM
00
Differential Remote Sense Setting
The VDD and VDDNB controllers have differential, remotesense inputs to eliminate the effects of voltage drops along
the PC board traces, processor internal power routes and
socket contacts. The processor contains on-die sense
pins, including of VDD_SENSE, VDDNB_SENSE and
VSS_SENSE. Connect RGND to VSS_SENSE. For VDD
controller, connect FB to VDD_SENSE with a resistor to
build the negative input path of the error amplifier. Connect
FB_NB to VDDNB_SENSE with a resistor using the same
way in VDD controller. Connect VSS_SENSE to RGND
using separate trace as shown in Figure 4. The precision
reference voltages refer to RGND for accurate remote
sensing.
Processor
VDD_SENSE VDDNB_SENSE
VDD
Controller
FB
FB_NB
RGND
RGND
VDDNB
Controller
VSS_SENSE
Figure 4. Differential Remote Voltage Sense Connection
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DS3662AC-04 July 2017
RT3662AC
SET1 Pin Setting
The RT3662AC provides the SET1 pin for platform users
to set the VDD and VDDNB controller current gain ratio
(AI_VDD, AI_VDDNB), VDD controller QR threshold
(QR_TH) and VDDNB voltage reporting offset bit[1:3]
(VDDNB_RPT_OFS). Platform designers should use
resistive voltage divider on the pin, refer to Figure 5. The
voltage (VREF) at VREF_PINSET pin will be pulled up to
3.2V for SET1 pin setting after power ready (POR), and
then the voltage will change and fix to 0.8V with a delay
time for normal operation.
RD
RU RD
The ADC monitors and decodes the voltage at this pin
only once after power up. After ADC decoding (only once),
a 80μA current (when VCC = 5V) will be generated at the
SET1 pin for pin setting. That is the voltage at SET1 pin
described as below:
VSET1_IR 80
RU RD
RU RD
AI_VDD,
AI_VDDNB
QR_TH
80µA
(VCC = 5V)
VREF
ADC
VSET1_DIV
SET1
Register
SET1
VSET1_IR
RU
RD
Figure 5. SET1 Pin Setting
TSEN and TSEN_NB Pin Setting
The RT3662AC provides the TSEN and TSEN_NB pins
for platform users to set the pin setting functions, including
the VDD and VDDNB controller switching frequency (FSW),
Initial offset, Per-phase over current protection (PHOCP)
and VDDNB voltage reporting offset bit[0]
(VDDNB_RPT_OFS). Platform designers should use
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DS3662AC-04 July 2017
VTSEN_DIV 3.2
Rp2
Rp1 Rp2
Rp4
Rp3 Rp4
The ADC monitors and decodes the voltage at this pin
only once after power up. After ADC decoding (only once),
a 80mA current (when VCC = 5V) will be generated at the
TSEN and TSEN_NB pin for thermal indicator and
protection functions.
From equation (3) and (4) and Table 4 and 5, platform
users can set the above described pin setting functions.
Thermal Indicator
From equation (1) and (2) and Table 2 and 3, platform
users can set the above described pin setting functions.
VDDNB_RPT
_COMP[1:3]
The divided voltage at the TSEN and TSEN_NB pin
described as below:
VTSEN_NB_DIV 3.2
The divided voltage at the SET1 pin as below :
VSET1_DIV 3.2
resistive voltage divider on the pins, refer to Figure 6. The
voltage (VREF) at VREF_PINSET pin will be pulled up to
3.2V for TSEN and TSEN_NB pin setting after power ready
(POR), and then the voltage will change and fix to 0.8V
with a delay time for normal operation.
Refer to Figure 6, the RT3662AC provides the thermal
indicator function. The VRHOT_L pin is an open-drain
output which is used for VR thermal indicator. When the
sensed voltage at TSEN or TSEN_NB pin is less than
2.2V, the VRHOT_L signal will be pulled low to notify CPU
that the temperature is over the VRHOT temperature
threshold.
After TSEN and TSEN_NB pin setting, a 80mA current
(when VCC = 5V) will be generated at the TSEN and
TSEN_NB pin for thermal indicator function. And the
voltage at TSEN and TSEN_NB pin as below:
R R
Rp2
Rp1 Rp2
VTSEN 80 A 1 NTC
VREF
R1 RNTC Rp1 Rp2
Rp1 Rp2
R R
Rp3 Rp4
VTSEN_NB 80 A 2 NTC
R
R
NTC Rp3 Rp4
2
Rp4
VREF
R
R
p4
p3
Due to the VREF reference voltage cause the thermal
compensation become complex. In this way, the sensed
voltage related VREF will be eliminated in ADC block.
The actual sensed voltage at TSEN and TSEN_NB pin
described as below:
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RT3662AC
R R
Rp1 Rp2
VTSEN_ADC 80 A 1 NTC
R
R
NTC Rp1 Rp2
1
CCRCOT on-time generator. When load current increases
(VCS increases), the steady state COMP voltage also
increases and induces VVDD_SENSE to decrease, thus
achieving AVP. A near -DC offset canceling is added to
the output of EA to eliminate the inherent output offset of
finite gain peak current mode controller.
R R
Rp3 Rp4
VTSEN_NB_ADC 80 A 2 NTC
R
R
NTC Rp3 Rp4
2
VDDIO
VIN
VRHOT_L
Thermal
Monitor
80µA
(VCC = 5V)
VREF
ADC
2.2V
VTSEN
Register
RNTC
Rp1
TSEN
R1
VTSEN_DIV
Rp2
80µA
(VCC = 5V)
VTSEN_NB
Driver
R2
0.75 x AI_VDD
+
1.867m
-
Offset
Canceling
VDD Controller
Active Phase Determination
The number of active phases is determined by the internal
circuitry that monitors the ISEN2P voltage during startup. Normally, the VDD controller operates as a 2-phase
PWM controller. Pulling ISEN2P to VCC programs a 1phase operation. At EN rising edge, VDD controller detects
whether the voltage of ISEN2P is higher than “ VCC 0.5V” to decide how many phases should be active and
the active phase number is determined and latched.
Loop Control
The VDD controller adopts Richtek’s proprietary GNAVPTM topology. The G-NAVPTM is based on the finite
gain peak current mode with CCRCOT (Constant Current
Ripple Constant On-Time) topology. The output voltage,
VVDD will decrease with increasing output load current.
The control loop consists of PWM modulators with power
stages, current sense amplifiers and an error amplifier as
shown in Figure 7.
Similar to the peak current mode control with finite
compensator gain, the HS_FET on-time is determined by
Copyright © 2017 Richtek Technology Corporation. All rights reserved.
EA
+
CX
VVDD
RC
RX2
ISENxP
ISENxN
IMON
C
RIMON
VREF_PINSET
C2
C1
COMP
FB
RGND
R2
R1
VVDD_SENSE
VSS_SENSE
VDAC
Rp4
Figure 6. TSEN and TSEN_NB Circuit
RX1
LS_FET
VCS
+
Rp3
TSEN_NB
RSENSE
L
CCRCOT
PWM
Logic
VREF
RNTC
VTSEN_NB_DIV
www.richtek.com
28
HS_FET
PROCHOT_L
+
CMP
-
PHOCP
FSW
COMP2
VDDNB_RPT Initial
_COMP[0] Offset
Figure 7. VDD Controller: Simplified Schematic with
Voltage Loop and Current Loop
Current Signal Sensing
Refer to Figure 7, for different RSENSE resistor, the current
sense method can classify as two types. The method1
only use RX1 for lower RSENSE application, and the method2
use RX1 and RX2 to divide the current signal for higher
RSENSE application. Richtek also provide Excel based
design tool to let user choose the appropriate components
quickly.
The current sense topology of the VDD controller is
continuous inductor current sensing. Therefore, the
controller has less noise sensitive. Low offset amplifiers
are used for current balance, loop control and over current
detection. The ISENxP and ISEN1N pins denote the
positive and negative input of the current sense amplifier.
In order to optimize transient performance, the
recommended Req and CX will be set according to the
equations as below, t recommended set to 1.1.
R eq C X
L
RSENSE
Method1 : Req = RX1
Method1 : Req R X1 R X2
R X1 R X2
is a registered trademark of Richtek Technology Corporation.
DS3662AC-04 July 2017
RT3662AC
Considering the inductance tolerance, the resistor Req has
to be tuned on board by examining the transient voltage.
If the output voltage transient has an initial dip below the
minimum load-line requirement and the response time is
too fast causing a ring back, the value of resistance should
be increased. Vice versa, with a high resistance, the output
voltage transient has only a small initial dip with a slow
response time. RX is highly recommended as two 0603
size resistors in series to enhance the Iout reporting
accuracy. CX is suggested X7R type for the application.
Droop Setting
It is very easy to achieve Active Voltage Positioning (AVP)
by properly setting the error amplifier gain due to the native
droop characteristics as shown in Figure 8. This target is
to have
VVDD = VDAC - ILOAD x RDROOP
Then solving the switching condition VCOMP2 = VCS in
Figure 7 yields the desired error amplifier gain as
Optimized compensation of the VDD controller allows for
best possible load step response of the regulator’s output.
A type-I compensator with one pole and one zero is
adequate for proper compensation. Figure 9 shows the
compensation circuit. Previous design procedure shows
how to select the resistive feedback components for the
error amplifier gain. Next, C1 and C2 must be calculated
for compensation. The target is to achieve constant
resistive output impedance over the widest possible
frequency range.
The pole frequency of the compensator must be set to
compensate the output capacitor ESR zero:
1
2 C RC
fP
Where C is the capacitance of output capacitor, and RC is
the ESR of output capacitor. C2 can be calculated as
follows:
C2
GI
A V R2
R1 RDROOP
GI RSENSE 1.867m RIMON 0.75 AI_VDD
GI RSENSE
Loop Compensation
R X2
1.867m RIMON 0.75 AI_VDD
R X1 R X2
VVDD
The zero of compensator has to be placed at half of the
switching frequency to filter the switching related noise.
Such that,
C1
1
R1 fSW
COMP
EA
+
C2
C1
R2
R1
FB
+
Where GI is the current sense amplifier gain. RSENSE is
the current sense resistor. If no external sense resistor
present, it is the equivalent resistance of the inductor.
RIMON is the IMON equivalent resistance. For the PHOCP
accuracy, the RIMON resistor need to set in 8kΩ to 70kΩ.
AI_VDD is the VDD controller current gain ratio set by
SET1 pin setting. RDROOP is the equivalent load-line
resistance as well as the desired static output impedance.
C RC
R2
RGND
VVDD_SENSE
VSS_SENSE
VDAC
Figure 9. VDD Controller: Compensation Circuit
AV2 > AV1
Current Balance
AV2
AV1
0
Load Current
Figure 8. VDD Controller: Error Amplifier gain (AV)
Influence on VVDD Accuracy
Copyright © 2017 Richtek Technology Corporation. All rights reserved.
DS3662AC-04 July 2017
The VDD controller implements internal current balance
mechanism in the current loop. The VDD controller senses
and compares per-phase current signal with average
current. If the sensed current of any particular phase is
larger than average current, the on-time of this phase will
be adjusted to be shorter.
is a registered trademark of Richtek Technology Corporation.
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29
RT3662AC
Figure 10 is the recommended current balance circuit for
two phase application due to RPCB1 and RPCB2 are difficult
to control very close. Detail derivative equations are as
below.
V1P +V2
VISEN1P =
2
VISEN2P =
VA =
V2P +V1
2
V1P -V1
2
- V1
2
V1P
- V1
2
=
V2P
=
Dynamic VID Enhancement
V2P -V2
V2P-1N = VISEN2P -VA =
VINI_OFS is the initial offset voltage set by pin setting
function, and the dynamic offset voltage, VDYN_OFS,
controlled by CPU, and it can be set through the SVI2
interface.
V1+V2
V1P
During a dynamic VID event, the charging (dynamic VID
up) or discharging (dynamic VID down) current causes
unwanted load-line effect which degrades the settling time
performance. The RT3662AC will hold the inductor current
to hold the load-line during a dynamic VID event. The VDD
controller will always enter full-phase configuration when
it receives dynamic VID up command; If VDD controller
receives dynamic VID down command, it will hold the
operating state.
2
- V2
2
V2P
- V2
2
IL1 x DCR1 = IL2 x DCR2
When the VID CCM down on light loading condition, the
negative inductor current will be produced, and it may
cause the audio noise and phase ring effect. For improving
the problems, the controller set the dynamic VID down
slew rate to 0.625mV/ms, the action will reduce the
negative current and phase ring effect.
VIN
V1
V1P
ISEN1P
RISEN
V1P-1N
RPCB1
DCR1
RISEN
VISEN1P
+
1
ISEN1N
VDD
Va
VIN
LOAD
1 V2
V2P
V2P-1N
DCR2
RPCB2
RISEN
+
ISEN2P
RISEN
VISEN2P
Figure 10. Recommended Current Balance Circuit for
Two Phase Application
Copyright © 2017 Richtek Technology Corporation. All rights reserved.
www.richtek.com
30
The VDD controller features initial and dynamic offset
function. The VDD rail initial offset function can be
implemented through the TSEN pin setting. And the
dynamic offset can be implemented by SVI2 interface, it
controlled by CPU. Consider the offset factor, the VDD
output voltage described as below:
VVDD VDAC ILOAD RDROOP VINI_OFS VDYN_OFS
2
V1P-1N = VISEN1P -VA =
Initial and Dynamic Offset
Ramp Compensation
G-NAVPTM topology is one type of ripple based control
that has fast transient response. However, ripple based
control usually don’ t have good noise immunity. The
RT3662AC provides a ramp compensation to increase
noise immunity and reduce jitter at the switching node,
refer to Figure 11 shows the ramp compensation. When
the VDD controller takes phase shedding operation and
enters diode emulation mode, the internal ramp of VDD
controller will be modified for the reason of stability.
is a registered trademark of Richtek Technology Corporation.
DS3662AC-04 July 2017
RT3662AC
W/O ramp compensation
VO
Noise Margin
VREF
VCOMP - VCS
PWM
With ramp compensation
VO
Noise Margin
VRAMP
VCOMP - VCS
Quick Response
When the transient load step-up becomes quite large, it
is difficult for loop response to meet the energy transfer.
Hence, the output voltage generate undershoot to fail
specification. The RT3662AC has Quick Response (QR)
mechanism which is able to improve this issue. It adopts
a nonlinear control mechanism which can disable
interleaving function and simultaneously turn on all UGATE
one pulse at instantaneous step-up transient load to
restrain the output voltage drooping. The output voltage
signal behavior needs to be detected so that QR
mechanism can be trigged. Refer to Figure 12, the output
voltage signal is via a remote sense line to connect at the
VSEN pin. The QR threshold can be set by SET1 pin
setting for VDD controller refers to Table 3.
PWM
QR_TH
CMP
+
+
Figure 11. Ramp Compensation
QR Pulse
Generation
Circuit
VSEN
Current Monitoring and Reporting
The VDD controller provides current monitoring function
via inductor current sensing. In the G-NAVPTM technology,
the output voltage is dependent on output current, and
the current monitoring function is achieved by this
characteristic of output voltage. The equivalent output
current will be sensed from inductor current sensing and
mirrored to the IMON pin. The resistor connected to the
IMON pin determines voltage of the IMON output.
For Method1 current sensing :
VIMON IL,SUM DCRL 1.867m RIMON 0.8
Where IL,SUM is the VDD output current, DCRL is the current
sense resistance, RIMON is the IMON pin equivalent setting
resistor, and the current sense gain equal to 1.867m.
The ADC circuit of the VDD controller monitors the voltage
variation at the IMON pin, and this voltage is decoded into
digital format and stored into output current register.
DIMON
Figure 12. VDD Controller: Quick Response Triggering
Circuit
Over-Current Protection
The RT3662AC provides the over current protection
function. The OCP_SPIKE threshold will be set by the
current monitor resistor RIMON as below :
For Method1 current sensing :
OCP_SPIKE
1.6 0.8
DCRL 1.867m RIMON
For prevent the OCP false trigger, the trigger delay is
requirement, refer to Electrical Characteristics. When
output current is still higher than the OCP_SPIKE after
the trigger delay time, the OCP will be latched, and then
the VDD controller will turn off both high-side and low-side
MOSFETs of all channels.
VIMON 0.8
255 (Bits)
0.8
Copyright © 2017 Richtek Technology Corporation. All rights reserved.
DS3662AC-04 July 2017
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
31
RT3662AC
Per-Phase Over Current Protection
The VDD controller provides per-phase over current
protection (PHOCP) function in each phase. If the VDD
controller force 1 phase operation by pulling ISEN2P pin
to 5V, it only detected at soft-start duration when VR power
on. The VDD PHOCP threshold is set by TSEN pin setting
described as below :
PHOCP_TH OCP_SPIKE
N
M
N is the VDD PHOCP setting ratio, M is the operation
phase number.
If the PHOCP is triggered, the controller will turn off all
high-side and low-side MOSFETs to protect CPU.
Over-Voltage Protection (OVP)
The OVP circuit of the VDD controller monitors the output
voltage via the VSEN pin after POR. When the VSEN
voltage exceeds the OVP threshold 1.85V, OVP is
triggered and latched. The VDD controller will try to turn
on low-side MOSFET and turn off high-side MOSFET of
all active phases to protect the CPU. When OVP is
triggered by one rail, the other rail will also enter soft shut
down sequence. A 1ms delay is used in OVP detection
circuit to prevent false trigger.
VDDNB Controller
VDDNB Controller Disable
The VDDNB controller can be disabled by connecting
ISENP_NB to a voltage higher than “VCC - 0.5V”. If not
in use, ISENN_NB is recommended to be connected to
VCC. When VDDNB controller is disabled, all SVID
commands related to VDDNB controller will be rejected.
Loop Control
The VDDNB controller adopts Richtek’s proprietary GNAVPTM topology. The G-NAVPTM is based on the finite
gain peak current mode with CCRCOT (Constant Current
Ripple Constant On-Time) topology. The output voltage,
VVDDNB will decrease with increasing output load current.
The control loop consists of PWM modulators with power
stages, current sense amplifiers and an error amplifier as
shown in Figure 13.
Similar to the peak current mode control with finite
compensator gain, the HS_FET on-time is determined by
CCRCOT on-time generator. When load current increases,
VCS increases, the steady state COMP voltage also
increases and induces VVDDNB_SENSE to decrease, thus
achieving AVP. A near-DC offset canceling is added to the
output of EA to eliminate the inherent output offset of finite
gain peak current mode controller.
Under-Voltage Protection (UVP)
VIN
HS_FET
L
CCRCOT
PWM
Logic
+
CMP
COMP2
The VDD controller implements UVP of VSEN pin. If VSEN
voltage is less than the internal reference by 500mV, the
VDD controller will trigger UVP latch. The UVP latch will
turn off both high-side and low-side MOSFETs. When UVP
is triggered by one rail, the other rail will also enter soft
shutdown sequence. A 3ms delay is used in UVP detection
circuit to prevent false trigger.
Driver
VCS
0.75 x AI_VDDNB
+
www.richtek.com
32
VVDDNB
CX
RX2
ISENP_NB
RC
C
1.867m ISENN_NB
-
IMON_NB RIMON_NB
Offset
Canceling
VREF_PINSET
C2
C1
COMP_NB
FB_NB
R2
R1
EA
+
+
Copyright © 2017 Richtek Technology Corporation. All rights reserved.
RX1
LS_FET
Under-Voltage Lock Out (UVLO)
During normal operation, if the voltage at the VCC pin
drops below IC POR threshold, the VDD controller will
trigger UVLO. The UVLO protection forces all high-side
and low-side MOSFETs off by shutting down internal PWM
logic drivers. A 3ms delay is used in UVLO detection
circuit to prevent false trigger.
RSENSE
RGND
VVDDNB_SENSE
VSS_SENSE
VDAC
Figure 13. VDDNB Controller : Simplified Schematic
with Voltage Loop and Current Loop
is a registered trademark of Richtek Technology Corporation.
DS3662AC-04 July 2017
RT3662AC
Current Sense Setting
Refer to Figure 13, for different RSENSE resistor, the current
sense method can classify as two types. The method1
only use RX1 for lower RSENSE application, and the method2
use RX1 and RX2 to divide the current signal for higher
RSENSE application. Richtek also provide Excel based
design tool to let user choose the appropriate components
quickly.
The current sense topology of the VDDNB controller is
continuous inductor current sensing. Therefore, the
controller has less noise sensitive. Low offset amplifiers
are used for loop control and over current detection. The
ISENP_NB and ISENN_NB pins denote the positive and
negative input of the current sense amplifier.
In order to optimize transient performance, the
recommended Req and CX will be set according to the
equation as below, and t recommended set to 1.1.
R eq C X
GI
A V R2
R1 RDROOP
Method1:
GI RSENSE 1.867m RIMON 0.75 AI_VDDNB
Method2:
GI RSENSE
R X2
1.867m RIMON 0.75 AI_VDDNB
R X1 R X2
Where GI is the current sense amplifier gain. RSENSE is
the current sense resistor. If no external sense resistor
present, it is the equivalent resistance of the inductor.
RIMON_NB is the IMON_NB equivalent resistance. For the
PHOCP accuracy, the RIMON_NB resistor need to set in
8kΩ to 70kΩ. AI_VDDNB is the VDDNB controller current
gain ratio set by SET1 pin setting. RDROOP is the equivalent
load-line resistance as well as the desired static output
impedance.
VVDDNB
L
RSENSE
AV2 > AV1
Method1 : Req R X1
AV2
R X1 R X2
Method2 : R eq R R
X1
X2
Considering the inductance tolerance, the resistor Req has
to be tuned on board by examining the transient voltage.
If the output voltage transient has an initial dip below the
minimum load-line requirement and the response time is
too fast causing a ring back, the value of resistance should
be increased. Vice versa, with a high resistance, the output
voltage transient has only a small initial dip with a slow
response time. RX is highly recommended as two 0603
size resistors in series to enhance the Iout reporting
accuracy. CX is suggested X7R type for the application.
Droop Setting
It is very easy to achieve Active Voltage Positioning (AVP)
by properly setting the error amplifier gain due to the native
droop characteristics as shown in Figure 14. This target
is to have
VVDDNB = VDAC - ILOAD x RDROOP
Then solving the switching condition VCOMP2 = VCS in
Figure 12 yields the desired error amplifier gain as
Copyright © 2017 Richtek Technology Corporation. All rights reserved.
DS3662AC-04 July 2017
AV1
0
Load Current
Figure 14. VDDNB Controller : Error Amplifier gain (AV)
Influence on VVDDNB Accuracy
Loop Compensation
Optimized compensation of the VDDNB controller allows
for best possible load step response of the regulator’s
output. A type-I compensator with one pole and one zero
is adequate for proper compensation. Figure 15 shows
the compensation circuit. Previous design procedure
shows how to select the resistive feedback components
for the error amplifier gain. Next, C1 and C2 must be
calculated for compensation. The target is to achieve
constant resistive output impedance over the widest
possible frequency range.
The pole frequency of the compensator must be set to
compensate the output capacitor ESR zero :
fP
1
2 C RC
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www.richtek.com
33
RT3662AC
Where C is the capacitance of output capacitor, and RC is
the ESR of output capacitor. C2 can be calculated as
follows :
C2
C x RC
R2
The zero of compensator has to be placed at half of the
switching frequency to filter the switching related noise.
Such that,
C1
1
R1 fSW
COMP_NB
C1
R2
R1
FB_NB
+
EA
+
C2
RGND
VVDDNB_SENSE
VSS_SENSE
VDAC
Figure 15. VDDNB Controller : Compensation Circuit
Initial and Dynamic Offset
The VDDNB controller features initial and dynamic offset
function. The initial offset function can be implemented
through the TSEN pin setting. And the Dynamic offset can
be implemented by SVI2 interface, it controlled by CPU.
Consider the offset factor, the VDDNB output voltage
described as below :
VVDDNB VDAC ILOAD RDROOP
VINI_OFS VDYN_OFS
VINI_OFS is the initial offset voltage set by pin setting
function, and the dynamic offset voltage, VDYN_OFS,
controlled by CPU, and it can be set through the SVI2
interface.
Dynamic VID Enhancement
During a dynamic VID event, the charging (dynamic VID
up) or discharging (dynamic VID down) current causes
unwanted load-line effect which degrades the settling time
performance. The RT3662AC will hold the inductor current
to hold the load-line during a dynamic VID event. The
VDDNB controller will always enter CCM operation when
it receives dynamic VID up command; If VDD controller
receives dynamic VID down command, it will hold the
operating state.
Copyright © 2017 Richtek Technology Corporation. All rights reserved.
www.richtek.com
34
When the VID CCM down on light loading condition, the
negative inductor current will be produced, and it may
cause the audio noise and phase ring effect. For improving
the problems, the controller set the dynamic VID down
slew rate to 0.625mV/ms, the action will reduce the
negative current and phase ring effect.
Ramp Compensation
G-NAVPTM topology is one type of ripple based control
that has fast transient response. However, ripple based
control usually don’t have good noise immunity. The
RT3662AC provides a ramp compensation to increase
noise immunity and reduce jitter at the switching node
refer to Figure 11 shows the ramp compensation. When
the VDDNB controller takes phase shedding operation and
enters diode emulation mode, the internal ramp of VDDNB
controller will be modified for the reason of stability.
Current Monitoring and Reporting
The VDDNB controller provides current monitoring function
via inductor current sensing. In the G-NAVPTM technology,
the output voltage is dependent on output current, and
the current monitoring function is achieved by this
characteristic of output voltage. The equivalent output
current will be sensed from inductor current sensing and
mirrored to the IMON_NB pin. The resistor connected to
the IMON_NB pin determines voltage of the IMON_NB
output.
For Method1 current sensing :
VIMON_NB IL,SUM DCRL 1.867m RIMON_NB 0.8
Where IL,SUM is the VDDNB output current, DCRL is the
current sense resistance, RIMON_NB is the IMON_NB pin
equivalent setting resistor, and the current sense gain equal
to 1.867m.
The ADC circuit of the VDDNB controller monitors the
voltage variation at the IMON_NB pin, and this voltage is
decoded into digital format and stored into output current
register.
DIMON_NB
VIMON_NB 0.8
0.8
255 (Bits)
is a registered trademark of Richtek Technology Corporation.
DS3662AC-04 July 2017
RT3662AC
VDDNB Voltage Reporting Offset
The VDDNB controller senses the ISENN_NB voltage for
voltage reporting. In Figure 16, due to the PCB trace (RPCB)
from ISENN_NB to output capacitor, it will cause the
voltage drop on loading, as the loading current become
bigger, the drop will affect the voltage reporting seriously.
Through the voltage reporting offset function, it can be
improved, and the voltage reporting of VDDNB controller
(VVDDNB_RPT) can be described as below :
VVDDNB_RPT(d) VISENN_NB_ADC(d) VVDDNB_RPT_OFS(d)
VVDDNB_RPT is the VDDNB voltage reporting digital code,
VISENN_NB_ADC is the ISENN_NB sensed voltage digital
code and VVDDNB_RPT_OFS is the VDDNB voltage reporting
offset bits.
IL
L
RX
ISEN_NB
+
1.867m
-
VVDDNB
DCRL
CX
ISENP_NB
ISENN_NB
Figure 16. The Description of PCB trace from ISENN_NB
to Output Capacitor
Over-Current Protection
The RT3662AC provides the over current protection
function. The OCP_SPIKE_NB threshold will be set by
the current monitor resistor RIMON_NB as below :
For Method1 current sensing :
OCP_SPIKE_NB
1.6 0.8
DCRL 1.867m RIMON_NB
For prevent the OCP false trigger, the trigger delay is
requirement, refer to Electrical Characteristics. When
output current is still higher than the OCP_SPIKE_NB
after the trigger delay time, the OCP will be latched, and
then the VDDNB controller will turn off both high-side and
low-side MOSFETs.
Per-Phase Over Current Protection
The VDDNB controller provides per-phase over current
protection (PHOCP) function, it only detected at soft-start
Copyright © 2017 Richtek Technology Corporation. All rights reserved.
DS3662AC-04 July 2017
duration when VR power on. The PHOCP threshold is set
by TSEN_NB pin setting described as below :
PHOCP_TH = OCP_SPIKE_NB x N
N is the VDDNB PHOCP setting ratio.
If the PHOCP is triggered, the controller will turn off all
high-side and low-side MOSFETs to protect CPU.
Over-Voltage Protection (OVP)
The OVP circuit of the VDDNB controller monitors the
output voltage via the ISENN_NB pin after POR. When
the ISENN_NB voltage exceeds the OVP threshold 1.85V,
OVP is triggered and latched. The VDDNB controller will
try to turn on low-side MOSFET and turn off high-side
MOSFET of all active phases to protect the CPU. When
OVP is triggered by one rail, the other rail will also enter
soft shut down sequence. A 1ms delay is used in OVP
detection circuit to prevent false trigger.
Under-Voltage Protection (UVP)
The VDDNB controller implements UVP of ISENN_NB pin.
If ISENN_NB voltage is less than the internal reference
by 500mV, the VDDNB controller will trigger UVP latch.
The UVP latch will turn off both high-side and low-side
MOSFETs. When UVP is triggered by one rail, the other
rail will also enter soft shutdown sequence. A 3ms delay
is used in UVP detection circuit to prevent false trigger.
Under-Voltage Lock Out (UVLO)
During normal operation, if the voltage at the VCC pin
drops below IC POR threshold, the VDDNB controller will
trigger UVLO. The UVLO protection forces all high-side
and low-side MOSFETs off by shutting down internal PWM
logic drivers. A 3ms delay is used in UVLO detection
circuit to prevent false trigger.
Thermal Considerations
The junction temperature should never exceed the
absolute maximum junction temperature TJ(MAX), listed
under Absolute Maximum Ratings, to avoid permanent
damage to the device. The maximum allowable power
dissipation depends on the thermal resistance of the IC
package, the PCB layout, the rate of surrounding airflow,
and the difference between the junction and ambient
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
35
RT3662AC
27.5°C/W on a standard JEDEC 51-7 high effective-thermalconductivity four-layer test board. The maximum power
dissipation at TA = 25°C can be calculated as below :
temperatures. The maximum power dissipation can be
calculated using the following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA
PD(MAX) = (125°C − 25°C) / (27.5°C/W) = 3.63W for a
WQFN-40L 5x5 package.
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction-to-ambient
thermal resistance.
The maximum power dissipation depends on the operating
ambient temperature for the fixed TJ(MAX) and the thermal
For continuous operation, the maximum operating junction
temperature indicated under Recommended Operating
Conditions is 125°C. The junction-to-ambient thermal
resistance, θJA, is highly package dependent. For a
WQFN-40L 5x5 package, the thermal resistance, θJA, is
resistance, θJA. The derating curves in Figure 17 allows
the designer to see the effect of rising ambient temperature
on the maximum power dissipation.
Maximum Power Dissipation (W)1
4.0
Four-Layer PCB
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 17. Derating Curve of Maximum Power Dissipation
Copyright © 2017 Richtek Technology Corporation. All rights reserved.
www.richtek.com
36
is a registered trademark of Richtek Technology Corporation.
DS3662AC-04 July 2017
RT3662AC
Outline Dimension
D
SEE DETAIL A
D2
L
1
E2
E
e
1
1
2
2
b
DETAIL A
Pin #1 ID and Tie Bar Mark Options
A
A3
A1
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.150
0.250
0.006
0.010
D
4.950
5.050
0.195
0.199
D2
3.250
3.500
0.128
0.138
E
4.950
5.050
0.195
0.199
E2
3.250
3.500
0.128
0.138
e
L
0.400
0.350
0.016
0.450
0.014
0.018
W-Type 40L QFN 5x5 Package
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Customers should obtain the latest relevant information and data sheets before placing orders and should verify
that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek
product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use;
nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent
or patent rights of Richtek or its subsidiaries.
DS3662AC-04 July 2017
www.richtek.com
37
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