RT4812GJ8F

RT4812 High Efficiency Boost Converter General Description Features The RT4812 allows systems to take advantage of new  CMCOT Topology and Small Output Ripple when VIN close VOUT Voltage battery chemistries that can supply significant energy when the battery voltage is lower than the required  Operates from a Single Li-ion Cell : 1.8V to 5.5V voltage for system power ICs. By combining built-in  Adjustable Output Voltage : 1.8V to 5.5V power transistors, synchronous rectification, and low  PSM Operation supply current; this IC provides a compact solution for  Up to 96% Efficiency systems using advanced Li-Ion battery chemistries.  Boost Current Limit  Output Over-Voltage Protection  Pin Adjustable Average Output Current Limit The RT4812 is a boost regulator designed to provide a minimum output voltage from a single-cell Li-Ion battery, Threshold (2 Levels) even when the battery voltage is below system minimum. In boost mode, output voltage regulation is guaranteed to a maximum load current of 2.1A. Quiescent current in Shutdown Mode is less than 1A, which maximizes battery life.  Internal Compensation  Output Discharge  Output Short Protection  True Load Disconnect Applications Ordering Information RT4812 Package Type J8F : TSOT-23-8 (FC)  Single-Cell Li-Ion, LiFePO4 Smart-Phones  Portable Equipment Marking Information Lead Plating System G : Green (Halogen Free and Pb Free) 0L= : Product Code DNN : Date Code 0L=DNN Note : Richtek products are :  RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.  Suitable for use in SnPb or Pb-free soldering processes. Simplified Application Circuit RT4812 L1 SW VIN VOUT VOUT C1 R1 VIN C3 FB C2 R2 EN R3 H/L ILIM Copyright © 2022 Richtek Technology Corporation. All rights reserved. DS4812-09 March 2022 GND is a registered trademark of Richtek Technology Corporation. www.richtek.com 1 RT4812 Pin Configuration EN SW GND 8 7 6 5 2 3 4 FB VOUT PGND VIN ILIM (TOP VIEW) TSOT-23-8 (FC) Functional Pin Description Pin No. Pin Name Pin Function 1 VIN Power input. Input capacitor CIN must be placed as close to IC as possible. 2 FB Voltage feedback. 3 VOUT Boost converter output. 4 PGND Power ground. 5 GND Analog ground. 6 SW Switching node. 7 EN Enable input (1 enabled, 0 disabled), must not be floating. 8 ILIM Average output current limit control pin. (H/L) Functional Block Diagram VOUT VIN SW Control ILIM OCP Gate DRV EN Digital CTRL PWM CTRL SW AMP - FB + OSC OTP PGND Copyright © 2022 Richtek Technology Corporation. All rights reserved. www.richtek.com 2 UVLO VREF GND is a registered trademark of Richtek Technology Corporation. DS4812-09 March 2022 RT4812 Operation The RT4812 combined built-in power transistors, Startup and Shutdown State synchronous rectification, and low supply current, it When VIN is rising and through the LIN state, it will provides a compact solution for system using advanced enter the Startup state. If EN is pulled low, any Li-Ion battery chemistries. function is turned-off in shutdown mode. In boost mode, output voltage regulation is guaranteed Soft-Start State to a maximum load current of 2.1A. Quiescent current in Shutdown mode is less than 1A, which maximizes battery life. It starts to switch in Soft-start state. After the LIN state, output voltage is rising with the internal reference voltage. Depiction Condition Fault State LIN 1 Linear startup 1 VIN > VOUT As the Figure 1 shown, it will enter to the Fault state LIN 2 Linear startup 2 VIN > VOUT as below, Soft-Start Boost soft-start VOUT < VOUT(MIN)  Boost Boost mode VOUT = VOUT(MIN) It will be the high impedance between the input and Mode LIN The timeout of LIN2 is over the 1024s. output when the fault is triggered. A restart will be LIN State start after 20ms. When VIN is rising, it enters the LIN State. There are two parts for the LIN state. It provides maximum OCP current for 1A to charge the COUT in LIN1, and the other one is for 3A in LIN2. By the way, the EN is The converter senses the current signal when the high-side P-MOSFET turns on. As a result, the OCP is cycle-by-cycle current limitation. If the OCP occurs, pulled high and VIN > UVLO. As the figure shown, if the timeout is over the specification, it will enter the Fault mode. the converter holds off the next on pulse until inductor current drops below the OCP limit. OTP EN = 1, Vin > UVLO The converter has an over-temperature protection. When the junction temperature is higher than the thermal shutdown rising threshold, the system will be LIN 1 Timeout < 512μs latched and the output voltage will no longer be Timeout > 512μs regulated until the junction temperature drops under the falling threshold. Soft-Start LIN 2 Timeout < 1024μs Boost mode Input Voltage POR (Power-On Reset) Timeout > 1024μs Fault State Figure 1. RT4812 State Chart The RT4812 is implemented POR function. Power-on reset (POR) function is used to reset IC's status to default. POR function is activated, when VIN is dropped and it should meet POR requirements. POR function may fail if VIN pattern are not meet POR event requirement. POR event requirements are listed below, refer to Figure 2 for the pattern. Copyright © 2022 Richtek Technology Corporation. All rights reserved. DS4812-09 March 2022 is a registered trademark of Richtek Technology Corporation. www.richtek.com 3 RT4812 1. VIN_min < 0.5V 2. Width > 20s 3. SR_rising < 1V/s VIN Width SR_falling SR_rising VIN_min VIN : Input voltage SR_falling : Slew rate for input voltage drop SR_rising : Slew rate for input voltage resume Width : Duration of input voltage drop VIN_min : Minimum voltage Figure 2. POR Pattern Illustration Copyright © 2022 Richtek Technology Corporation. All rights reserved. www.richtek.com 4 is a registered trademark of Richtek Technology Corporation. DS4812-09 March 2022 RT4812 Absolute Maximum Ratings (Note 1)  VIN, FB, ILIM, EN, SW to GND ---------------------------------------------------------------------------------- 0.2V to 6V  VOUT to GND ------------------------------------------------------------------------------------------------------- 6.2V  Power Dissipation, PD @ TA = 25C  TSOT-23-8 (FC) ----------------------------------------------------------------------------------------------------- 1.78W  Package Thermal Resistance (Note 2) TSOT-23-8 (FC), JA ----------------------------------------------------------------------------------------------- 56C/W TSOT-23-8 (FC), JC ----------------------------------------------------------------------------------------------- 28C/W  Lead Temperature (Soldering, 10sec.) ------------------------------------------------------------------------- 260C  Junction Temperature -------------------------------------------------------------------------------------------- 65C to 150C  Storage Temperature Range ------------------------------------------------------------------------------------- 65C to 150C  ESD Susceptibility (Note 3) HBM (Human Body Model) -------------------------------------------------------------------------------------- 2kV Recommended Operating Conditions (Note 4)  Input Voltage Range ---------------------------------------------------------------------------------------------- 1.8V to 5.5V  Output Voltage Range --------------------------------------------------------------------------------------------- 1.8V to 5.5V  Junction Temperature (TJ) Range ------------------------------------------------------------------------------ 40C to 125C  Ambient Temperature (TA) Range ------------------------------------------------------------------------------ 40C to 85C Electrical Characteristics (VIN = 3.6V, TA = 25C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit Supply Voltage VIN VIN  VOUT 0.2V 1.8 -- 5.5 V Output Voltage VOUT VIN  VOUT 0.2V 1.8 -- 5.5 V Under-Voltage Lockout Rising Threshold UVLO_RISE 1.5 1.65 1.8 V Under-Voltage Lockout Falling Threshold UVLO_Falling 1.3 1.55 1.7 V FB Voltage VFB Force PWM 0.495 0.5 0.505 V Regulated DC VOUT Voltage VOUT 1.8  VIN  VOUT  0.2V IOUT = 0mA (PSM) 2 -- 4 % Shutdown Current ISHDN EN = 0V -- 0.1 1 A Close loop, no load FB = 3V, non-switching current -- 90 -- A -- 1 -- A VOUT  VIN > 1V -- 0.5 -- MHz ILIM = L 1 -- -- ILIM = H 2.1 -- -- High-Side Switch Ron VIN = 5V -- 45 -- m Low-Side Switch Ron VIN = 5V -- 30 -- m Quiescent Current Pre-charge Current Ipre Switching Frequency fSW Average Output Current Limit ILIM Copyright © 2022 Richtek Technology Corporation. All rights reserved. DS4812-09 March 2022 A is a registered trademark of Richtek Technology Corporation. www.richtek.com 5 RT4812 Parameter Symbol Test Conditions Min Typ Max Unit 1 -- 1 A FB Pin Input Leakage IFB Leakage of SW ISW All switch off -- -- 5 A Line Regulation VOUT, LINE VIN = 2.7V to 4.5V, VOUT = 5V, IOUT = 1500mA 2 -- 2 % Load Regulation VOUT, LOAD CCM, IOUT  2A, VIN = 3.6V, VOUT = 5V 1.5 -- 1.5 % Output Over Voltage Protection VOVP 5.8 6 6.2 V EN Input Low Voltage VIL -- -- 0.4 V EN Input High Voltage VIH 1.2 -- -- V -- 0.1 1 A EN Sink Current Thermal Shutdown TSD -- 160 -- C Thermal Shutdown Hysteresis TSD -- 30 -- C Note 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. JA is measured at TA = 25C on a two-layer Richtek Evaluation Board. Note 3. Devices are ESD sensitive. Handling precautions are recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Copyright © 2022 Richtek Technology Corporation. All rights reserved. www.richtek.com 6 is a registered trademark of Richtek Technology Corporation. DS4812-09 March 2022 RT4812 Typical Application Circuit RT4812 L1 VIN 6 SW VOUT C1 22μF 1 VIN FB C2 1μF R3 100k DS4812-09 March 2022 2 VOUT R1 909k C3 22μF x 2 R2 100k 7 EN 8 ILIM Copyright © 2022 Richtek Technology Corporation. All rights reserved. 3 GND 5 PGND 4 is a registered trademark of Richtek Technology Corporation. www.richtek.com 7 RT4812 Typical Operating Characteristics Efficiency vs. Output Current Efficiency vs. Output Current 100 100 90 80 VIN = 4.2V 80 VIN = 2.5V 70 VIN = 3.6V 70 VIN = 1.8V 60 VIN = 2.5V Efficiency (%) Efficiency (%) 90 VIN = 1.8V 50 40 30 20 VOUT = 5V, L = 1.5μH (TDK SPM6530), 10 R1 = 45.3k, R2 = 4.99k, C OUT = 22μF x 2 60 50 40 30 20 VOUT = 3.6V, L = 1.5μH (TDK SPM6530), 10 R1 = 45.3k, R2 = 7.3k, C OUT = 22μF x 2 0 0 0 400 800 1200 1600 0 2000 400 Output Current (mA) Efficiency vs. Outout Current 1200 100 90 90 80 VIN = 4.2V 80 VIN = 2.5V 70 VIN = 3.7V 70 VIN = 1.8V 60 VIN = 3.3V VIN = 2.5V 50 VIN = 1.8V 40 30 20 2000 60 50 40 30 20 VOUT = 5V, L = 1.5μH (TDK SPM6530), R1 = 909k, 10 1600 Efficiency vs. Output Current 100 Efficiency (%) Efficiency (%) 800 Output Current (mA) VOUT = 3.6V, L = 1.5μH (TDK SPM6530), R1 = 909k, 10 R2 = 100k, COUT = 22μF x 2 R2 = 146.6k, C OUT = 22μF x 2 0 0 0 400 800 1200 1600 2000 0 2400 400 800 1200 1600 2000 2400 Output Current (mA) Outout Current (mA) Load Current vs. Output Voltage Shutdown Current vs. Temperature 2.5 1.8 1.6 Load Current (A) Shutdown Current (μA)1 ILIM = H 2.0 1.5 1.0 ILIM = L 0.5 1.4 1.2 1.0 0.8 VIN = 5.5V 0.6 VIN = 3.6V 0.4 0.2 0.0 0.0 4.0 4.2 4.4 4.6 4.8 Output Voltage (V) Copyright © 2022 Richtek Technology Corporation. All rights reserved. www.richtek.com 8 5.0 -40 -15 10 35 60 85 Temperature (°C) is a registered trademark of Richtek Technology Corporation. DS4812-09 March 2022 RT4812 Output Voltage Ripple Output Voltage Ripple VBAT = 2.5V, VOUT = 5V, IOUT = 1000mA SW (2V/Div) SW (2V/Div) VOUT_ac (20mV/Div) VOUT_ac (50mV/Div) VBAT = 2.5V, VOUT = 5V, IOUT = 0mA L = 1.5H, COUT = 22F x 2 L = 1.5H, COUT = 22F x 2 Time (10s/Div) Time (1s/Div) Output Voltage Ripple Output Voltage Ripple SW (2V/Div) SW (2V/Div) VOUT_ac (20mV/Div) VOUT_ac (50mV/Div) VBAT = 3.6V, VOUT = 5V, IOUT = 1000mA L = 1.5H, COUT = 22F x 2 VBAT = 3.6V, VOUT = 5V, IOUT = 0mA L = 1.5H, COUT = 22F x 2 Time (10s/Div) Time (1s/Div) Output Voltage Ripple Output Voltage Ripple SW (2V/Div) SW (2V/Div) VOUT_ac (20mV/Div) VOUT_ac (50mV/Div) VBAT = 4.2V, VOUT = 5V, IOUT = 0mA L = 1.5H, COUT = 22F x 2 Time (10s/Div) Copyright © 2022 Richtek Technology Corporation. All rights reserved. DS4812-09 March 2022 VBAT = 4.2V, VOUT = 5V, IOUT = 1000mA, L = 1.5H, COUT = 22F x 2 Time (1s/Div) is a registered trademark of Richtek Technology Corporation. www.richtek.com 9 RT4812 Load Transient Response IOUT (1A/Div) IOUT (1A/Div) VOUT_ac (200mV/Div) Load Transient Response VBAT = 3.7V, VOUT = 5V, IOUT = 1000mA to 2000mA L = 1.5H, COUT = 22F x 2 VBAT = 2.5V, VOUT = 5V, IOUT = 1000mA to 2000mA L = 1.5H, COUT = 22F x 2 VOUT_ac (200mV/Div) Time (500s/Div) Time (500s/Div) Load Transient Response IOUT (1A/Div) VBAT = 4.2V, VOUT = 5V, IOUT = 1000mA to 2000mA L = 1.5H, COUT = 22F x 2 VOUT_ac (200mV/Diiv) Time (500s/Div) Copyright © 2022 Richtek Technology Corporation. All rights reserved. www.richtek.com 10 is a registered trademark of Richtek Technology Corporation. DS4812-09 March 2022 RT4812 Application Information Enable Power Save Mode The device can be enabled or disabled by the EN pin. PSM is the way to improve efficiency at light load. When the EN pin is higher than the threshold of When the output voltage is lower than a set threshold logic-high, the device starts operating with soft-start. voltage, the converter will operate in PSM. Once the EN pin is set at low, the device will be shut It raises the output voltage with several pulses until down. In shutdown mode, the converter stops the loop exits PSM. switching, internal control circuitry is turned off, and the load is disconnected from the input. This also Under-Voltage Lockout means that the output voltage can drop below the The under-voltage lockout circuit prevents the device input voltage during shutdown. from operating incorrectly at low input voltages. It prevents the converter from turning on the power Soft-Start State switches under undefined conditions and prevents the After the successful completion of the LIN state (VOUT ≥ VIN = 300mV), the regulator begins switching with battery from deep discharge. VIN voltage must be greater than 1.65V to enable the converter. During boost valley-current limited value 3500mA. operation, if VIN voltage drops below 1.55V, the During Soft-Start state, VOUT is ramped up by Boost converter is disabled and waiting internal IC default internal loop. If VOUT fails to reach target value during parameter value ready until the supply exceeds the the Soft-Start period for more than 2ms, a fault UVLO rising threshold. The RT4812 automatically condition is declared. restarts if the input voltage recovers to the input voltage UVLO high level. Output Voltage Setting The output voltage is adjustable by an external Thermal Shutdown resistive divider. The resistive divider must be The device has a built-in temperature sensor which connected between VOUT, FB and GND. When the monitors the internal junction temperature. If the output voltage is regulated properly, the typical value temperature exceeds the threshold, the device stops of the voltage at the FB pin is 500mV. Output voltage operating. As soon as the IC temperature has can be calculated by equation as below : decreased below the threshold with a hysteresis, it V  R1  R2   OUT  1  VFB  starts operating again. The built-in hysteresis is designed to avoid unstable operation at IC temperatures near the over temperature threshold. Inductor Selection The recommended nominal inductance value is 1.5H It is recommended to use inductor with dc saturation current ≥ 5000mA Table 1. List of Inductors Manufacturer Series Dimensions (in mm) Saturation Current (mA) TDK SPM6530T 7.1 x 6.5 x 3.0 11500 Taiyo Yuden NRS5040T 5.15 x 5.15 x 4.2 6400 Copyright © 2022 Richtek Technology Corporation. All rights reserved. DS4812-09 March 2022 is a registered trademark of Richtek Technology Corporation. www.richtek.com 11 RT4812 Input Capacitor Selection Output Discharge Function At least a 22F and the rate voltage is 16V for DC With the EN pin set to low, the VOUT pin is internally bias input capacitor is recommended to improve connected to GND for 10ms by an internal discharge transient behavior of the regulator and EMI behavior N-MOSFET switch. After the 10ms, IC will be of the total power supply circuit for SW. And at least a true-shut down. 1F ceramic capacitor placed as close as possible to This feature prevents residual charge voltages on the VIN and GND pins of the IC is recommended. capacitor connected to VOUT pins, which may impact proper power up of the system. Output Capacitor Selection At least 22F x 2 capacitors is recommended to Valley Current Limit improve VOUT ripple. The RT4812 employs a valley-current limit detection Output voltage ripple is inversely proportional to scheme to sense inductor current during the off-time. COUT. When the loading current is increased such that the Output capacitor is selected according to output ripple loading is above the valley current limit threshold, the which is calculated as : off-time is increased until the current is decreased to valley-current threshold. Next on-time begins after I VRIPPLE(P P)  tON  LOAD COUT current is decreased to valley-current threshold. On-time is decided by (VOUT VIN) / VOUT ratio. The output voltage decreases when further loading and  V  tON  tSW  D  tSW   1  IN  V OUT   therefore :  V COUT  tSW   1  IN V OUT  and tSW  current increase. The current limit function is implemented by the scheme, refer to Figure 3. Average Output Current Limit  ILOAD  V RIPPLE(P P)  The RT4812 features the average output current limit to protect the output terminal. When the load current is over the limit, output current will be clamped. 1 fSW The maximum VRIPPLE occurs at minimum input voltage and maximum output load. IIN (DC) Valley Current Limit f Inductor Current IIN (DC) IL IL = VIN D  L f Figure 3. Inductor Currents In Current Limit Operation Table 2. List of Capacitor Reference Qty. Part Number Description Package Manufacturer CIN 1 GRM21BR61C226ME44 22F / 16V / X5R 0805 MuRata COUT 2 GRM21BR61C226ME44 22F / 16V / X5R 0805 MuRata Copyright © 2022 Richtek Technology Corporation. All rights reserved. www.richtek.com 12 is a registered trademark of Richtek Technology Corporation. DS4812-09 March 2022 RT4812 Thermal Considerations For continuous operation, do not exceed absolute 2.0 Maximum Power Dissipation (W)1 maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : PD(MAX) = (TJ(MAX)  TA) / JA where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and JA is the junction Two-Layer PCB 1.6 1.2 0.8 0.4 0.0 to ambient thermal resistance. 0 For recommended operating condition specifications, 25 50 75 100 125 Ambient Temperature (°C) the maximum junction temperature is 125C. The junction to ambient thermal resistance, JA, is layout Figure 4. Derating Curve of Maximum Power dependent. For TSOT-23-8 (FC) package, the Dissipation thermal resistance, JA, is 56C/W on a standard two-layer EVB test board. The maximum power dissipation at TA = 25C can be calculated by the following formula : PD(MAX) = (125C  25C) / (56C/W) = 1.78W for TSOT-23-8 (FC) package The maximum power dissipation depends on the operating ambient temperature for fixed T J(MAX) and thermal resistance, JA. The derating curve in Figure 4 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. Layout Consideration The PCB layout is an important step to maintain the high performance of the RT4812. Both the high current and the fast switching nodes demand full attention to the PCB layout to save the robustness of the RT4812 through the PCB layout. Improper layout might show the symptoms of poor line or load regulation, ground and output voltage shifts, stability issues, unsatisfying EMI behavior or worsened efficiency. For the best performance of the RT4812, the following PCB layout guidelines must be strictly followed.  Input/Output capacitors must be placed as close as possible to the Input/Output pins.  SW should be connected to Inductor by wide and short trace, keep sensitive components away from this trace.  The feedback divider should be placed as close as possible to the FB pin. Copyright © 2022 Richtek Technology Corporation. All rights reserved. DS4812-09 March 2022 is a registered trademark of Richtek Technology Corporation. www.richtek.com 13 RT4812 L Vin Cin Cout Cout Vout GND Figure 5. PCB Layout Guide Copyright © 2022 Richtek Technology Corporation. All rights reserved. www.richtek.com 14 is a registered trademark of Richtek Technology Corporation. DS4812-09 March 2022 RT4812 Outline Dimension Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 1.000 0.028 0.039 A1 0.000 0.100 0.000 0.004 B 1.397 1.803 0.055 0.071 b 0.220 0.380 0.009 0.015 C 2.591 3.000 0.102 0.118 D 2.692 3.099 0.106 0.122 e 0.585 0.715 0.023 0.028 H 0.080 0.254 0.003 0.010 L 0.300 0.610 0.012 0.024 TSOT-23-8 (FC) Surface Mount Package Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. Copyright © 2022 Richtek Technology Corporation. All rights reserved. DS4812-09 March 2022 is a registered trademark of Richtek Technology Corporation. www.richtek.com 15