RT4831A
Four-Channel LCD Backlight Driver with Integrated Bias
Power
General Description
The RT4831A is an integrated four-channel backlight
WLED driver with LCD bias supply for portable device.
The backlight WLED driver supports up to 4P8S
WLED configuration. Meanwhile, the driver maximum
acceptable output voltage is 29V. Each channel
current is controlled by the I2C interface and/or the
external PWM input to achieve 11 bit LED current steps
Features
System
Hardware Enable Pin
I2C Controlled Interface
Over-Temperature Protection
Backlight WLED Driver
2.7V to 5V Input Voltage Range
Drives Up to 4P8S WLED Configuration (29V
from 60A to 30mA in exponential or linear mapping
Maximum Output Voltage)
curves. The LCD bias supply is implemented with a
External PWM Input and I2C Brightness Control
Boost, a LDO and an inverting charge pump to provide
11 Bit Exponential and Linear Dimming Control
positive and negative voltage. The LCD bias provides
Programmable Over-Voltage Protection
up to 150mA output current and the output voltage can
be programmed via I2C interface from ±4V to ±6.5V with
Programmable Over-Current Protection
Auto Operating Frequency (250kHz, 500kHz,
50mV/step. The RT4831A is available in a WL-CSP-
1MHz)
24B 1.84x2.68 (BSC) package.
Ordering Information
LCD Bias Supply
RT4831A
Package Type
WSC : WL-CSP-24B 1.84x2.68 (BSC)
2.7V to 5V Input Voltage Range
Programmable Positive / Negative Output
Voltage from ±4V to ±6.5V with 50mV/Step
Programmable Boost Output Voltage from 4V to
7.15V with 50mV/Step
Richtek products are :
Note :
WLED Current Ramp Up / Ramp Down Smoothen
RoHS compliant and compatible with the current
150mA Output Current Capability
Output Short-Circuit Protection
requirements of IPC/JEDEC J-STD-020.
Suitable for use in SnPb or Pb-free soldering processes.
Copyright © 2020 Richtek Technology Corporation. All rights reserved.
DS4831A-05
July 2020
Applications
LCD Panels with up to 32 LEDs
Smartphone
Tablet
is a registered trademark of Richtek Technology Corporation.
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1
RT4831A
Marking Information
Pin Configuration
7H : Product Code
W : Date Code
(TOP VIEW)
7HW
A1
A2
A3
A4
VNEG
C-
CP_GND
C+
B1
B2
B3
B4
IN
LCM_
EN2
LCM_
EN1
VPOS
C1
C2
C3
C4
LED4
SCL
SDA
LCM_
OUT
D1
D2
D3
D4
HWEN
LCM_
SW
E3
E4
LED3
PWM
E1
E2
LED2
AGND
F1
F2
LCM_ BL_GND
GND
F3
F4
LED1 BL_OUT BL_SW BL_SW
WL-CSP-24B 1.84x2.68 (BSC)
Simplified Application Circuit
L1
D1
VBL
VIN
C1
BL_SW
RT4831A
IN
C3
C4
BL_OUT
BL_GND
LED1
L2
LED2
LCM_SW
C2
LED3
LED4
PWM
LCM_OUT
C5
SCL
LCM_GND
SDA
VPOS
VPOS
C6
HWEN
VNEG
LCM_EN1
VNEG
C7
C8
CP_GND
LCM_EN2
C+
C9
CAGND
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is a registered trademark of Richtek Technology Corporation.
DS4831A-05
July 2020
RT4831A
Functional Pin Description
Pin No.
Pin Name
Pin Function
A1
VNEG
Charge pump negative output. Connect a 10F decouple ceramic
capacitor between this pin and CP_GND pin.
A2
C-
Charge pump flying capacitor negative connection. Connect a 10F
ceramic capacitor between this pin and C+ pin.
A3
CP_GND
Charge pump ground.
A4
C+
Charge pump flying capacitor positive connection. Connect a 10F
ceramic capacitor between this pin and C- pin.
B1
IN
Input voltage connection. Connect a 10F or larger decouple ceramic
capacitor between this pin and ground.
B2
LCM_EN2
Enable input for LCD bias VNEG.
B3
LCM_EN1
Enable input for LCD bias VPOS.
B4
VPOS
LCD bias positive output. Connect a 10F decouple ceramic capacitor
between this pin and ground.
C1
LED4
Backlight LED current sink 4 input. Connect the cathode of LED string 4 to
this pin.
C2
SCL
I2C serial clock input. An external pull-up resistor is required.
C3
SDA
I2C serial data input/output. An external pull-up resistor is required.
C4
LCM_OUT
LCD bias boost output. Connect a 10F decouple ceramic capacitor
between this pin and LCM_GND pin.
D1
LED3
Backlight LED current sink 3 input. Connect the cathode of LED string 3 to
this pin.
D2
PWM
Backlight PWM dimming input.
D3
HWEN
Chip enable input.
D4
LCM_SW
LCD bias boost inductor connection.
E1
LED2
Backlight LED current sink 2 input. Connect the cathode of LED string 2 to
this pin.
E2
AGND
Analog ground.
E3
LCM_GND
LCD bias boost ground.
E4
BL_GND
Backlight boost ground.
F1
LED1
Backlight LED current sink 1 input. Connect the cathode of LED string 1 to
this pin.
F2
BL_OUT
Backlight boost output voltage sense connection.
F3, F4
BL_SW
Backlight boost inductor connection.
Copyright © 2020 Richtek Technology Corporation. All rights reserved.
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July 2020
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RT4831A
Functional Block Diagram
BL_SW
BL_SW
IN
OTP
POR
OCP
BL_GND
HWEN
SCL
SDA
UVLO
Backlight Boost
OVP
LED1
2
Brightness
Control
I C Interface
Control
LED
Current
Control
LED2
LED3
LCM_EN1
LCM_EN2
BL_OUT
LED4
LCM Bias
Control
Digital
Control
VPOS
SCP
PWM
LCM Boost
VPOS
LDO
VPOS
VNEG
-1X Charge
Pump
C+
CVNEG
VNEG
SCP
AGND
LCM_GND
LCM_SW
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LCM_OUT
CP_GND
is a registered trademark of Richtek Technology Corporation.
DS4831A-05
July 2020
RT4831A
Absolute Maximum Ratings
(Note 1)
IN, LCM_EN2, LCM_EN1, SCL, SDA, PWM, HWEN --------------------------------------------------------0.3V to 6V
C+, VPOS, LCM_OUT -----------------------------------------------------------------------------------------------0.3V to 8.5V
LCM_SW ---------------------------------------------------------------------------------------------------------------0.3V to 8.5V
(0
1
Duty = 0
0000
Standby
1
1
1111
>0
1
Duty > 0
0000
ILEDx = (BLED
Brightness x PWM
Duty)
1
1
1111
>0
1
Duty > 0
1111
Standby
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Status
is a registered trademark of Richtek Technology Corporation.
DS4831A-05
July 2020
RT4831A
OVP, OCP, PWM,
Ramp time, Brightness code
BLED_EN,
BLED_CHx_EN
BLED_EN = 0,
BLED_CHx_EN
= 0000
Ramp time, Brightness code
2
I C
Vf of LED string
VBL_OUT
SS
time
Ramp
time
Ramp
time
ILEDx
VLEDx
Figure 1. Power Sequence with I2C
OVP, OCP, BLED_EN,
BLED_CHx_EN,
Ramp time, Brightness code
PWM_EN
Ramp time
2
I C
PWM
Vf of LED string
PWM detector
gets 1 cycle
VBL_OUT
PWM detector
gets 1 cycle
SS
time
Ramp
time
Ramp
time
Time
out
ILEDx
VLEDx
Figure 2. Power Sequence with PWM
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RT4831A
Register Programming
When register 0x02[0] = 1 (BLED_PWM_EN), the
The following registers or bits must be programmed
IC built-in PWM dimming function is activated to
while the register bit 0x08[4] = 0 (BLED_EN) and
participate in controlling the LED brightness
register bit 0x08[3:0] = 0 (BLED_CHx_EN).
current. Each channel output current for the 11 bits
Register 0x02[0] (BLED_PWM_EN)
brightness code can be approximate by below
Register 0x02[1] (BLED_PWM_RAMP_EN)
Register 0x02[2] (BLED_CONFIG)
Register 0x02[3] (BLED_CODE)
Register 0x03[1:0] (BLED_PWM_HYS)
Register 0x03[2] (BLED_PWM_ SAMPLE)
Register 0x03[6:3] (BLED_RAMPTIME)
Register 0x06 (BLED_AFLT)
Register 0x07 (BLED_AFHT)
Register 0x10[0]
bit maximum resolution of PWM duty cycle to the
(BLED_PWM_24MHz_SAMPLE)
LED brightness code, the input PWM duty cycle
Register 0x10[2:1] (BLED_PWM_DEGLITCH)
must be ≥ 11-bits, and the PWM sample period
Register 0x10[6:3] (BLED_CHx_FB_DISABLE)
(1/ƒSAMPLE) must be smaller than the minimum
Register 0x14[1:0] (BLED_SMOOTH_EN)
PWM input pulse width. Figure 3 shows the ideal
equation.
Linear Mode (PWM)
ILED = 45.37A + 14.63A x brightness code x
PWM Duty
Exponential Mode (PWM)
ILED = 60A x 1.003040572brightness code x PWM Duty
PWM Resolution and Input Frequency Range
The PWM input frequency must be operated at
range from 50Hz to 50kHz. To achieve the full 11-
maximum resolutions based on the input PWM
LED Brightness Current Control and PWM
frequency. The minimum PWM frequency for each
Brightness Dimming
PWM sample rate is based on PWM timeout. Note
The LED brightness current level is controlled via
to set register 0x08[4] = 0 (BLED_EN) before
the register only (I2C) or the register together with
changing the different PWM sampling rate.
PWM duty cycle (I2C + PWM). The brightness
maps to the LED current can be set either linear
12
mapping or exponential mapping.
11
LED current is set via the register and each
channel output current for the 11 bits brightness
code can be approximate by below equation.
Linear Mode
ILED = 45.37A + 14.63A x brightness code
Exponential Mode
ILED = 60A x 1.003040572brightness code
Maximum Resolution (bits)1
When register 0x02[0] = 0 (BLED_PWM_EN), the
PWM Sample Rate
10
9
8
7
6
4MHz
1MHz
24MHz
5
4
10
100
1000
10000
100000
PWM Frequency (Hz)
Figure 3. PWM Sample Rate, Resolution, and PWM
Input Frequency
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is a registered trademark of Richtek Technology Corporation.
DS4831A-05
July 2020
RT4831A
Table 2. Input Quiescent with Different Dimming Mode
Dimming Mode
Typical Input Quiescent Current
ILED = 30mA/string, 4P4S
I2C mode
1.75mA
PWM mode, Sample rate = 1MHz
2.18mA
PWM mode, Sample rate = 4MHz
2.21mA
PWM mode, Sample rate = 24MHz
2.37mA
PWM Ramper
cycle change. When 0x02[1] = 1, ramper is
The PWM ramper smooths the transition from one
activated and ramping is achieved between I2C x
brightness value to another. If register 0x02[1] = 0,
PWM currents. Register 0x03[6:3] is used to set up
the PWM duty cycle is multiplied with the I2C
the up and down ramp time. Ramp time is always
brightness code at the output of the ramper and
same regardless the amount of change in
there is no current ramping between PWM duty
brightness.
Digital
Analog
Mapping register
(bled_code)
BL_VOUT
Mapper
2
I C
2
Ramper/
Limiter
I C_BRGT
_CODE
DAC code
1
Exponential
mapping
DAC
0
+
-
VLED
MUX
PWM duty
PWM
Figure 4. I2C + PWM Brightness Control, 0x02[1] = 0, PWM Ramper Disabled
Digital
Analog
Mapping register
(bled_code)
BL_VOUT
Mapper
2
I C
2
Ramper/
Limiter
I C_BRGT
_CODE
1
Exponential
mapping
PWM
0
DAC code
DAC
+
-
VLED
MUX
PWM duty
Figure 5. I2C + PWM Brightness Control, 0x02[1] = 1, PWM Ramper Enabled
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RT4831A
PWM Hysteresis
(b)
The RT4831A provides unidirectional hysteresis
the previous duty.
design to prevent jitter at the input PWM signal
(b-1) If the new PWM duty does not overcome the
without reducing the resolution. There are 4
hysteresis, the LED current keeps the
selectable
original value without any change.
hysteresis
settings
with
PWM duty changes with reverse direction of
register
0x03[1:0]. The hysteresis options for the 1MHz
(b-2) If the new PWM duty overcomes the
and 4MHz PWM sample rate settings are 1, 2, 4,
hysteresis,
and 6 bits and for the 24MHz PWM sample rate
following the changed PWM duty.
the
LED
current
changes
setting are 0, 1, 2, and 3 bits. Note to set register
0x08[4] = 0 (BLED_EN) before changing the
different PWM hysteresis. Refer to below figure for
(a)
Hysteresis
Hysteresis
PWM Duty
Hysteresis
(b-1)
explanations.
(a) PWM duty changes with the same direction.
(b-2)
Hysteresis
(b-2)
(a)
(b-2)
(b-2)
(b-1)
(increase or decrease) LED current changes
ILED
following the new PWM duty even it does not
overcome the PWM hysteresis.
Time
Figure 6. PWM Hysteresis
PWM Timeout
The RT4831A features PWM timeout function to turn off boost output if no PWM pulse detected when the PWM
dimming is enabled. The timeout duration changes based on the PWM sample rate selected which results in a
minimum supported PWM input frequency.
Table 3. PWM Timeout & Minimum Supported PWM Frequency
Time Out
Minimum PWM Frequency
1MHz
25ms
48Hz
4MHz
3ms
400Hz
24MHz
0.6ms
2000Hz
PWM-to-Digital Code Readback
0.32
In PWM mode, the register 0x12[7:0] and 0x13[2:0]
0.30
can read back the 11 bits PWM duty detector result.
0.28
With example of readback value 0x3FF (decimal
0.26
1023), the PWM duty is calculated approximately
50%. (1023/2047)
Minimum Regulated Headroom Voltage
0.24
VHR (V)
Sample Rate
0.22
0.20
0.18
To optimize the system efficiency, the RT4831A
0.16
integrates a minimum regulated headroom voltage
0.14
function with good ILED accuracy and matching
performance. Following graph is the VLED tracking
target for the minimum one of the VLED strings that
0.12
0.10
0.1
1
10
100
ILED (mA)
is enable.
Figure 7. Linear Regulated Headroom Voltage vs.
Programmed LED Current
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is a registered trademark of Richtek Technology Corporation.
DS4831A-05
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RT4831A
Boost Switching Frequency
Auto-frequency mode is enabled whenever there is
The RT4831A serves 2 fixed switching frequency
non-zero code in either register 0x06 or register
(1MHz and 0.5MHz) and auto-frequency function
0x07. With comparison of registers 0x05[7:0]
(1MHz, 0.5MHz and 0.25MHz) to optimize the
(Brightness MSB), 0x06[7:0] and 0x07[7:0], the
boost efficiency. When both registers 0x06 (AFLT)
RT4831A auto switchovers different switching
and 0x07 (AFHT) are zero code, the boost
frequency. Table 4 gives an example of boost
switching frequency is fixed and the value is set via
switching frequency setting. Note the inductor
the register 0x03[7].
selection and OCP level need to be taken into
consideration with different applications.
Table 4. Boost Switching Frequency Setting Example
Brightness MSB
0x05[7:0]
BLED_BST_FREQUENCY
0x03[7]
BLED_AFLT
0x06[7:0]
BLED_AFHT
0x07[7:0]
Switching
Frequency
X
0
0x00
0x00
0.5MHz (Fixed)
X
1
0x00
0x00
1MHz (Fixed)
< 0x40
X
0x40
0x80
0.25MHz (Auto)
0x40 ≤ & < 0x80
X
0x40
0x80
0.5MHz (Auto)
≥ 0x80
X
0x40
0x80
1MHz (Auto)
LCD Bias
Operation Control
The RT4831 LCD bias provides four different operating modes (Normal, Auto, Wake1 and Wake2) for flexible
application. Registers 0x09[7:5] are used to control the operating mode.
Table 5. LCD Bias Control
HWEN
DSV_MODE_
EN
0x09[7:5]
DSV_VPOS_
EN
0x09[2]
DSV_VNEG_
EN
0x09[1]
DSV_EXTERNAL_
EN
0x09[0]
LCM_
EN1
LCM_
EN2
Low
XXX
X
X
X
X
X
Shutdown
High
000
X
X
X
X
X
Standby
High
100
0
0
0
X
X
Normal Mode
Standby
High
100
X
X
1
0
0
Normal Mode
Standby
X
Normal Mode
Channel enabled via I2C
VPOS = 0x0D setting target
VNEG is off state
X
Normal mode
Channel enabled via I2C
VPOS is off state
VNEG = 0x0E setting target
High
High
100
100
1
0
0
1
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0
0
X
X
Status
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RT4831A
HWEN
High
High
High
High
High
DSV_MODE_
EN
0x09[7:5]
100
100
100
100
101
DSV_VPOS_
EN
0x09[2]
1
X
X
X
1
DSV_VNEG_
EN
0x09[1]
1
X
X
X
1
DSV_EXTERNAL_
EN
0x09[0]
0
1
1
1
0
LCM_
EN1
X
1
0
1
X
LCM_
EN2
Status
X
Normal mode
Channel enabled via I2C
VPOS = 0x0D setting target
VNEG = 0x0E setting target
0
Normal mode
Channel enabled via
external pin
VPOS = 0x0D setting target
VNEG is off state
1
Normal mode
Channel enabled via
external pin
VPOS is off state
VNEG = 0x0E setting target
1
Normal mode
Channel enabled via
external pin
VPOS = 0x0D setting target
VNEG = 0x0E setting target
X
Auto sequence mode
Channel enabled via I2C
VPOS = 0x0D setting target
VNEG = 0x0E setting target
High
101
X
X
1
X
1
Auto sequence mode
Channel enabled via
LCM_EN2
VPOS = 0x0D setting target
VNEG = 0x0E setting target
High
110
1
1
X
X
0
Wake1 Mode
Standby
High
110
0
0
X
X
1
Wake1 Mode
Standby
High
110
1
0
X
X
1
Wake1 Mode
VPOS = VIN
VNEG is off state
High
110
0
1
X
X
1
Wake1 Mode
VPOS is off state
VNEG = VIN
High
110
1
1
X
X
1
Wake1 Mode
VPOS = VIN
VNEG = VIN
High
111
1
1
X
X
0
Wake2 Mode
Standby
High
111
0
0
X
X
1
Wake2 Mode
Standby
High
111
1
0
X
X
1
Wake2 Mode
VPOS = 0x0D setting target
VNEG is off state
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RT4831A
HWEN
DSV_MODE_
EN
0x09[7:5]
DSV_VPOS_
EN
0x09[2]
DSV_VNEG_
EN
0x09[1]
DSV_EXTERNAL_
EN
0x09[0]
LCM_
EN1
LCM_
EN2
Status
High
111
0
1
X
X
1
Wake2 Mode
VPOS is off state
VNEG = 0x0E setting target
High
111
1
1
X
X
1
Wake2 Mode
VPOS = 0x0D setting target
VNEG = 0x0E setting target
Normal Mode Control Setting
POS and NEG outputs are regulated to programmed values with normal mode operation. The channel on-off
setting of POS and NEG can be programmed via I2C with dedicated registers or external pins.
Registers 0x09[2]/ 0x09[1] are able to software control POS/ NEG on-off.
With register 0x09[0]=1, LCM_EN1/ LCM_EN2 are used to hardware control POS/ NEG on-off.
HWEN
DSV_VPOS
0x0D[5:0]
DSV_VNEG
0x0E[5:0]
LCM_EN1 or
DSV_VPOS_EN 0x09[2]
2.5ms
LCM_EN2 or
DSV_VNEG_EN 0x09[1]
2.5ms
90%
VLCM
VIN
256µs
Vtarget
< 300µs
POS voltage changes to new target only after
channel ON/ OFF
New Vtarget
3V
VPOS
DSV_VPOS_SR
0x0A[5:4]
512µs
< 500µs
VNEG
-3V
DSV_VNEG_SR
0x0A[3:0]
New Vtarget
Vtarget
NEG voltage changes to new target only after
channel ON/ OFF
Figure 8. Example for Normal Mode with I2C Software Control or External Pins Control
Auto Mode Control Setting
In auto mode, POS and NEG are on or off in sequence. Within power on sequence, V POS voltage ramp up to
the programmed value, then VNEG voltage starts to ramp down to its programmed value after 1.2ms (typ.). Within
power-off sequence, VNEG voltage drops to 0V then VPOS starts to turn off after 1.2ms (typ.). Channels on-off
setting can be programmed via I2C with dedicated registers or external pin.
Registers 0x09[2] and 0x09[1] are able to software control POS and NEG on-off. Note only both above
register bits are written 1, there will be output voltage VPOS and VNEG.
With register 0x09[0] = 1, LCM_EN2 is used to hardware control POS and NEG on-off.
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RT4831A
HWEN
DSV_VPOS_EN 0x09[2]
2ms
Power sequence starts only when both DSV_VPOS_EN
and DSV_VNEG_EN are high
2.5ms
DSV_VNEG_EN 0x09[1]
Power sequence re-starts when both DSV_VPOS_EN
and DSV_VNEG_EN are high
90%
VLCM
Both channels will be turned off if DSV_VPOS_EN
or DSV_VNEG_EN is low
VIN
Vtarget
100µs
< 300µs
3V
DSV_VPOS_SR
0x0A[5:4]
VPOS
1.2ms
1.2ms
1.2ms
< 500µs
VNEG
-3V
DSV_VNEG_SR
0x0A[3:0]
Vtarget
Figure 9. Example for Auto Mode with I2C Software Control
HWEN
LCM_EN2
2.5ms
90%
VLCM
VIN
Vtarget
100µs
< 300µs
3V
DSV_VPOS_SR
0x0A[5:4]
VPOS
1.2ms
VNEG
1.2ms
< 500µs
-3V
DSV_VNEG_SR
0x0A[3:0]
Vtarget
Figure 10. Example for Auto Mode with External Pin Control
Wake1 Mode Control Setting
In wake1 mode, the RT4831A passes VIN through to the LCM boost output, the enabled POS and NEG outputs.
Due to the impedance of the LCM boost, the POS LDO and the NEG charge pump, the respective outputs are
regulated close to VIN only at very light load current and drops as the load increases. POS and NEG on-off
setting can be controlled only by external pin.
Registers 0x09[2]/ 0x09[1] with external pin LCM_EN2 are used to control POS/ NEG on-off.
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DS4831A-05
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RT4831A
HWEN
DSV_VPOS_EN 0x09[2]
DSV_VNEG_EN 0x09[1]
LCM_EN2
VLCM
VIN
64µs
VIN
< 500µs
VPOS
128µs
VNEG
< 1ms
-VIN
Figure 11. Example for Wake1 Mode with External Pin Control
Wake2 Mode Control Setting
In wake2 mode, the VPOS and VNEG are regulated to programmed values. POS and NEG on-off setting can be
controlled only by external pin.
Registers 0x09[2]/ 0x09[1] with external pin LCM_EN2 are used to control POS/ NEG on-off.
HWEN
DSV_VPOS_EN 0x09[2]
DSV_VNEG_EN 0x09[1]
LCM_EN2
2.5ms
90%
VLCM
VIN
Vtarget
128µs
< 500µs
VPOS
256µs
VNEG
< 1ms
Vtarget
Figure 12. Example for Wake2 Mode with External Pin Control
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RT4831A
Output Voltage Setting
The RT4831A LCD bias output voltage VLCM, VPOS
Backlight
and VNEG can be programmed via I2C with
The OVP function prevents the RT4831A from
dedicated registers.
being damaged when LED with no connection or
any open circuit conditions. Via the registers
LCM
0x02[7:5] and 0x02[4], the RT4831A sets the BLED
Register 0x0C[5:0] is used to control LCM output
OVP flag, register 0x0F[1] = 1 for notification or
voltage ranges from 4V to 7.15V with 50mV step.
OVP flag with backlight shutdown when over-
It is recommended to select VLCM with the
estimation : VLCM = max (VPOS, ∣VNEG∣)+VHR,
voltage found on the output terminal. Disabling the
where VHR ≥ 200mV for lower currents and VHR
OVP shutdown (0x02[4] = 0) function when the
≥ 300mV for higher currents.
quick dimming (>10mA/500s) application such as
voltage ranges from 4V to 6.5V with 50mV step.
Note the new programmed voltage is not output
when channel is at on state. It takes effect only
after the channel is disabled and re-enabled.
CABC to avoid triggering the OVP shutdown.
POS
Register 0x0D[5:0] is used to control POS output
NEG
Register 0x0E[5:0] is used to control NEG output
voltage ranges from 4V to 6.5V with 50mV
step. Note the new programmed voltage is not
output when channel is at on state. It takes effect
only after the channel is disabled and re-enabled.
Boost Output Over-Voltage Protection
Output Active Discharge Setting
Over-Current Protection
There are four selectable OCP thresholds with the
register 0x11[1:0]. When the inductor current
reaches the low-side MOSFET peak current limit
threshold, the low-side MOSFET will be turned-off.
Meanwhile, the register 0x0F[0] is set 1 for
notification. The maximum inductor current is
decided by the inductor current rising rate and the
response delay time of the internal network.
Below
tables
are
the
OCP
level
setting
recommendations for different applications without
triggering OCP. Note the inductor saturation
current selected should be higher than OCP level.
The RT4831A integrates internal switch resistors to
actively discharge the output voltage when the
L = 4.7H
30mA
25mA
20mA
4P4S
1.5A
1.2A
0.9A
4P5S
1.8A
1.5A
1.2A
4P6S
1.8A
1.5A
1.5A
4P7S
1.8A
1.8A
1.5A
4P8S
1.8A
1.8A
1.5A
L = 10H
30mA
25mA
20mA
4P4S
1.2A
0.9A
0.9A
4P5S
1.5A
1.2A
0.9A
to prevent the device from damages causing by
4P6S
1.8A
1.5A
1.2A
abnormal operation or fault conditions. (over-load,
4P7S
1.8A
1.5A
1.2A
short-circuit, soldering issue…etc.)
4P8S
1.8A
1.8A
1.5A
channel is off.
The POS active discharge function is controlled by
register 0x09[4].
The NEG active discharge function is controlled by
register 0x09[3].
Channel Protection Features
The RT4831A equips boost output Over-Voltage
Protection and LED Over-Current Protection for
backlight; LCM output Over-Voltage Protection, and
POS/ NEG output Short-Circuit Protection for LCD bias,
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is a registered trademark of Richtek Technology Corporation.
DS4831A-05
July 2020
RT4831A
For different LED applications, the following tables
LCM Inductor Over-Current Protection
show the VIN operating range due to the maximum
When the loading current is increased such that the
duty and OCP limitation.
inductor current is above the high-side MOSFET
valley current limit threshold, the off-time is
L = 4.7H
30mA
25mA
20mA
4P4S
2.5 to 5V
2.5 to 5V
2.5 to 5V
4P5S
2.5 to 5V
2.5 to 5V
2.5 to 5V
4P6S
2.5 to 5V
2.5 to 5V
2.5 to 5V
4P7S
2.7 to 5V
2.5 to 5V
2.5 to 5V
4P8S
3.1 to 5V
2.7 to 5V
2.5 to 5V
increased until the inductor current is decreased to
valley current threshold. The maximum inductor
current is decided by the high-side MOSFET valley
current limit level and internal designed inductor
current ripple.
POS Output Short-Circuit Protection
If the output current at POS exceeds 180mA (typ.),
the RT4831A sets the POS SCP flag, register
0x0F[3]. Register 0x0A[7:6] configures the IC
L = 10H
30mA
25mA
20mA
4P4S
2.5 to 5V
2.5 to 5V
2.5 to 5V
4P5S
2.5 to 5V
2.5 to 5V
2.5 to 5V
4P6S
2.7 to 5V
2.5 to 5V
2.5 to 5V
Backlight. Once the output over current condition is
4P7S
2.9 to 5V
2.7 to 5V
2.5 to 5V
removed, the flag can be cleared with an I2C read
4P8S
3.1 to 5V
2.9 to 5V
2.7 to 5V
back of the register. To avoid falsely triggering a
behavior for the POS SCP. Three options are
report flag, report flag with shutdown POS/ NEG,
and report flag with shutdown POS/ NEG/
short-circuit condition, the register 0x0B[3:2]
provides four programmable POS short-circuit filter
LCD Bias
options : 100s, 500s, 1ms, and 2ms.
LCM Output Over-Voltage Protection
The RT4831A monitors the LCM output voltage to
protect LCM_OUT and LCM_SW from exceeding
safe operating voltages. If output voltage VLCM
reaches the over-voltage threshold 7.8V (typ.), the
RT4831A sets the LCM OVP flag, register 0x0F[5]
for notification. Once the OVP condition is removed,
the flag can be cleared with an I2C read back of the
register. The RT4831A only reports LCM OVP
condition and does not shutdown the LCM bias.
NEG Output Short-Circuit Protection
Once the VNEG output voltage rise above 79%
(typ.) of its programmed value, the RT4831A sets
the NEG SCP flag, register 0x0F[2]. Register
0x0A[7:6] configures the IC behavior for the NEG
SCP. Three options are report flag, report flag with
shutdown POS/ NEG, and report flag with
shutdown POS/ NEG/ Backlight. Once the output
voltage goes back to 82% (typ.) of its programmed
value, the flag can be cleared with an I2C read back
of the register. To avoid falsely triggering a shortcircuit condition, the register 0x0B[1:0] provides
four programmable NEG short-circuit filter options :
100s, 500s, 1ms, and 2ms.
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RT4831A
Table 6. Protection
Threshold
(typ.)
UVLO
VIN ≤ 2.04V
NA
IC Shutdown
VIN ≥ 2.3V
OTP
Temperature
≥ 140°C
NA
Flag with shutdown display bias
and backlight
Temperature ≤
120°C
BLED
OVP
VOUT ≥
VOUT_OV_BL
Occur 32s
every 500s
cycling time
0x02[4]
0 : Flag only (default)
1 : Flag with shutdown backlight
VOUT ≤
VOUT_OV_BL
BLED
OCP
IBL_SW ≥
ICL_PK_BL
Occur 32s
every 500s
cycling time
Flag only
IBL_SW ≤
ICL_PK_BL
LCM
OVP
VLCM ≥ 7.8V
Occur 128s
every 1000s
cycling time
Flag only
VLCM ≤ 7.8V
IPOS ≥
IPOS_CL
0x0B[3:2]
00 : 2ms
(default)
01 : 1ms
10 : 500s
11 : 100s
0x0A[7:6]
00 : Flag only (default)
01 : Flag only
10 : Flag with shutdown display
bias
11 : Flag with shutdown display
bias and backlight
IPOS ≤ IPOS_CL
VNEG ≥
VNEG_target x
79%
0x0B[1:0]
00 : 2ms
(default)
01 : 1ms
10 : 500s
11 : 100s
0x0A[7:6]
00 : Flag only (default)
01 : Flag only
10 : Flag with shutdown display
bias
11 : Flag with shutdown display
bias and backlight
VNEG ≤
VNEG_target x 82%
System
Backlight
POS
SCP
LCD
bias
NEG
SCP
Deglitch Time
(typ.)
Reset and
Threshold
(typ.)
Type
Channel
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Protection
is a registered trademark of Richtek Technology Corporation.
DS4831A-05
July 2020
RT4831A
Unused Channel Pin Connection
If the RT4831A backlight or LCD bias function is unused, the related pins need to be connected as below table.
Table 7. Unused Channel Pin Connection
Unused Part
Unused Pin Name
Pin Connection
(Short to ground / Floating / Others)
BL_OUT
Floating
BL_SW
Floating
BL_GND
Short to ground
PWM
Floating
LED1
Floating
LED2
Floating
LED3
Floating
LED4
Floating
Channel 1 only
LED1
Floating
Channel 2 only
LED2
Floating
Channel 3 only
LED3
Floating
Channel 4 only
LED4
Floating
LCM_OUT
Floating
LCM_SW
Floating
LCM_GND
Short to ground
VPOS
Floating
VNEG
Floating
C+
Floating
C-
Floating
CP_GND
Short to ground
LCM_EN1
Floating
LCM_EN2
Floating
Unused Function
All functions
Backlight
LCD Bias
All functions
for the application with consideration of ambient
Component Selection
temperature.
Inductor Selection
Inductance in the range from 4.7H to 15H is
(2) To select an inductor with the low DCR to provide
required for backlight boost converter. To ensure the
good performance and efficiency for application.
boost stability, register 0x011[7:6] is used to adjust
Input Capacitor Selection
with corresponding selected inductance. The 2.2H
For the RT4831A, it is recommended at least a 10F
inductance is recommend for LCD bias boost
input capacitor for backlight and a 10F input
converter. There are two main considerations when
capacitor for LCD bias. Input capacitor should be
choosing an inductor :
located as close to the RT4831A as impossible to
(1) The inductor saturation current must be chosen
reduce the PCB series resistance and inductance
higher than the RT4831A peak current limit level
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that can inject noise into the chip.
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RT4831A
Boost Output Capacitor Selection
Two 1F output capacitor in parallel for backlight and
10F output capacitor for LCD bias are sufficient for
most applications. Note the capacitor tolerance,
operating voltage and ambient temperature all needs
to be taken into considerations for the effective
capacitance. The ripple voltage is an important index
for choosing output capacitor. This portion consists of
two parts. One is the product of ripple current with the
ESR of the output capacitor, while the other part is
formed by the charging and discharging process of
the output capacitor. The output ripple can be
calculated as below.
∆VOUT = ∆VESR + ∆VOUT1 = ∆VESR +
IOUT × D
fSW × COUT
where ∆VESR = ICrms × RCESR
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is a registered trademark of Richtek Technology Corporation.
DS4831A-05
July 2020
RT4831A
I2C Interface
The following table shows the RT4831A slave address 0x11(7bit).
RT4831A I2C Slave Address
MSB
LSB
R/W bit
R/W
001000
1
1/0
23/22
The I2C interface bus must be connect a resistor 2.2k to power node and independent connection to processor,
individually. The I2C timing diagrams are listed below.
Read single byte of data from Register
Slave Address
Register Address
S
0
Slave Address
A
MSB
A Sr
1
LSB
A
Assume Address = m
R/W
Data
A
P
Data for Address = m
Read N bytes of data from Registers
Slave Address
Register Address
S
0
Slave Address
A
MSB
A Sr
1
MSB
A
Data for Address = m
Data 2
LSB
MSB
Data N
LSB
A
A
S
0
MSB
Write N bytes of data to Registers
Slave Address
0
LSB
A
A
MSB
Data 1
LSB
A
Assume Address = m
P
Data for Address = m
Register Address
R/W
Data
A
Assume Address = m
R/W
S
Register Address
A
P
Data for Address = m + N - 1
Data for Address = m + 1
Write single byte of data to Register
Slave Address
LSB
A
Assume Address = m
R/W
Data 1
MSB
Data 2
LSB
A
Data for Address = m
MSB
A
Data for Address = m + 1
Data N
LSB
A P
Data for Address = m + N - 1
Driven by Master,
Driven by Slave, P Stop,
S Start,
Sr Repeat Start
I2C Waveform Information
SDA
tLOW
tF
tSU;DAT
tR
tF
tHD;STA
tSP
tBUF
tR
SCL
tHD;STA
S
tHD;DAT
tHIGH
Copyright © 2020 Richtek Technology Corporation. All rights reserved.
DS4831A-05
July 2020
tSU;STA
tSU;STO
Sr
P
S
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RT4831A
I2C Register Table
R : Read Only
RC : Read then Clear
RW : Read and Write
RWC : Read and Write Clear (Write "1" then automatic clears to "0" after procedure finish)
Addr
RegName
0x01
Revision
0x02
Backlight
Configuration 1
Bit
BitName
Default
Type
7:2
Version_ID
000000
R
Chip Version
1:0
Vendor_ID
11
R
11 : RICHTEK
Backlight OVP
000 : 17V
001 : 21V (default)
010 : 25V
011 : 29V
100 to 111 : 29V
Shutdown Enable for
Backlight OVP
0 : OVP is report only (default)
1 : OVP shutdown
Backlight Mapping Code
0 : Exponential
1 : Linear (default)
7:5
BLED_OVP
001
RW
4
BLED_OVP_
SHUTDOWN
0
RW
3
BLED_CODE
1
RW
2
BLED_CONFIG
0
RW
Backlight PWM Configuration
0 : Active High (default)
1 : Active Low
1
BLED_PWM_RAMP_
EN
0
RW
PWM Ramp Mode Enable
0 : w/o Ramp (default)
1 : w/ Ramp
0
BLED_PWM_EN
0
RW
PWM Enable
0 : PWM disable (default)
1 : PWM enable
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Description
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DS4831A-05
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RT4831A
Addr
RegName
Bit
BitName
Default
Type
7
BLED_BST_
FREQUENCY
1
RW
6:3
BLED_RAMPTIME
0001
RW
Backlight
Configuration 2
0x03
2
0x04
Backlight
Brightness LSB
0x05
Backlight
Brightness MSB
BLED_PWM_
SAMPLE
July 2020
Backlight Boost Switching
Frequency
(Please also see registers
0x06 and 0x07)
0 : 500kHz
1 : 1MHz (default)
Backlight Ramp Up/Down
Time
0000 : 0
0001 : 500s (default)
0010 : 750s
0011 : 1ms
0100 : 2ms
0101 : 5ms
0110 : 10ms
0111 : 20ms
1000 : 50ms
1001 : 100ms
1010 : 250ms
1011 : 800ms
1100 : 1s
1101 : 2s
1110 : 4s
1111 : 8s
RW
PWM Sampling Frequency
0 : 1MHz
1 : 4MHz (default)
(Please see also register
0x10)
1:0
BLED_PWM_HYS
01
RW
PWM Input Hysteresis
PWM Sample Frequency
(1MHz or 4MHz)
00 : 1 bit
01 : 2 bit (default)
10 : 4 bit
11 : 6 bit
PWM Sample Frequency
(24MHz)
00 : 0
01 : 1 bit (default)
10 : 2 bits
11 : 3 bits
7:3
Reserved
00000
RW
Reserved
2:0
BLED_DIM_L
111
RW
LSBs of 11 bit Backlight
Brightness control,
BLED_DIM[2:0], update after
write register 0x05.
7:0
BLED_DIM_H
11111111
RW
MSBs of 11 bit Backlight
Brightness control,
BLED_DIM[10:3].
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RT4831A
Addr
0x06
0x07
0x08
RegName
Backlight AutoFrequency Low
Backlight AutoFrequency High
Backlight Enable
Bit
7:0
7:0
BitName
BLED_AFLT
BLED_AFHT
00000000
00000000
Type
Description
RW
If 0x05 code is smaller than
0x06, Backlight Boost
switching frequency will be set
to 250kHz.
(Please also see register 0x03
and 0x07)
RW
If 0x05 code is greater than
0x06 but NOT greater than
0x07, Backlight Boost
switching frequency will be set
to 500kHz. If 0x05 code is
greater than 0x07, switching
frequency will be set 1MHz.
(Please also see register 0x03
and 0x06)
Software Reset
0 : Not Reset (default)
1 : Reset (Automatic returns
to 0 after reset)
7
SF_RESET
0
RWC
6:5
Reserved
00
RW
Reserved
4
BLED_EN
0
RW
Blacklight Enable
0 : Disable (default)
1 : Enable
3
BLED_CH4_EN
0
RW
LED4 Channel Enable
0 : Disable (default)
1 : Enable
2
BLED_CH3_EN
0
RW
LED3 Channel Enable
0 : Disable (default)
1 : Enable
1
BLED_CH2_EN
0
RW
LED2 Channel Enable
0 : Disable (default)
1 : Enable
0
BLED_CH1_EN
0
RW
LED1 Channel Enable
0 : Disable (default)
1 : Enable
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Default
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DS4831A-05
July 2020
RT4831A
Addr
0x09
0x0A
RegName
Display Bias
Configuration 1
Bit
BitName
Type
7:5
DSV_MODE_EN
000
RW
4
DSV_VPOS_DISC
1
RW
3
DSV_VNEG_DISC
1
RW
2
DSV_VPOS_EN
0
RW
1
DSV_VNEG_EN
0
RW
0
DSV_EXTERNAL_EN
0
RW
7:6
DSV_SHORT_MODE
00
RW
5:4
DSV_VPOS_SR
01
RW
3:0
DSV_VNEG_SR
0001
RW
Display Bias
Configuration 2
Copyright © 2020 Richtek Technology Corporation. All rights reserved.
DS4831A-05
Default
July 2020
Description
Display Bias Mode
000 : Display Bias Off (I2C
and External) (default)
100 : Normal Mode
101 : Auto Seqence
110 : Wake Up 1
111 : Wake Up 2
Others : Reserved
VPOS Discharge Enable
0 : Not Discharge
1 : Active Discharge (default)
VNEG Discharge Enable
0 : Not Discharge
1 : Active Discharge (default)
VPOS Channel Enable
0 : Disable (default)
1 : Enable
VNEG Channel Enable
0 : Disable (default)
1 : Enable
Display Bias External Control
0 : Disable (default)
1 : Enable
Display Bias Short Mode
00 : Flag Only (default)
01 : Flag Only
10 : Flag with Shutdown
Display Bias
11 : Flag with Shutdown
Display Bias and Backlight
VPOS Ramp Up Time (refer
to Figure 8)
00 : 256s
01 : 512s (default)
10 : 768s
11 : 1024s
VNEG Ramp Up Time (refer
to Figure 8)
0000 : 500s
0001 : 1024s (default)
0010 : 1536s
0011 : 2048s
0100 : 2560s
0101 : 3072s
0110 : 3584s
0111 : 4096s
1000 : 4608s
1001 : 5120s
1010 : 5632s
1011 : 6144s
1100 : 6656s
1101 : 7168s
1110 : 7680s
1111 : 8192s
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RT4831A
Addr
0x0B
0x0C
0x0D
0x0E
RegName
Bit
BitName
Default
Type
7:4
Reserved
0000
RW
VPOS Bias
VNEG Bias
VPOS Short Timer
00 : 2ms (default)
01 : 1ms
10 : 500s
11 : 100s
VNEG Short Timer
00 : 2ms (default)
01 : 1ms
10 : 500s
11 : 100s
DSV_VPOS_SHORT_
TIMER
00
RW
1:0
DSV_VNEG_SHORT
_TIMER
00
RW
7:6
Reserved
00
RW
Reserved
5:0
DSV_VLCM
101000
RW
VLCM Voltage
000000 : 4V
000001 : 4.05V
:
101000 : 6V (default)
:
111111 : 7.15V
7:6
Reserved
00
RW
Reserved
5:0
DSV_VPOS
011110
RW
VPOS Voltage
000000 : 4V
000001 : 4.05V
:
011110 : 5.5V (default)
:
110010 : 6.5V
110011 to 111111 map to
6.5V
7:6
Reserved
00
RW
Reserved
RW
VNEG Voltage
000000 : 4V
000001 : 4.05V
:
011100 : 5.4V (default)
:
110010 : 6.5V
110011 to 111111 map to
6.5V
5:0
DSV_VNEG
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Reserved
3:2
Display Bias
Configuration 3
LCM Bias
Description
011100
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DS4831A-05
July 2020
RT4831A
Addr
RegName
Bit
BitName
Default
Type
7
Reserved
0
RC
Reserved
6
OTP_FLAG
0
RC
Chip Over-Temperature Flag
0 : Normal operation (default)
1 : Thermal shutdown
5
DSV_LCM_OVP_
FLAG
0
RC
Display Bias LCM Output
Over-Voltage Flag
0 : Normal operation (default)
1 : VLCM > 7.8V
4
Reserved
0
RC
Reserved
RC
Display Bias VPOS Output
Short Circuit Flag
0 : Normal operation (default)
1 : VPOS output has hit the
over-current threshold
RC
Display Bias VNEG Output
Short Circuit Flag
0 : Normal operation (default)
1 : VNEG > 0.84 ×
VNEG_target
3
0x0F
DSV_VPOS_SCP_
FLAG
Flags
2
DSV_VNEG_SCP_
FLAG
July 2020
0
1
BLED_OVP_FLAG
0
RC
0
BLED_OCP_FLAG
0
RC
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DS4831A-05
0
Description
Bcaklight Output OverVoltage Flag
0 : Normal operation (default)
1 : Backlight Boost output >
OVP threshold
Bcaklight Boost Over-Current
Flag
0 : Normal operation (default)
1 : Backlight Boost switch
current > OCP threshold
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RT4831A
Addr
0x10
RegName
Backlight Option 1
Bit
BitName
Default
Type
7
Reserved
0
RW
Reserved
6
BLED_CH4_FB_
DISABLE
0
RW
LED4 Feedback Setting
0 : Enable (default)
1 : Disable
5
BLED_CH3_FB_
DISABLE
0
RW
LED3 Feedback Setting
0 : Enable (default)
1 : Disable
4
BLED_CH2_FB_
DISABLE
0
RW
LED2 Feedback Setting
0 : Enable (default)
1 : Disable
3
BLED_CH1_FB_
DISABLE
0
RW
LED1 Feedback Setting
0 : Enable (default)
1 : Disable
RW
PWM Dglitch Filter Time
00 : 0ns
01 : 100ns
10 : 160ns
11 : 200ns (default)
RW
PWM Sampling Frequency
24MHz Enable
0 : Disable (default)
1 : Enable
(Please also see register
0x03)
2:1
0
0x11
0x12
Backlight Option 2
PWM-to-Digital
Code LSB
Readback
BLED_PWM_
DEGLITCH
BLED_PWM_24MHz_
SAMPLE
0
7:6
BLED_L_SELECT
00
RW
Backlight Boost L Select
00 : 4.7H (default)
01 : 10H
10 : 15H
11 : 15H
5:4
BLED_SEL_P
11
RW
Reserved
3:2
BLED_SEL_I
01
RW
Reserved
Backlight Over-Current Limit
00 : 900mA
01 : 1200mA (default)
10 : 1500mA
11 : 1800mA
1:0
BLED_OC
01
RW
7:0
BLED_PWM_TO_
DIG_L
00000000
R
Copyright © 2020 Richtek Technology Corporation. All rights reserved.
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46
11
Description
11 bit PWM-to-Digital
Conversion Code LSBs
is a registered trademark of Richtek Technology Corporation.
DS4831A-05
July 2020
RT4831A
Addr
RegName
Bit
BitName
Default
Type
7:3
Reserved
00000
R
Reserved
0x13
PWM-to-Digital
Code MSB
Readback
2:0
BLED_PWM_TO_
DIG_H
000
R
11 bit PWM-to-Digital
Conversion Code MSBs
7:2
Reserved
000000
R
Reserved
1
BLED_RAMP_DN_
SMOOTH_EN
0
BLED_RAMP_UP_
SMOOTH_EN
7:1
Reserved
0x14
RW
Backlight Smooth Enable for
Ramp Down
0 : Disable (default)
1 : Enable
0
RW
Backlight Smooth Enable for
Ramp Up
0 : Disable (default)
1 : Enable
0000000
R
0
Backlight Smooth
0x15
I2C Protect
0
I2C_SAFE_TIMER_
EN
Copyright © 2020 Richtek Technology Corporation. All rights reserved.
DS4831A-05
July 2020
Description
0
RW
Reserved
I2C safe timer to reset the I2C
slave when SDAO stays low
longer than 1 second.
0 : Disable (default)
1 : Enable
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
47
RT4831A
Thermal Considerations
Layout Considerations
The junction temperature should never exceed the
absolute maximum junction temperature T J(MAX), listed
under Absolute Maximum Ratings, to avoid permanent
damage to the device. The maximum allowable power
dissipation depends on the thermal resistance of the IC
package, the PCB layout, the rate of surrounding airflow,
and the difference between the junction and ambient
temperatures. The maximum power dissipation can be
calculated using the following formula :
The PCB layout is an important step to maintain the high
performance of the RT4831A. Both the high current and
the fast switching nodes demand full attention to the
PCB layout to keep the robustness of the RT4831A
through the PCB layout. Improper layout might lead to
the symptoms of poor line or load regulation, ground
and output voltage shifts, stability issues, unsatisfying
EMI behavior or worsened efficiency. For the best
performance of the RT4831A, the following PCB layout
guidelines must be strictly followed.
PD(MAX) = (TJ(MAX) - TA) / JA
where TJ(MAX) is the maximum junction temperature, T A
is the ambient temperature, and JA is the junction-toambient thermal resistance.
For continuous operation, the maximum operating
junction temperature indicated under Recommended
Operating Conditions is 125°C. The junction-to-ambient
thermal resistance, JA, is highly package dependent.
For a WL-CSP-24B 1.84x2.68 (BSC) package, the
thermal resistance, JA, is 37.1°C/W on a standard
JEDEC 51-7 high effective-thermal-conductivity fourlayer test board. The maximum power dissipation at T A
= 25°C can be calculated as below :
PD(MAX) = (125°C - 25°C) / (37.1°C/W) = 2.69W for a
WL-CSP-24B 1.84x2.68 (BSC) package.
The maximum power dissipation depends on the
operating ambient temperature for the fixed T J(MAX) and
the thermal resistance, JA. The derating curves in
Figure 13 allows the designer to see the effect of rising
ambient temperature on the maximum power
dissipation.
The trace from switching node to inductor should be
as short as possible to minimized the switching loop
for better EMI.
Place the input and output capacitors close to the
input and output pins respectively for good filtering.
Both Backlight and LCD bias inputs must have an
independent capacitor to filter switching noise. The
suggested capacitor value is 10F.
To guarantee IC normal operation, there must have a
dedicated power trace connected from the IN pin to
the input capacitor of Backlight or LCD bias.
Keep the main power traces as wide and short as
possible.
Separate the CP_GND, AGND, LCM_GND and
BL_GND. Each connects to a strong ground plane for
maximum thermal dissipation and noise protection.
Maximum Power Dissipation (W)1
3.0
Four-Layer PCB
2.5
2.0
1.5
1.0
0.5
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 13. Derating Curve of Maximum Power
Dissipation
Copyright © 2020 Richtek Technology Corporation. All rights reserved.
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48
is a registered trademark of Richtek Technology Corporation.
DS4831A-05
July 2020
RT4831A
TOP Layer
2nd Layer
3rd Layer
Bottom Layer
GND
VIN
C2
VBL
C4
L2
C3
C5
C6
D1
VPOS
C+
VPOS
LCM_
OUT
LCM_
SW
BL_
GND
BL_
SW
CP_
GND
LCM_
EN1
SDA
HWEN
LCM_
GND
BL_
SW
C-
LCM_
EN2
SCL
PWM
AGND
BL_
OUT
VNEG
IN
LED4
LED3
LED2
LED1
C9
L1
C1
C7
C8
VNEG
Figure 14. PCB Layout Guide
Copyright © 2020 Richtek Technology Corporation. All rights reserved.
DS4831A-05
July 2020
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
49
RT4831A
Outline Dimension
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
0.500
0.600
0.020
0.024
A1
0.170
0.230
0.007
0.009
b
0.240
0.300
0.009
0.012
D
2.640
2.720
0.104
0.107
D1
E
2.000
1.800
0.079
1.880
0.071
0.074
E1
1.200
0.047
e
0.400
0.016
24B WL-CSP 1.84x2.68 Package (BSC)
Copyright © 2020 Richtek Technology Corporation. All rights reserved.
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50
is a registered trademark of Richtek Technology Corporation.
DS4831A-05
July 2020
RT4831A
Footprint Information
Package
Number of
Pin
Footprint Dimension (mm)
Type
Tolerance
e
NSMD
WL-CSP1.84X2.68-24(BSC)
24
A
B
0.240
0.340
0.270
0.240
0.400
SMD
±0.025
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume
responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable.
However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
Copyright © 2020 Richtek Technology Corporation. All rights reserved.
DS4831A-05
July 2020
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
51
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