®
RT5028A
Integrated PMIC with 4-Channel Synchronous Buck
Converters, 8 LDOs, and MTP Non-Volatile Memory for
Industrial and Automotive Applications
General Description
Features
The RT5028A is a highly-integrated low-power highperformance analog SOC with PMIC in one single chip
designed for Industrial/Automotive applications.
The RT5028A includes four synchronous step-down DCDC converters and eight LDOs for system power.
The RT5028A also embeds one EEPROM (MTP) for setting
sequence and timing etc.
Additionally, the RT5028A PMIC also includes one IRQ
report.
Input Voltage Operating Range is 3.3V to 5.5V
Step-Down Regulator : VIN Range is 3.3V to 5.5V
Max Current 2.4A/2A/1.6A/2A
Programmable Frequency from 500kHz to 2MHz
2
I C Programmable Output Level
2
I C Programmable Operation Mode (Force PWM
or Auto PSM/PWM)
2
I C Programmable Output Discharge Mode
(Discharge or Flatting)
Linear Regulators : VIN Range is 2.5V to 5.5V
Max Current 0.3A
2
I C Programmable Output Level
Embedded 32Bytes MTP for Factory Tuning
External MTP Pin for Write Protection
Sequence can be Controlled by I2C or each EN pins
Defined by MASK_GPIO Pin
OT/UVP/VIN LV/POWRON Press Time Interrupt (IRQ)
2
I C Control Interface : Support Fast Mode up to
400kb/s
Available in AEC-Q100 Grade 3 Qualified
RoHS Compliant and Halogen Free
Ordering Information
RT5028A
Package Type
QW : WQFN-56L 7x7 (W-Type)
Lead Plating System
G : Green (Halogen Free and Pb Free)
Note :
Richtek products are :
RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
Suitable for use in SnPb or Pb-free soldering processes.
Applications
Industrial/Automotive
Simplified Application Circuit
VIN
VOUTLx
RT5028A
VDDP
SCL
SDA
VINL123
IRQ
VINL456
RESET
VINL78
PWRHOLD
PWRON
LXBx
REBOOT
VOUTBxS
MTP
VINBx
MASK_GPIO
ENBx
ENLx
SADDR
AGND
Copyright © 2019 Richtek Technology Corporation. All rights reserved.
DS5028A-06 August 2019
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1
RT5028A
Marking Information
Pin Configuration
RT5028AGQW : Product Number
(TOP VIEW)
AGND
ENL3
ENL2
ENL1
VIN
VDDP
VOUTB1S
ENB1
LXB1
LXB1
VINB1
VINB1
VINB2
VINB2
RT5028A
GQW
YMDNN
YMDNN : Date Code
56 55 54 53 52 51 50 49 48 47 46 45 44 43
VOUTL1
VINL123
VOUTL2
VOUTL3
VOUTL6
VOUTL5
VINL456
VOUTL4
VOUTL7
VINL78
VOUTL8
ENL4
ENL5
ENL6
1
42
2
41
3
40
4
39
5
38
37
6
7
36
AGND
8
35
34
9
33
10
57
11
32
31
12
13
30
14
29
LXB2
LXB2
ENB2
VOUTB2S
VINB3
VINB3
LXB3
LXB3
AGND
VOUTB3S
VINB4
LXB4
ENB3
VOUTB4S
SCL
SDA
ENL7
ENL8
IRQ
RESET
AGND
PWRON
REBOOT
MTP
MASK_GPIO
PWRHOLD
SADDR
ENB4
15 16 17 18 19 20 21 22 23 24 25 26 27 28
WQFN-56L 7x7
Functional Pin Description
Pin No.
Pin Name
Pin Function
1
VOUTL1
Output voltage regulation node for LDO1.
2
VINL123
Input power for LDO1, LDO2 and LDO3.
3
VOUTL2
Output voltage regulation node for LDO2.
4
VOUTL3
Output voltage regulation node for LDO3.
5
VOUTL6
Output voltage regulation node for LDO6.
6
VOUTL5
Output voltage regulation node for LDO5.
7
VINL456
Input power for LDO4, LDO5 and LDO6.
8
VOUTL4
Output voltage regulation node for LDO4.
9
VOUTL7
Output voltage regulation node for LDO7.
10
VINL78
Input power for LDO7 and LDO8.
11
VOUTL8
Output voltage regulation node for LDO8.
12
ENL4
Enable control input for LDO4.
13
ENL5
Enable control input for LDO5.
14
ENL6
Enable control input for LDO6.
15
SCL
Clock input for I2C. Open-drain output.
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DS5028A-06 August 2019
RT5028A
Pin No.
Pin Name
Pin Function
2
16
SDA
Data input for I C. Open-drain output.
17
ENL7
Enable control input for LDO7.
18
ENL8
Enable control input for LDO8.
19
IRQ
Open-drain IRQ output node.
20
RESET
Reset output.
21, 34, 56, 57
AGND
(Exposed Pad)
Analog ground. The exposed pad must be soldered to a large PCB and
connected to AGND for maximum power dissipation.
22
PWRON
Manual power on.
23
REBOOT
System power reboot.
24
MTP
MTP write protection pin. Logic low is inhibited and logic high is permit to write.
25
MASK_GPIO
Select I2C or EN pin for Bucks and LDOs. Connect a 100k pull-low resistor.
As MASK_GPIO is high, ignore all EN pins.
As MASK_GPIO is low, EN pins and I2C both can control. EN pins priority is
higher than I2C.
26
PWRHOLD
Power hold input.
27
SADDR
I2C slave address.
28
ENB4
Enable control input for Buck4.
29
VOUTB4S
Output voltage regulation node for Buck4.
30
ENB3
Enable control input for Buck3.
31
LXB4
Internal switch node to output inductor connection for Buck4.
32
VINB4
Input power for Buck4.
33
VOUTB3S
Output Voltage regulation node for Buck3.
35, 36
LXB3
Internal switch node to output inductor connection for Buck3.
37, 38
VINB3
Input power for Buck3.
39
VOUTB2S
Output voltage regulation node for Buck2.
40
ENB2
Enable control input for Buck2.
41, 42
LXB2
Internal switch node to output inductor connection for Buck2.
43, 44
VINB2
Input power for Buck2.
45, 46
VINB1
Input power for Buck1.
47, 48
LXB1
Internal switch node to output inductor connection for Buck1.
49
ENB1
Enable control input for Buck1.
50
VOUTB1S
Output voltage regulation node for Buck1
51
VDDP
Internal bias regulator voltage. External load on this pin is not allowed.
52
VIN
Input power for analog base.
53
ENL1
Enable control input for LDO1.
54
ENL2
Enable control input for LDO2.
55
ENL3
Enable control input for LDO3.
Copyright © 2019 Richtek Technology Corporation. All rights reserved.
DS5028A-06 August 2019
is a registered trademark of Richtek Technology Corporation.
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3
RT5028A
Functional Block Diagram
VOUTL1
VINL123
LDO1
300mA
VOUTL2
LDO2
300mA
VOUTL3
LDO3
300mA
VOUTL4
VINL456
LDO4
300mA
VOUTL5
LDO5
300mA
VIN
VDDP
Analog
Base
VINB1
Buck1
2.4A
LXB1
GND
VOUTB1S
VINB2
VOUTL6
LDO6
300mA
VOUTL7
VINL78
LDO7
300mA
VOUTL8
LDO8
300mA
Central
Controller
2
I C
Programmable
Buck2
2A
LXB2
GND
SDA
VOUTB2S
VINB3
SCL
IRQ
Buck3
1.6A
RESET
LXB3
PWRHOLD
REBOOT
MTP
State
Machine
GND
VOUTB3S
VINB4
MASK_GPIO
SADDR
PWRON
ENB1 to ENB4
Buck4
2A
LXB4
ENL1 to ENL8
AGND
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4
GND
VOUTB4S
is a registered trademark of Richtek Technology Corporation.
DS5028A-06 August 2019
RT5028A
Absolute Maximum Ratings
(Note 1)
Analog Base Input Voltage, VIN ---------------------------------------------------------------------------------------PMIC Input Voltage, VINL123/456/78, VINB1/2/3/4 ---------------------------------------------------------------PMIC Output Voltage, VOUTLx, VOUTBxS, LXBx ----------------------------------------------------------------PMIC related Other Pins -------------------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C
WQFN-56L 7x7 ------------------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2)
WQFN-56L 7x7, θJA -------------------------------------------------------------------------------------------------------WQFN-56L 7x7, θJC ------------------------------------------------------------------------------------------------------Junction Temperature -----------------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------------------Storage Temperature Range --------------------------------------------------------------------------------------------ESD Susceptibility (Note 3)
HBM (Human Body Model) ----------------------------------------------------------------------------------------------MM (Machine Model) ------------------------------------------------------------------------------------------------------
Recommended Operating Conditions
−0.3V to 6V
−0.3V to 6V
−0.3V to 6V
−0.3V to 6V
3.7W
27°C/W
7°C/W
150°C
260°C
−65°C to 150°C
2kV
200V
(Note 4)
Junction Temperature Range --------------------------------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range --------------------------------------------------------------------------------------------- −40°C to 85°C
Electrical Characteristics
(Note 5)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
--
--
6
V
As f SW > 1MHz, 3.3V VIN 5.5V.
If f SW 1MHz, VIN 4V.
3.3
--
5.5
V
VIN = 5V, LDOs, Bucks are ON with no
load. Bucks operate in auto mode
(Reg0x06 = FFh)
500
700
950
AMR for VIN
Operation Voltage of VIN
PMIC
Quiescent Current
IIN
Warning for Die
Temperature
OTW
Over-Temperature
Protection
OTP
5
30
60
Temperature 1
--
100
--
Temperature 2
--
125
--
--
165
--
C
--
10
--
C
70
115
160
k
OTP and Warning
Hysteresis
Input Pull-Low 100k
Resistor
RLow
VIN = 5V, temperature = 40C to 85C
Copyright © 2019 Richtek Technology Corporation. All rights reserved.
DS5028A-06 August 2019
A
VIN = 5V, SCL = SDA = 0V, LDO and
Bucks are OFF, Disable PMIC
(Reg0x15[7] = 1)
C
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5
RT5028A
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
3.3
--
5.5
V
Buck1 to Buck4
Input Voltage
VINB
Consumption Current
IVINB
AUTO mode IOUT = 0mA, each buck
10
30
50
A
Output Voltage Accuracy
VOUTAcc
3.1V < VIN < 5.5V, 1mA < IOUT < IMAX,
40 < TA < 85C
3
--
3
%
Switching Frequency
f SW
I2C programmable
0.43
--
2
MHz
1MHz f SW
10
--
10
f SW 1MHz
20
--
20
Buck1
3.1
4.4
5.8
Buck2
2.8
4
5.2
Buck3
2.6
3.7
4.8
Buck4
2.8
4.1
5.3
VOUTB1S to VOUTB4S < 0.66 x (VOUT
Target)
56
66
76
Buck1
2.4
--
--
Buck2
2
--
--
Buck3
1.6
--
--
Buck4
2.0
--
--
Switching Frequency
Accuracy
Peak Current Limit
Under-Voltage Protection
Maximum Output Current
OCP
UVP
IMAX
%
A
%
A
High-Side On-Resistance
Rpon
VIN = 3.7V
50
150
250
m
Low-Side On-Resistance
Rnon
VIN = 3.7V
40
110
160
m
2.5
--
5.5
V
LDO1 to LDO8
Input Voltage for
VINL123/456/78
VINL
Output Voltage LDO123/78 VOUTL
3.1V VIN 5.5V, 50A IOUT IMAX
40 < TA < 85C
3
--
3
%
Output Voltage LDO456
VOUTL
3.1V VIN 5.5V, 50A IOUT IMAX
40 < TA < 85C
3
--
3
%
Output Current
IOUT
300
--
--
mA
Output Short Current
Isht
330
450
600
mA
Voltage Difference
VIN VOUT
0.05
0.1
0.3
0.05
0.11
0.5
Supply Current
ISS
10
50
75
A
Shutdown Current
IOFF
0
1
2
A
VIN > 3.1V
VIN > 2.5V
IOUT = 0mA
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VIN = VSET,
IOUT = IOUTMAX
V
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DS5028A-06 August 2019
RT5028A
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
--
--
0.4
V
High-Level VIH
1.5
--
--
Low-Level VIL
--
--
0.4
Isink = 1mA,VIN = 3.3V to 5.5V
--
--
0.2
TA = 25C, VIN = 3.3V to 5.5V
1
0
1
TA = 85C,VIN = 3.3V to 5.5V
--
0.1
--
Control Input Pin Electrical Characteristics
Voltage Output Low
Input Voltage
VOL
V
RESET Pin Electrical Characteristics
Output Low Voltage
RESET
Output High Leakage
RESET
V
A
Note 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. Limits apply to the recommended operating temperature range of −40°C to 85°C, unless otherwise noted. Minimum
and maximum limits are verified through test, design, or statistical correlation. Typical values represent the most likely
parametric norm at TA = 25°C, and are provided for reference purposes only. Unless otherwise stated the following
conditions apply : VIN = 3.3V to 5.5V.
Copyright © 2019 Richtek Technology Corporation. All rights reserved.
DS5028A-06 August 2019
is a registered trademark of Richtek Technology Corporation.
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7
RT5028A
Typical Application Circuit
1µF
1µF
1µF
1µF
1µF
52 VIN
RT5028A
51 VDDP
2 VINL123
7 VINL456
10 VINL78
VOUTL1
VOUTL2
VOUTL3
1
3
4
1µF
1µF
1µF
1µF
VOUTL4
8
1µF
VOUTL5 6
1µF
45, 46
VINB1
VOUTL6 5
10µF
2.2µH
22µF
47, 48
50
43, 44
VOUTL7
LXB1
VOUTB1S
VOUTL8 11
VINB2
SCL
10µF
SDA
2.2µH
22µF
41, 42
39
37, 38
LXB2
VOUTB2S
22µF
VINB3
MTP
MASK_GPIO
35, 36
33
32
SADDR
LXB3
VOUTB3S
1µF
PWRON
VIN
1µF
SADDR
MASK_GPIOMTP
15
16
IRQ 19
20
RESET
26
PWRHOLD
23
REBOOT
10µF
2.2µH
9
As SADDR connect to AGND
slave address
=0111111
As SADDR connect to VIN
slave address
=0110111
24
25
27
As MASK_GPIO connect to AGND
EN pins can control.
As MASK_GPIO connect to VIN
Ignore all EN pins.
22
VINB4
10µF
2.2µH
22µF
31
29
AGND
AP
ENL1 to ENL8
ENB1 to ENB4
LXB4
VOUTB4S
AGND 21, 34, 56,
57 (Exposed Pad)
As MTP connect to AGND
Inhibit to write MTP.
As MTP connect to VIN
Permit to write MTP.
Suggested Components for Typical Application Circuit
Description
Manufacturer
Inductor for Buck-2.2H
LQH43PB2R2M26L
Murata
CIN for Buck-10F
C1206X7R1E516DT
Murata
COUT for Buck-22F
C1206X7R22E416DT
Murata
CIN/COUT for LDO-1F
C0603X7R1E216DT
Murata
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P/N
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DS5028A-06 August 2019
RT5028A
Typical Operating Characteristics
CH1 Buck Efficiency vs. Output Current
CH2 Buck Efficiency vs. Output Current
100
100
90
90
80
VIN
VIN
VIN
VIN
VIN
VIN
70
60
50
40
=
=
=
=
=
=
3.3V
3.6V
3.9V
4.2V
5V
5.5V
Efficiency (%)
Efficiency (%)
80
30
20
VIN
VIN
VIN
VIN
VIN
VIN
70
60
50
40
=
=
=
=
=
=
3.3V
3.6V
3.9V
4.2V
5V
5.5V
30
20
10
10
VOUT = 1.35V, L = 2.2μH, COUT = 10μF
0
VOUT = 1.5V, L = 2.2μH, COUT = 10μF
0
10
100
1000
10000
10
100
Output Current (mA)
CH3 Buck Efficiency vs. Output Current
100
90
90
VIN
VIN
VIN
VIN
VIN
VIN
80
70
60
50
40
3.3V
3.6V
3.9V
4.2V
5V
5.5V
Efficiency (%)
Efficiency (%)
80
=
=
=
=
=
=
30
20
70
60
50
=
=
=
=
=
=
3.6V
3.9V
4.2V
4.5V
5V
5.5V
40
30
20
10
10
VOUT = 1.2V, L = 2.2μH, COUT = 10μF
0
VOUT = 3.3V, L = 2.2μH, COUT = 10μF
0
10
100
1000
10000
10
Output Current (mA)
100
1000
10000
Output Current (mA)
CH2 Buck Output Voltage vs. Output Current
CH1 Buck Output Voltage vs. Output Current
1.39
1.53
1.37
1.36
=
=
=
=
=
=
3.3V
3.6V
3.9V
4.2V
5V
5.5V
1.52
Output Voltage (V)
VIN
VIN
VIN
VIN
VIN
VIN
1.38
Output Voltage (V)
10000
CH4 Buck Efficiency vs. Output Current
100
VIN
VIN
VIN
VIN
VIN
VIN
1000
Output Current (mA)
1.35
1.34
VIN
VIN
VIN
VIN
VIN
VIN
1.51
1.50
=
=
=
=
=
=
3.3V
3.6V
3.9V
4.2V
5V
5.5V
1.49
1.48
1.33
L = 2.2μH, COUT = 10μF
1.32
L = 2.2μH, COUT = 10μF
1.47
0
300
600
900
1200 1500 1800 2100 2400
Output Current (mA)
Copyright © 2019 Richtek Technology Corporation. All rights reserved.
DS5028A-06 August 2019
0
500
1000
1500
2000
Output Current (A)
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RT5028A
CH4 Buck Output Voltage vs. Output Current
CH3 Buck Output Voltage vs. Output Current
3.38
1.25
VIN
VIN
VIN
VIN
VIN
VIN
3.33
1.23
VIN
VIN
VIN
VIN
VIN
VIN
1.22
1.21
1.20
=
=
=
=
=
=
Output Voltage (V)
Output Voltage (V)
1.24
3.3V
3.6V
3.9V
4.2V
5V
5.5V
1.19
3.28
=
=
=
=
=
=
3.6V
3.9V
4.2V
4.5V
5V
5.5V
3.23
3.18
3.13
1.18
L = 2.2μH, COUT = 10μF
L = 2.2μH, COUT = 10μF
3.08
1.17
0
200
400
600
800
0
1000 1200 1400 1600
500
Output Current (mA)
1000
1500
2000
Output Current (mA)
CH1 Buck Output Voltage vs. Input Voltage
CH2 Buck Output Voltage vs. Input Voltage
1.40
1.55
1.39
1.53
Output Voltage (V)
Output Voltage (V)
1.38
1.37
1.36
1.35
IOUT = 0mA
IOUT = 500mA
IOUT = 1000mA
IOUT = 1500mA
IOUT = 2000mA
IOUT = 2400mA
1.34
1.33
1.32
1.31
1.51
1.49
IOUT = 0mA
IOUT = 500mA
IOUT = 1000mA
IOUT = 1500mA
IOUT = 2000mA
1.47
L = 2.2μH, COUT = 10μF
1.30
L = 2.2μH, COUT = 10μF
1.45
3.3
3.8
4.3
4.8
5.3
5.8
3.3
3.8
Input Voltage (V)
4.3
4.8
5.3
5.8
Input Voltage (V)
CH4 Buck Output Voltage vs. Input Voltage
CH3 Buck Output Voltage vs. Input Voltage
3.80
1.24
1.23
3.60
Output Voltage (V)
Output Voltage (V)
1.22
1.21
1.20
1.19
IOUT = 0mA
IOUT = 500mA
IOUT = 1000mA
IOUT = 1600mA
1.18
1.17
3.40
3.20
IOUT = 0mA
IOUT = 500mA
IOUT = 1000mA
IOUT = 1500mA
IOUT = 2000mA
3.00
2.80
1.16
2.60
1.15
L = 2.2μH, COUT = 10μF
L = 2.2μH, COUT = 10μF
2.40
1.14
3.3
3.8
4.3
4.8
5.3
Input Voltage (V)
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5.8
3.3
3.8
4.3
4.8
5.3
5.8
Input Voltage (V)
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DS5028A-06 August 2019
RT5028A
LDO2 Output Voltage vs. Output Current
LDO5 Output Voltage vs. Output Current
3.32
1.790
3.30
VIN
VIN
VIN
VIN
VIN
VIN
1.780
1.775
1.770
=
=
=
=
=
=
2.5V
3V
3.6V
4.2V
5V
5.5V
Output Voltage (V)
Output Voltage (V)
1.785
1.765
1.760
3.28
VIN
VIN
VIN
VIN
VIN
VIN
3.26
3.24
=
=
=
=
=
=
3.3V
3.6V
3.9V
4.2V
5V
5.5V
3.22
1.755
COUT = 1μF
COUT = 1μF
3.20
1.750
0
50
100
150
200
250
0
300
50
2.50
1.78
Output Voltage (V)
Output Voltage (V)
1.78
2.48
2.44
2.42
=
=
=
=
=
=
200
250
300
LDO2 Output Voltage vs. Input Voltage
LDO7 Output Voltage vs. Output Current
2.52
VIN
VIN
VIN
VIN
VIN
VIN
150
Output Current (mA)
Output Current (mA)
2.46
100
2.5V
3V
3.6V
4.2V
5V
5.5V
IOUT = 0mA
1.77
IOUT = 100mA
1.77
IOUT = 200mA
1.76
IOUT = 300mA
1.76
COUT = 1μF
COUT = 1μF
1.75
2.40
0
50
100
150
200
250
300
2.5
3
3.5
4
4.5
5
5.5
Input Voltage (V)
Output Current (mA)
LDO5 Output Voltage vs. Input Voltage
LDO7 Output Voltage vs. Input Voltage
3.50
2.50
3.45
2.48
Output Voltage (V)
Output Voltage (V)
3.40
3.35
3.30
3.25
IOUT = 0mA
IOUT = 100mA
IOUT = 200mA
IOUT = 300mA
3.20
3.15
3.10
2.46
IOUT = 0mA
IOUT = 100mA
IOUT = 200mA
IOUT = 300mA
2.44
2.42
3.05
COUT = 1μF
3.00
COUT = 1μF
2.40
3.3
3.8
4.3
4.8
5.3
Input Voltage (V)
Copyright © 2019 Richtek Technology Corporation. All rights reserved.
DS5028A-06 August 2019
5.8
2.5
3
3.5
4
4.5
5
5.5
Input Voltage (V)
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11
RT5028A
Application Information
The RT5028A is a highly-integrated solution for automotive
system including PMIC and memory system. The
RT5028A application mechanism and I2C compatible
interface are introduced in later sections. The system's
slave address is 0110111 (As SADDR = high) or 0111111(As
SADDR = low).
PMIC - Power management system provides 8 low dropout
linear regulator and 4 high efficiency synchronous stepdown DC-DC converters. Power-On and Power-Off
sequences are control by PWRON and RESET input pins.
Parameter
Symbol
Detail time sequence control is described in Power ON/
OFF diagram. The I2C interface can program individual
regulator output voltage as well as on/off control and
voltage setting.
I2C Interface Timing Diagram
The RT5028A acts as an I2C -bus slave. The I2C-bus master
configures the settings for all function blocks by sending
command bytes to the RT5028A via the 2-wire I2C-bus.
The I2C timing diagrams are list in the following.
Test Conditions
Min
Typ
Max
Unit
SDA, SCLK Input High Level
Threshold
0.7 x
VDDP
--
--
V
SDA, SCLK Input Low Level
Threshold
--
--
0.3 x
VDDP
V
--
--
400
kHz
2
I C Interface Electrical Characteristics
SCLK Clock Rate
f SCL
Hold Time (Repeated) START
Condition.
After this period, the first clock
pulse is generated
tHD;STA
0.6
--
--
s
LOW Period of the SCL Clock
tLOW
1.3
--
--
s
HIGH Period of the SCL Clock
tHIGH
0.6
--
--
s
Set-Up Time for a Repeated
START Condition
tSU;STA
0.6
--
--
s
Data Hold Time
tHD;DAT
0
--
0.9
s
Data Set-Up Time
tSU;DAT
100
--
--
ns
Set-Up Time for STOP
Condition
tSU;STO
0.6
--
--
s
Bus Free Time Between a
STOP and START Condition
tBUF
1.3
--
--
s
Rise Time of Both SDA and
SCL Signals
tR
20
--
300
ns
Fall Time of Both SDA and
SCL Signals
tF
20
--
300
ns
2
--
--
mA
SDA and SCL Output Low Sink
IOL
Current
SDA or SCL voltage = 0.4V
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RT5028A
Read Function
Reading One Indexed Byte of Data from RT (With 1-Byte)
Acknowledge from RT
S
Acknowledge from RT
Slave Address
0
A
Acknowledge from RT
Register Address
R/W
A Sr
Acknowledge from Master
Slave Address
Repeated Start
1
A
Data Byte
A
P
A
P
R/W
1Byte
Reading n Indexed Words of Data from RT (With N-Byte)
Acknowledge from RT
S
Slave Address
Acknowledge from RT
0
A
Register Address
R/W
A Sr
Slave Address
Repeated Start
Acknowledge from Master
Data Byte
Acknowledge from RT
Data Byte
1st Byte
A
R/W
Acknowledge from Master
A
1
Acknowledge from Master
A
……
2nd Byte
Data Byte
Acknowledge from Master
A
(n-1)th Byte
Data Byte
nth Byte
Write Function
Writing One Byte of Data to RT (With 1-Byte)
Acknowledge from RT
S
Slave Address
Acknowledge from RT
0
A
Register Address
Acknowledge from RT
A
Data Byte
A
P
R/W
1Byte
Writing n Bytes of Data to RT (With N-Byte)
Acknowledge from RT
S
Slave Address
Acknowledge from RT
0
A
Register Address
Acknowledge from RT
A
Data Byte
Acknowledge from RT
A
Data Byte
A
…
A
P
R/W
1st Byte
2nd Byte
Acknowledge from RT
Acknowledge from RT
Data Byte
(n-1)th Byte
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A
Data Byte
nth Byte
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RT5028A
PMIC
Power Channels Control Methodology
input voltage. If the voltage exceeds the OVP threshold
(typ value = 5.95V), the device stops operating. As soon
as the voltage drops below the low threshold (typ value =
5.65V), the device starts to operate again. Therefore, overvoltage protection is implemented to prevent the input
voltage from exceeding critical values to damage the
device.
When VIN power Good or PWRON event occurs, the PMIC
will follow the power on sequence to turn on channels.
During normal operation, users can use the REBOOT pin
to restart PMIC again. Another PWROFF event, OTP or
UVP occurs, PMIC will execute the power off. In the
RT5028A PMIC, the UVP event will be set out when the
Buck1 to Buck4s' output voltage is lower than 1/2 x (VOUT).
Base on ISO 7637 test case, if VIN vary violently, the device
will trigger UVP or OVP (VIN rising up slew rate should
be less than 5V/1ms) and then stops operating. The device
needs to do power reset (VIN < 1.7V) to resume operation.
VIN Over-Voltage Protection
The device has a built-in OVP circuit which monitors the
PowerOFF
Edge trigger
Edge trigger
No
No
VIN Power
Good
PWRON
Chcek
Yes
Yes
Mask_GPIO
1
2
(Internal I C)
0
(External Enable Control)
No
External EN
Check
Power On
Sequence
Yes
Yes
Yes
REBOOT
Check
REBOOT
Check
Normal Operation
No
No
No
OTP Check
Yes
VIN OVP
Check
No
UVP Check
Yes
Yes
VIN UVLO
Check
Yes
No
PWROFF
Check
No
Yes
PowerOFF
OTP function can be controlled by 0x16[2]
VOUT UVP function can be controlled by 0x16 [7:4]
VIN_UVLO threshold can be controlled by 0x 0x12[7:5]
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RT5028A
PMIC - POWER ON/OFF Setting
The circuit setting for communication between RT5028A
and AP is showed as below.
VIN
SADDR
MASK_GPIOMTP
SCL
SDA
AGND
IRQ
RESET
PWRHOLD
AP
REBOOT
State
Machine
MTP
MASK_GPIO
SADDR
PWRON
ENL1 to ENL8
As SADDR connect to AGND
slave address
=0111111
As SADDR connect to VIN
slave address
=0110111
As MASK_GPIO connect to AGND
EN pins can control.
As MASK_GPIO connect to VIN
Ignore all EN pins.
ENB1 to ENB4
As MTP connect to AGND
Inhibit to write MTP.
As MTP connect to VIN
Permit to write MTP.
RESET Pin
The RESET comparator features an open drain output.
The RESET pin pull high to input voltage with 10kΩ which
slew rate define as follow.
RESET Falling Slew Rate
RESET Rising Slew Rate
VIN
VIN
Rph
Rph
10k
10k
Tfall = 3 x Rpl x CL = 8ns
Trise = 3 x Rph x CL = 600ns
RESET
RESET
CL= 20pF
CL= 20pF
Rpl
400
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Rpl
400
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RT5028A
GPIO Pin Pull-Up/Down Defined
Pin No.
Pin Name
GPIO Pin Pull-Up/Down Defined
Resistor
12
ENL4
Internal 100k pull low resistor
Internal
13
ENL5
Internal 100k pull low resistor
Internal
14
ENL6
Internal 100k pull low resistor
Internal
15
SCL
Open drain, need to connect 10k pull up
External
16
SDA
Open drain, need to connect 10k pull up
External
17
ENL7
Internal 100k pull low resistor
Internal
18
ENL8
Internal 100k pull low resistor
Internal
22
PWRON
Internal 100k pull up resistor
Internal
23
REBOOT
Internal 100k pull low resistor
Internal
24
MTP
Internal 100k pull low resistor
Internal
26
PWRHOLD
Internal 100k pull low resistor
Internal
27
SADDR
Internal 100k pull low resistor
Internal
28
ENB4
Internal 100k pull low resistor
Internal
30
ENB3
Internal 100k pull low resistor
Internal
40
ENB2
Internal 100k pull low resistor
Internal
49
ENB1
Internal 100k pull low resistor
Internal
53
ENL1
Internal 100k pull low resistor
Internal
54
ENL2
Internal 100k pull low resistor
Internal
55
ENL3
Internal 100k pull low resistor
Internal
Power Hold Function
When the “PWRHOLD” signal does not come during
THOLD time, the RT5028A will do shutdown sequence.
If users want to disable power hold function, set
“DisTHOLD” bit in I2C register 10 bit[0] to disable this
function. In the timing diagram below, the “THOLD” and
“RESET_DLY” can be set by MTP program.
START_TIME
PWRON
BUCK1
……
BUCK4
LDO1
……
LDO8
RESET_DLY
RESET
PWRHOLD
THOLD
Always Low
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Turn off sequence :
First-on-last-Off
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DS5028A-06 August 2019
RT5028A
When AP sends the “PWRHOLD” signal during THOLD time, the RT5028A will keep power-on.
START_TIME
PWRON
BUCK1
……
BUCK4
LDO1
……
LDO8
RESET_DLY
THOLD
RESET
Low to High signal from AP.
PWRHOLD
Timing Based ON/OFF Sequence (PWRON_NORMOFF_EN, Reg0x15[0] = 1)
START_TIME
Normal power on
Normal power off
SHDN_PRESS
PWRON
TSS
BUCK1
TSS
BUCK2
……
BUCK4
TSS
TSS
LDO1
...
……
LDO8
RESET_DLY
RESET
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RT5028A
Level Based ON/OFF Sequence (PWRON_NORMOFF_EN, Reg0x15[0] = 1)
Normal power on
START_TIME
SHDN_PRESS
Normal power off
PWRON
> 80%
BUCK1
8ms
> 80%
8ms
> 80%
BUCK2
8ms
tdly_Buck
BUCK3
> 80%
tdly_Buck
…...
8ms
LDO1
> 80%
LDO2
…...
tdly_LDO
LDO8
RESET_DLY
RESET
Note.
Sequence : BUCK1 BUCK2 BUCK3 BUCK4 LDO1 LDO2 LDO3 LDO4 LDO5 LDO6 LDO7 LDO8
tdly_Buck : 192 x (1/fsw) + 40µs ±35%
tdly_LDO : 110µs ±20% (If previous one channel is Buck, additional delay time 32 x (1/fsw) need to be added to tdly_LDO.)
Abnormal OFF (OTP, Buck 1/2/3/4 UVP)
START_TIME
Normal power on
IRQ Even Occur
Abnormal power off
PWRON
IRQ
SHDN_DLYTIME
BUCK1
TSS
BUCK2
……
BUCK4
TSS
LDO1
……
LDO8
RESET_DLY
RESET
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DS5028A-06 August 2019
RT5028A
Based ON/OFF Sequence by VIN (VINLV_ENSHDN, Reg0x16[1] = 0)
IC POR
VIN
VDDP
600µs
> 80%
BUCK1
> 80%
BUCK2
……
> 80%
BUCK4
> 80%
LDO1
……
LDO8
RESET_DLY
RESET
(VINLV_ENSHDN, Reg0x16[1] = 1; VINLV_SEQ_EN, Reg0x16[0] = 1)
VOFF setting
Reg0x12[7:5]
IC POR
VIN
VDDP
600µs
> 80%
BUCK1
< 8ms
> 80%
8ms
BUCK2
……
> 80%
8ms
BUCK4
> 80%
8ms
LDO1
……
LDO8
RESET_DLY
RESET
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19
RT5028A
PMU On/Off Sequence Setting
In the RT5028A, users can set the power on/off sequence and output voltage by I2C register 0x01 to 0x04 for Buck
output voltage, 0x07 to 0x0E for LDO output voltage and 0x2C to 0X32 for startup sequence setting.
In the table below, users must set one by one (continues number) and missing code is not allowed.
If users miss sequence code, the RT5028A will wait for next channel and the IC will be hold in waiting status.
Buck1
Buck2
Buck3
Buck4
LDO1
LDO2
LDO3
LDO4
LDO5
LDO6
LDO7
LDO8
Output Voltage Setting
Startup Sequence Setting
Buck1Output[5:0]
Buck1_Seq[3:0]
[000000]
[0001]
Buck2Output[5:0]
Buck2_Seq[3:0]
[101100]
[0010]
Buck3Output[5:0]
Buck3_Seq[3:0]
[000000]
[0011]
Buck4Output[5:0]
Buck4_Seq[3:0]
[101100]
[0100]
LDO1OUT[6:0]
LDO1_Seq[3:0]
[0000000]
[0101]
LDO2OUT[6:0]
LDO2_Seq[3:0]
[0101000]
[0110]
LDO3OUT[6:0]
LDO3_Seq[3:0]
[0000000]
[0111]
LDO4OUT[6:0]
LDO4_Seq[3:0]
[0101000]
[1000]
LDO5OUT[6:0]
LDO5_Seq[3:0]
[0000000]
[1001]
LDO6OUT[6:0]
LDO6_Seq[3:0]
[0101000]
[1010]
LDO7OUT[6:0]
LDO7_Seq[3:0]
[0000000]
[1011]
LDO8OUT[6:0]
LDO8_Seq[3:0]
[0101000]
[1100]
Startup Enable Method
(Soft-Start Control)
[10]
Note :
* Output Voltage Setting: fill relative binary code to set the output voltage.
* Startup Sequence Setting :
“0000” denotes no operation (disable).
“0001” denotes first-startup.
“1100 to 1111” denotes last-startup.
If same number, it means startup at the same time.
*Startup Enable Method :
[01] to [11] : each startup enable interval time (1ms, 4ms, 8ms).
[00] : start end voltage (the output voltage's 80%)
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RT5028A
Synchronous Step-Down DC-DC Converter
Four current mode synchronous step-down DC-DC
converters operate with internal power MOSFETs and
compensation network. These channels supply the power
core chip of portable system. They can be operated at
100% maximum duty cycle to extend battery operating
voltage range. When the input voltage is close to the output
voltage, the converter enters low dropout mode with low
output ripple. The operating frequency range of step-down
converter is 0.5MHz to 2MHz.
Four step-down converters have RAMP control function
as the following diagram.
DC-DC 1/2/3/4
Output Voltage4
DC-DC 1/2/3/4
Output Voltage2
DC-DC 1/2/3/4
Output Voltage1
DC-DC 1/2/3/4
Output Voltage3
Input and Output Capacitors Selection
The RT5028A is designed to work with low ESR ceramic
capacitors. The effective value of these capacitors is
defined as the actual capacitance under voltage bias and
temperature. All ceramic capacitors have a large voltage
coefficient, in addition to normal tolerances and
temperature coefficients. Under D.C. bias, the capacitance
value drops considerably. Larger case sizes or higher
voltage capacitors are better in this regard. To help mitigate
these effects, multiple small capacitors can be used in
parallel to bring the minimum effective capacitance up to
the desired value.
The input capacitance, C IN , is needed to filter the
trapezoidal current at the source of the top MOSFET. A
low ESR input capacitor with larger ripple current rating
should be used for the maximum RMS current. RMS
current is given by :
This formula has a maximum at VIN = 2VOUT, where IRMS
= IOUT / 2. This simple worst case condition is commonly
used for design because even significant deviations do
not offer much relief. Note that ripple current ratings from
capacitor manufacturers are often based on only 2000
hours of life, which makes it advisable to either further
derate the capacitor or choose a capacitor rated at a higher
temperature than required. Several capacitors may also
be placed in parallel to meet size or height requirements
in the design. The selection of COUT is determined by the
effective series resistance (ESR) that is required to
minimize voltage ripple, load step transients, and the
amount of bulk capacitance that is necessary to ensure
that the control loop is stable. Loop stability can be
examined by viewing the load transient response as
described in a later section. The output ripple, ΔVOUT, is
determined by :
1
VOUT IL ESR +
8 fSW COUT
The output ripple is highest at maximum input voltage
since DIL increases with input voltage. Multiple capacitors
placed in parallel may be needed to meet the ESR and
RMS current handling requirements. Dry tantalum, special
polymer, aluminum electrolytic and ceramic capacitors are
all available in surface mount packages. Special polymer
capacitors offer very low ESR but have lower capacitance
density than other types. Tantalum capacitors have the
highest capacitance density but it is important to only
use types that have been surge tested for use in switching
power supplies. Aluminum electrolytic capacitors have
significantly higher ESR but can be used in cost-sensitive
applications provided that consideration is given to ripple
current ratings and long-term reliability. Ceramic capacitors
have excellent low ESR characteristics but can have a
high voltage coefficient and audible piezoelectric effects.
The high Q of ceramic capacitors with trace inductance
can also lead to significant ringing.
V
VIN
IRMS = IOUT(MAX) OUT
1
VIN
VOUT
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RT5028A
Using Ceramic Input and Output Capacitors
Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However, care must
be taken when these capacitors are used at the input and
output. When a ceramic capacitor is used at the input
and the power is supplied by a wall adapter through long
wires, a load step at the output can induce ringing at the
input, VIN. At best, this ringing can couple to the output
and be mistaken as loop instability. At worst, a sudden
inrush of current through the long wires can potentially
cause a voltage spike at VIN large enough to damage the
part. Page 8 shows the nominal values of input/output
capacitance recommenced for the RT5028A.
Inductor Selection
For a given input and output voltage, the inductor value
and operating frequency determine the ripple current. The
ripple current ΔIL increases with higher VIN and decreases
with higher inductance :
V
V
IL = OUT 1 OUT
VIN
fOSC L
Having a lower ripple current reduces the ESR losses in
the output capacitors and the output voltage ripple. Highest
efficiency operation is achieved at low frequency with small
ripple current. This, however, requires a large inductor. A
reasonable starting point for selecting the ripple current
is ΔIL = 0.4 (IMAX). The largest ripple current occurs at
the highest VIN. To guarantee that the ripple current stays
below a specified maximum, the inductor value should be
chosen according to the following equation :
VOUT
VOUT
L=
1
fOSC IL(MAX) VIN(MAX)
selected. As the inductance increases, core losses
decrease. However, increased inductance requires more
turns of wire and therefore copper losses will increase.
Ferrite designs have very low core losses and are preferred
at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard” which means that
inductance collapses abruptly when the peak design
current is exceeded.
This results in an abrupt increase in inductor ripple current
and consequent output voltage ripple.
Do not allow the core to saturate!
Different core materials and shapes will change the size/
current and price/current relationship of an inductor. Toroid
or shielded pot cores in ferrite or permalloy materials are
small and don’t radiate energy but generally cost more
than powdered iron core inductors with similar
characteristics. The choice of which style inductor to use
mainly depend on the price vs. size requirements and
any radiated field/EMI requirements.
REBOOT Function
As the REBOOT pin is set from low to high, the REBOOT
function will be active. The REBOOT's FSM is shown as
below. It concludes 100ms de-bouncing time and delay1/
delay2 power off delay time.
Table 1. REBOOT Input Control Setting
Description
delayed2
delayed1
Action
00 : 100ms
01 : 500ms
10 : 1s
11 : 2s
Default
Option
Option
delayed1 power-off then
delayed2 power-on PMIC
Inductor Core Selection
Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite or permalloy cores.
Actual core loss is independent of core size for a fixed
inductor value but it is very dependent on the inductance
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RT5028A
IRQ Table
From “LOW“ to “HIGH” rising
input into REBOOT pin with
100ms debouncing time
We summarize all IRQ items in the register table. All
IRQ_status registers are implemented as reset after read.
If IRQ_enable bit is Low, the IRQ_status bit will not update
status. IRQ_enable will mask IRQ_status to trigger
IRQ_PMIC Low, so the system can decide which interrupt
is necessary.
Wait for delayed1 time
Power off the PMIC
Wait for delayed2 time
Power on the PMIC
Waveform - (when the other IRQ_status are low)
Mask
IRQ_Status
IRQ_Enable_OVP
OVP
Reset after
Read
Reset after
Read
IRQ_Status_OVP
IRQ_PMIC
Waveform - (when the other IRQ_status are low)
* OTW125/OTW100 means the 125°C/100°C pre-warming over-temperature.
EEPROM (MTP) Control Flow
The RT5028A embeds 32 bytes MTP memory, and it allows
users to save some I2C register bank data to MTP. When
the I2C register 0x3A Bit[0]/Bit[1] is wrote to “1”, the
MTP Page1/Page2 will execute erase process firstly.
Because the erase process will be done in every writing
time, the MTP data will be missed. So it would be best
for users to read data from MTP to I2C first before
executing writing process.
Page 1 writing follow :
Set I2C Register 0x3A Bit[4] =1
Reading MTP process
PMU will read MTP data to
relative I2C register bank.
Set I2C Register 0x3A Bit[0]
PMU will erase the MTP page1
data
Writing MTP process
PMU will move relative I2C
register bank data to MTP
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RT5028A
Page 2 writing follow :
Set I2C Register 0x3A Bit[5] =1
Reading MTP process
The maximum power dissipation depends on the operating
ambient temperature for fixed T J(MAX) and thermal
resistance, θJA. The derating curve in Figure 1 allows the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
Maximum Power Dissipation (W)1
PMU will read MTP data to
relative I2C register bank.
Set I2C Register 0x3A Bit[1]
PMU will erase the MTP page2
data
Writing MTP process
PMU will move relative I2C
register bank data to MTP
4.0
Four-Layer PCB
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
WQFN-56L 7x7 package, the thermal resistance, θJA, is
27°C/W on a standard JEDEC 51-7 four-layer thermal test
board. The maximum power dissipation at TA = 25°C can
be calculated by the following formula :
P D(MAX) = (125°C − 25°C) / (27°C/W) = 3.7W for
WQFN-56L 7x7 package
Copyright © 2019 Richtek Technology Corporation. All rights reserved.
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24
50
75
100
125
Ambient Temperature (°C)
Figure 1. Derating Curve of Maximum Power Dissipation
Layout Considerations
For the best performance of the RT5028A, the following
PCB layout guidelines must be strictly followed.
Place the input and output capacitors as close as
possible to the input and output pins respectively for
good filtering.
Keep the main power traces as wide and short as
possible.
The switching node area connected to LX and inductor
should be minimized for lower EMI.
Connect the GND and Exposed Pad to a strong ground
plane for maximum thermal dissipation and noise
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
25
protection.
Directly connect the output capacitors to the feedback
network of each channel to avoid bouncing caused by
parasitic resistance and inductance from the PCB trace.
is a registered trademark of Richtek Technology Corporation.
DS5028A-06 August 2019
RT5028A
VOUTB1
GND
GND
LX should be connected to Inductor by wide and short
trace, keep sensitive compontents away from this trace.
48
47
VINB2
49
VIN
50
VINB2
VIN
51
VINB1
LXB1
52
VINB1
LXB1
53
ENB1
54
VOUTB1S
ENL1
55
VIN VIN
ENL2
56
VDDP
AGND
ENL3
Input/Output capacitors must be
placed as close as possible to the
Input/Output pins.
46
45
44
43
VOUTL1 1
42 LXB2
VIN VINL123 2
41 LXB2
VOUTB2
GND
40 ENB2
GND
VOUTL2
3
VOUTL3
4
39 VOUTB2S
VOUTL6
5
38 VINB3
VOUTL5
6
37 VINB3
VIN
GND
36 LXB3
VIN VINL456 7
VOUTB3
VOUTL4
8
VOUTL7
9
35 LXB3
GND
34 AGND
GND
33 VOUTB3S
VIN VINL78 10
10
VOUTL8 11
32 VINB4 VIN
31 LXB4
ENL4 12
ENL5 13
GND
GND
VOUTB4
30 ENB3
GND
29 VOUTB4S
SCL
ENL7
ENL8
IRQ
/RESET
AGND
22
23
24
25
26
27
28
ENB4
21
SADDR
20
PWRHOLD
19
MTP
18
MASK_GPIO
17
PWRON
16
REBOOT
15
SDA
ENL6 14
GND
Connect the Exposed
Pad to a ground plane.
GND
Figure 2. PCB Layout Guide
Copyright © 2019 Richtek Technology Corporation. All rights reserved.
DS5028A-06 August 2019
is a registered trademark of Richtek Technology Corporation.
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25
RT5028A
Table 2. I2C Register Table
Detail Description
Address
00
Device ID
Bit
Name
Description
[7:4]
VENDOR_ID
[3:0]
CHIP_REV
Address
01
Bit
Name
Read/Write
Reset Value
Vendor Identification : Richtek : 1000b
R
1000
Chip Revision
R
0101
Description
R/W
Reset Value
Buck1 output voltage regulation
000000 : 0.7V, 25mV per step
000001 : 0.725V
…
101100 : 1.8V
…
111111 : 1.8V
R/W
Option
VRC setting
00 : 25mV/10s, 01 : 50mV/10s,
10 : 100mV/10s, 11 : 200mV/10s
R/W
Option
R/W
Reset Value
Buck2 output voltage regulation
000000 : 0.7V, 25mV per step
000001 : 0.725V
…
101100 : 1.8V
…
111111 : 1.8V
R/W
Option
VRC setting
00 : 25mV/10s, 01 : 50mV/10s,
10 : 100mV/10s, 11 : 200mV/10s
R/W
Option
Description
R/W
Reset Value
Buck3 output voltage regulation
000000 : 0.7V, 50mV per step
000001 : 0.75V
…
111010 : 3.6V
…
111111 : 3.6V
R/W
Option
VRC setting
00 : 50mV/10s, 01 : 100mV/10s,
10 : 200mV/10s, 11 : 400mV/10s
R/W
Option
BUCKcontrol1
[7:2]
Buck1Output[5:0]
[1:0]
Buck1VRC
Address
02
BUCKcontrol2
Bit
Name
Description
[7:2]
Buck2Output[5:0]
[1:0]
Buck2VRC
Address
03
Bit
Name
[7:2]
Buck3Output[5:0]
[1:0]
Buck3VRC
BUCKcontrol3
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is a registered trademark of Richtek Technology Corporation.
DS5028A-06 August 2019
RT5028A
Address
04
BUCKcontrol4
Bit
Name
Description
R/W
Reset Value
Buck4 output voltage regulation
000000 : 0.7V, 50mV per step
000001 : 0.75V
…
111010 : 3.6V
…
111111 : 3.6V
R/W
Option
VRC setting
00 : 50mV/10s, 01 : 100mV/10s,
10 : 200mV/10s, 11 : 400mV/10s
R/W
Option
[7:2]
Buck4Output[5:0]
[1:0]
Buck4VRC
Address
05
VRC Control
Bit
Name
Description
R/W
Reset Value
Buck1VRC_EN
Buck1 VRC
0 : disable - voltage ramps up to target voltage
with one time
1 : enable - voltage ramps up to target voltage
with slope control
R/W
Option
Buck2VRC_EN
Buck2 VRC
0 - disable - voltage ramps up to target voltage
with one time
1 - enable - voltage ramps up to target voltage
with slope control
R/W
Option
Buck3VRC_EN
Buck3 VRC
0 : disable - voltage ramps up to target voltage
with one time
1 : enable - voltage ramps up to target voltage
with slope control
R/W
Option
4
Buck4VRC_EN
Buck4 VRC
0 : disable - voltage ramps up to target voltage
with one time
1 : enable - voltage ramps up to target voltage
with slope control
R/W
Option
[3:0]
Reserved
R/W
0000
Address
06
BUCK Mode
Bit
Name
Description
R/W
Reset Value
7
Buck1mode
Buck1 mode
0 : Force PWM
1 : Auto Mode (PSM/PWM)
R/W
Option
6
Buck2mode
Buck2 mode
0 : Force PWM
1 : Auto Mode (PSM/PWM)
R/W
Option
5
Buck3mode
Buck3 mode
0 : Force PWM
1 : Auto Mode (PSM/PWM)
R/W
Option
7
6
5
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27
RT5028A
Buck4 mode
0 : Force PWM
1 : Auto Mode (PSM/PWM)
R/W
Option
Buck1oms
Buck1 output off mode state
0 : floating
1 : Ground-discharged, discharge resistance =
1010 (Typical)
R/W
Option
Buck2oms
Buck2 output off mode state
0 : floating
1 : Ground-discharged, discharge resistance =
1010 (Typical)
R/W
Option
Buck3oms
Buck3 output off mode state
0 : floating
1 : Ground-discharged, discharge resistance =
1010 (Typical)
R/W
Option
0
Buck4oms
Buck4 output off mode state
0 : floating
1 : Ground-discharged, discharge resistance =
1010 (Typical)
R/W
Option
Address
07
LDOcontrol1
Bit
Name
Description
R/W
Reset Value
7
Reserved
R/W
0
R/W
Option
R/W
Reset Value
R/W
0
R/W
Option
R/W
Reset Value
R/W
0
R/W
Option
4
Buck4mode
3
2
1
[6:0]
LDO1OUT[6:0]
Address
08
Bit
Name
7
Reserved
LDO1 output voltage regulation
0000000 : 1.6V, 25mV per step
0000001 : 1.625V
...
1100000 : 3.6V (MAX)
…
1111111 : 3.6V (MAX)
LDOcontrol2
Description
LDO2 output voltage regulation
0000000 : 1.6V, 25mV per step
0000001 : 1.625V
...
1100000 : 3.6V (MAX)
…
1111111 : 3.6V (MAX)
[6:0]
LDO2OUT[6:0]
Address
09
LDOcontrol3
Bit
Name
Description
7
Reserved
[6:0]
LDO3OUT[6:0]
LDO3 output voltage regulation
0000000 : 1.6V, 25mV per step
0000001 : 1.625V
...
1100000 : 3.6V (MAX)
…
1111111 : 3.6V (MAX)
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is a registered trademark of Richtek Technology Corporation.
DS5028A-06 August 2019
RT5028A
Address
0A
LDOcontrol4
Bit
Name
Description
7
Reserved
LDO4 output voltage regulation
0000000 : 3 V, 25mV per step
0000001 : 3.025V
...
0011000 : 3.6V (MAX)
…
1111111 : 3.6V (MAX)
[6:0]
LDO4OUT[6:0]
Address
0B
LDOcontrol5
Bit
Name
Description
7
Reserved
LDO5 output voltage regulation
0000000 : 3V, 25mV per step
0000001 : 3.025V
...
0011000 : 3.6V (MAX)
…
1111111 : 3.6V (MAX)
[6:0]
LDO5OUT[6:0]
Address
0C
LDOcontrol6
Bit
Name
Description
7
Reserved
LDO6 output voltage regulation
0000000 : 3.0V, 25mV per step
0000001 : 3.025V
...
0011000 : 3.6V (MAX)
…
1111111 : 3.6V (MAX)
[6:0]
LDO6OUT[6:0]
Address
0D
LDOcontrol7
Bit
Name
Description
7
Reserved
[6:0]
LDO7UT[6:0]
LDO7output voltage regulation
0000000 : 1.6V, 25mV per step
0000001 : 1.625V
...
1100000 : 3.6V (MAX)
…
1111111 : 3.6V (MAX)
Copyright © 2019 Richtek Technology Corporation. All rights reserved.
DS5028A-06 August 2019
R/W
Reset Value
R/W
0
R/W
Option
R/W
Reset Value
R/W
0
R/W
Option
R/W
Reset Value
R/W
0
R/W
Option
R/W
Reset Value
R/W
0
R/W
Option
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RT5028A
Address
0E
LDOcontrol8
Bit
Name
Description
7
Reserved
LDO8utput voltage regulation
0000000 : 1.6V, 25mV per step
0000001 : 1.625V
...
1100000 : 3.6V (MAX)
…
1111111 : 3.6V (MAX)
R/W
Reset Value
R/W
0
R/W
Option
[6:0]
LDO8T[6:0]
Address
0F
LDOs off mode state
Bit
Name
Description
R/W
Reset Value
LDO8oms
LDO8 output off mode state
0 : floating
1 : Ground-discharged, discharge resistance =
15 (Typical)
R/W
1
LDO7oms
LDO7 output off mode state
0 : floating
1 : Ground-discharged, discharge resistance =
15 (Typical)
R/W
1
LDO6oms
LDO6 output off mode state
0 : floating
1 : Ground-discharged, discharge resistance =
15 (Typical)
R/W
1
LDO5oms
LDO5 output off mode state
0 : floating
1 : Ground-discharged, discharge resistance =
15 (Typical)
R/W
1
LDO4oms
LDO4 output off mode state
0 : floating
1 : Ground-discharged, discharge resistance =
15 (Typical)
R/W
1
LDO3oms
LDO3 output off mode state
0 : floating
1 : Ground-discharged, discharge resistance =
15 (Typical)
R/W
1
LDO2oms
LDO2 output off mode state
0 : floating
1 : Ground-discharged, discharge resistance =
15 (Typical)
R/W
1
LDO1ms
LDO1output off mode state
0 : floating
1 : Ground-discharged, discharge resistance =
15 (Typical)
R/W
1
7
6
5
4
3
2
1
0
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is a registered trademark of Richtek Technology Corporation.
DS5028A-06 August 2019
RT5028A
Address
10
REBOOT/PWRHOLD delay time control
Bit
Name
Description
[7:6]
Delayed2[1:0]
[5:4]
R/W
Reset Value
Delayed2 setting
(00 : 100ms/01 : 500ms/10 : 1s/11 : 2s)
R/W
Option
Delayed1[1:0]
Delayed1 setting
(00 : 100ms/01 : 500ms/10 : 1s/11 : 2s)
R/W
Option
[3:2]
THOLD[1:0]
THOLD setting
(00 : 100ms/01 : 500ms/10 : 1s/11 : 2s)
R/W
Option
1
Reserved
R/W
0
0
DisTHOLD
R/W
Option
Address
11
Bit
Name
R/W
Reset Value
R
111
R/W
0
R/W
Reset Value
R/W
Option
R/W
0
Ignore THOLD Time.
0 : Keep PWRHOLD function.
1 : Ignore PWRHOLD function.
ON Event Setting
Description
Powered on because of
000 : PWRON key-pressed
001 : VIN plugged in
010 : from REBOOT pin event
111 : No event happen
[7:5]
On_Event
[4:0]
Reserved
Address
12
VIN UVLO/Buck On/Off
Bit
Name
Description
VIN UVLO 2.8V to 3.5V per 0.1V to power off
PMIC
000 : 2.8V
001 : 2.9V
010 : 3V
011 : 3.1V
100 : 3.2V
101 : 3.3V
110 : 3.4V
111 : 3.5V
[7:5]
VOFF setting
4
Reserved
3
Buck4
Buck4 control
(0 : Disable Buck4/1 : Enable Buck4)
R/W
Option
2
Buck3
Buck3 control
(0 : Disable Buck3/1 : Enable Buck3)
R/W
Option
1
Buck2
Buck2 control
(0 : Disable Buck2/1 : Enable Buck2)
R/W
Option
0
Buck1
Buck1 control
(0 : Disable Buck1/1 : Enable Buck1)
R/W
Option
Copyright © 2019 Richtek Technology Corporation. All rights reserved.
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31
RT5028A
Address
13
LDOs On/Off
Bit
Name
Description
7
LDO8
6
R/W
Reset Value
LDO8 control
(0 : Disable LDO8 / 1 : Enable LDO8)
R/W
Option
LDO7
LDO7 control
(0 : Disable LDO7 / 1 : Enable LDO7)
R/W
Option
5
LDO6
LDO6 control
(0 : Disable LDO6 / 1 : Enable LDO6)
R/W
Option
4
LDO5
LDO5 control
(0 : Disable LDO5 / 1 : Enable LDO5)
R/W
Option
3
LDO4
LDO4 control
(0 : Disable LDO4 / 1 : Enable LDO4)
R/W
Option
2
LDO3
LDO3 control
(0 : Disable LDO3 / 1 : Enable LDO3)
R/W
Option
1
LDO2
LDO2 control
(0 : Disable LDO2 / 1 : Enable LDO2)
R/W
Option
0
LDO1
LDO1 control
(0 : Disable LDO1 / 1 : Enable LDO1)
R/W
Option
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DS5028A-06 August 2019
RT5028A
Address
14
Bit
Name
[7:6]
START_TIME
[5:4]
L_PRESS_TIME
[3:2]
[1:0]
SHDN_PRESS
RESET_DLY
PWRON(Power On Key) time Parameters
Setting / RESET delay
Description
Startup time setting
00 : 100s (pressing time - low level)
01 : 100ms
10 : 1s
11 : 2s
Long-press time setting (after Power-On,
00 : 1s (falling edge to rising edge)
01 : 1.5s
10 : 2s
11 : 2.5s
Sending short/long-press IRQ to CPU
ex : 1.5s
=> low time < 1.5s (short IRQ)
=> low time > 1.5s but < 6s (shutdown time)
(long IRQ)
=> low time > 6s (shutdown time) (shutdown)
R/W
Reset Value
R/W
Option
R/W
Option
Key-press forced shutdown time setting
00 : 4s/0ms (pressing time : low level)
01 : 6s/1ms
10 : 8s/1ms
11 : 10s/2ms (allow option 0/1/1/2ms by
SHDN_PRESS_SHORT)
R/W
Option
RESET signal delay after the last power startup
is done
00 : 10ms
01 : 50ms
10 : 100ms
11 : 200ms/5ms (allow option 5ms by
RESET_DLY_5ms_EN)
R/W
Option
Copyright © 2019 Richtek Technology Corporation. All rights reserved.
DS5028A-06 August 2019
is a registered trademark of Richtek Technology Corporation.
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33
RT5028A
Address
15
SHDN Control
Bit
Name
Description
7
6
Read/Write
Reset Value
SHDN_CTRL
Power Off setting by CPU, after set, 100ms
delayed power off
0 : Normal operation
1 : Disable the PMIC output
R/W
0
SHDN_TIMING
Disable Buck/LDO only for normal power off
(SHDN_CTRL = 1)
0 : disable at the same time
1 : contrary to the startup timing
(first_on-last_off)
R/W
Option
Delayed shutdown time after send the
(PWRON)key-press-forced-shutdown IRQ
(when IRQ is disable, there is no delay)
00 : 100ms
01 : 500ms
10 : 1s
11 : 2s
R/W
Option
R/W
0
R/W
Option
R/W
Option
R/W
Option
[5:4]
SHDN_DLYTIME
3
Reserved
2
RESET_DLY_5ms_EN
1
0 : 0x14[3:2], SHDN_PRESS time is
4s/6s/8s/10s
SHDN_PRESS_SHORT
1 : 0x14[3:2], SHDN_PRESS time is
0ms/1ms/1ms/2ms
0
PWRON_NORMOFF_EN
0 : 0x14[1:0] = 11, reset delay is 200ms
1 : 0x14[1:0] = 11, reset delay is 5ms
PWRON off sequence
0 : disable this event. 1 : enable this event
Copyright © 2019 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS5028A-06 August 2019
RT5028A
Address
16
Powered off conditions enable setting
Bit
Name
Description
7
BCK1LV_ENSHDN
6
Read/Write
Reset Value
Buck1 output voltage low SHDN
0 : disable this event. 1 : enable this event
R/W
0
BCK2LV_ENSHDN
Buck2 output voltage low SHDN
0 : disable this event. 1 : enable this event
R/W
0
5
BCK3LV_ENSHDN
Buck3 output voltage low SHDN
0 : disable this event. 1 : enable this event
R/W
0
4
BCK4LV_ENSHDN
Buck4 output voltage low SHDN
0 : disable this event. 1 : enable this event
R/W
0
3
PWRON_ENSHDN
PWRON key-pressed forced SHDN
0 : disable this event. 1 : enable this event
R/W
1
2
OT_ENSHDN
Over temperature SHDN
0 : disable this event. 1 : enable this event
R/W
1
1
VINLV_ENSHDN
VIN voltage low (VOFF) SHDN
0 : disable this event. 1 : enable this event
R/W
Option
0
VINLV_SEQ_EN
Off sequence after VIN voltage low (VOFF)
0 : disable this event. 1 : enable this event
R/W
Option
Address
17
OFF Event (Only reset by POR)
Bit
Name
Description
Read/Write
Reset Value
R
1111
R
0000
R/W
0
[7:4]
OFF_Event
[3:0]
Reserved
Address
18 to 27
Powered off because of (Only shows last
power-off event)
0000 : VIN voltage low (VOFF) (Set by reg)
0001 : Buck1 output voltage low
0010 : Buck2 output voltage low
0011 : Buck3 output voltage low
0100 : PWRON key-pressed forced shutdown
0101 : Power Off register setting
0110 : Over temperature event
0111 : Reboot restart.
1000 : Buck4 output voltage low
1001 : PWR_HOLD fail.
1010 : No event happen.
….
1111 : No event happen
16 bytes registers Data Cache (Only reset by
POR)
Copyright © 2019 Richtek Technology Corporation. All rights reserved.
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RT5028A
IRQ_PMIC (Power Channels)
Address
28
IRQ Enable1
Bit
Name
Description
7
OT_IRQ
6
Read/Write
Reset Value
Internal over-temperature was triggered, IRQ
enable
R/W
1
Bck1LV_IRQ
Buck1 output voltage equal 66% x VTarget, IRQ
enable
R/W
1
5
Bck2LV_IRQ
Buck2 output voltage equal 66% x VTarget, IRQ
enable
R/W
1
4
Bck3LV_IRQ
Buck3 output voltage equal 66% x VTarget, IRQ
enable
R/W
1
3
Bck4LV_IRQ
Buck4 output voltage equal 66% x VTarget, IRQ
enable
R/W
1
2
PWRONSP_IRQ
PWRON short press, IRQ enable
(32s deglitch time)
R/W
0
1
PWRONLP_IRQ
PWRON long press, IRQ enable
(32s deglitch time)
R/W
0
0
SYSLV_IRQ
VIN voltage is lower than VOFF, IRQ enable
R/W
0
Address
29
IRQ Status1
Bit
Name
Description
Read/Write
Reset Value
7
OT
Internal over-temperature
R
0
6
Bck1LV
Buck1 output voltage equal 66% x VTarget
R
0
5
Bck2LV
Buck2 output voltage equal 66% x VTarget
R
0
4
Bck3LV
Buck3 output voltage equal 66% x VTarget
R
0
3
Bck4LV
Buck4 output voltage equal 66% x VTarget
R
0
2
PWRONSP
PWRON short press (32s deglitch time)
R
0
1
PWRONLP
PWRON long press (32s deglitch time)
R
0
0
VINLV
VIN voltage is lower than VOFF
R
0
Address
2A
IRQ Enable2
Bit
Name
Description
Read/Write
Reset Value
7
KPSHDN_IRQ
Key-press forced shutdown, IRQ enable
R/W
1
6
PWRONR_IRQ
PWRON press rising edge, IRQ enable
R/W
0
5
PWRONF_IRQ
PWRON press falling edge, IRQ enable
R/W
0
[4:0]
Reserved
R
0000
Address
2B
IRQ Status2
Bit
Name
Description
Read/Write
Reset Value
7
KPSHDN
Key-press forced shutdown
R
0
6
PWRONR
PWRON press rising edge
R
0
5
PWRONF
PWRON press falling edge
R
0
[4:2]
Reserved
R
000
1
OTW125
Internal 125C pre-warning over-temperature.
R
0
0
OTW100
Internal 100C pre-warning over-temperature.
R
0
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RT5028A
Address
2C
PMU On/Off Sequence1
Bit
Name
Description (Setting on/off sequence priority)
(0000 : off, 0001 : first on, 1100 : last on)
(The sequence is planed by first on last off)
[7:4]
Buck2_Seq[3:0]
[3:0]
Buck1_Seq[3:0]
Address
2D
PMU On/Off Sequence2
Bit
Name
Description (Setting on/off sequence priority)
(0000 : off, 0001 : first on, 1100 : last on)
(The sequence is planed by first on last off)
[7:4]
Buck4_Seq[3:0]
[3:0]
Buck3_Seq[3:0]
Address
2E
PMU On/Off Sequence3
Bit
Name
Description (Setting on/off sequence priority)
(0000 : off, 0001 : first on, 1100 : last on)
(The sequence is planed by first on last off)
[7:4]
LDO2_Seq[3:0]
[3:0]
LDO1_Seq[3:0]
Address
2F
PMU On/Off Sequence4
Bit
Name
Description (Setting on/off sequence priority)
(0000 : off, 0001 : first on, 1100 : last on)
(The sequence is planed by first on last off)
[7:4]
LDO4_Seq[3:0]
[3:0]
LDO3_Seq[3:0]
Address
30
PMU On/Off Sequence5
Bit
Name
Description (Setting on/off sequence priority)
(0000 : off, 0001 : first on, 1100 : last on)
(The sequence is planed by first on last off)
[7:4]
LDO6_Seq[3:0]
[3:0]
LDO5_Seq[3:0]
Address
31
PMU On Sequence6
Bit
Name
Description (Setting on/off sequence priority)
(0000 : off, 0001 : first on, 1100 : last on)
(The sequence is planed by first on last off)
[7:4]
LDO8_Seq[3:0]
[3:0]
LDO7_Seq[3:0]
Address
32
Soft-Start Control
Bit
Name
Description
[7:6]
Reserved
Read/Write
Reset Value
Setting Buck2 on/off sequence priority
R/W
Option
Setting Buck1 on/off sequence priority
R/W
Option
Read/Write
Reset Value
Setting Buck4 on/off sequence priority
R/W
Option
Setting Buck3 on/off sequence priority
R/W
Option
Read/Write
Reset Value
Setting LDO2 on/off sequence priority
R/W
Option
Setting LDO1 on/off sequence priority
R/W
Option
Read/Write
Reset Value
Setting LDO4 on/off sequence priority
R/W
Option
Setting LDO3 on/off sequence priority
R/W
Option
Read/Write
Reset Value
Setting LDO6 on/off sequence priority
R/W
Option
Setting LDO5 on/off sequence priority
R/W
Option
Read/Write
Reset Value
Setting LDO8 on/off sequence priority
R/W
Option
Setting LDO7 on/off sequence priority
R/W
Option
Read/Write
Reset Value
R
Option
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37
RT5028A
[5:2]
0000 : First turn on channel decide the
RESET_DLY time.
0001 : Buck1 decide the RESET_DLY time.
Soft-Start End Control ….
0100 : Buck4 decide the RESET_DLY time.
@ MASK_GPIO = 0
0101 : LDO1 decide the RESET_DLY time.
(External Enable pin
define)
….
1100 : LDO8 decide the RESET_DLY time.
….
1111 : LDO8 decide the RESET_DLY time.
R/W
Option
[1:0]
Voltage Level
00 : When output voltage arrives to 80%
VTarget, next channel will turn on.
Soft-Start Voltage level
Soft-start time interval (TSS) :
/ time soft-start control.
01 : 1ms
10 : 4ms
11 : 8ms
R/W
Option
Read/Write
Reset Value
VCO_VRC
VCO input voltage slop.
00: 25mV/10s, 01: 25mV/20s
10: 25mV/40s, 11: 25mV/80s
Note :
The VCO’s voltage input range is 0.375V to
1.8V and the output frequency is 500kHz to
2.18MHz.
R/W
Option
[5:0]
VCO_DVS
VCO input voltage DVS control
000000 : 0.375V (500kHz)
………
111001 : 1.8V (2MHz)
………
111111 : 1.8V (2MHz)
R/W
Option
Address
34
Buck Syn-Clock Spread Spectrum Control
Bit
Name
Description
Read/Write
Reset Value
[7:1]
Reserved
R/W
0000000
0
SSOSC
R/W
Option
Address
3A
EEPROM (MTP) Control
Bit
Name
Description
Read/Write
Reset Value
[7:6]
Reserved
R/W
00
5
MTP Page 2 Read
Read MTP Page 2
R
0
4
MTP Page 1 Read
Read MTP Page 1
R
0
[3:2]
Reserved
R/W
00
1
MTP Page 2 write
Write MTP Page 2, and MTP also needs to be
logic high.
W
0
0
MTP Page 1 write
Write MTP Page 1, and MTP also needs to be
logic high.
W
0
Address
33
Buck Syn-Clock Control
Bit
Name
Description
[7:6]
Buck Clock Spread Spectrum Control
0 : Disable spread spectrum function.
1 : Turn on spread spectrum function.
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DS5028A-06 August 2019
RT5028A
Table 3. I2C to MTP Mapping Table
MTP Page-1
2
I C Register Address
Bit7
Bit6
Bit5
Function
1
1
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
BUCKcontrol2
Buck2Output[5:0]
Buck2VRC
Default
0
0
1
1
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
BUCKcontrol3
Buck3Output[5:0]
Buck3VRC
Default
0
0
1
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
Function
BUCKcontrol4
Meaning
Buck4Output[5:0]
Buck4VRC
Default
0
1
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
Function
VRC Control
Meaning
Buck1VR
C_EN
Buck2VR
C_EN
Buck3VR
C_EN
Buck4VR
C_EN
Reserved
Reserved
Reserved
Reserved
Default
0
0
0
0
0
1
0
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
Function
0x06
Buck1VRC
0
Meaning
0x05
Bit0
0
Function
0x04
Bit1
Default
Meaning
0x03
Bit2
Buck1Output[5:0]
Function
0x02
Bit3
BUCKcontrol1
Meaning
0x01
Bit4
BUCK Mode
Meaning
Buck1
mode
Buck2
mode
Buck3
mode
Buck4
mode
Buck1om
s
Buck2om
s
Buck3om
s
Buck4om
s
Default
0
0
0
0
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
Copyright © 2019 Richtek Technology Corporation. All rights reserved.
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39
RT5028A
2
I C Register Address
Bit7
Bit6
Bit5
Function
Bit4
Bit3
Bit2
Bit1
Bit0
LDOcontrol1
Meaning
Reserved
Default
0
0
1
1
1
1
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
0x07
LDO1OUT[6:0]
Function
LDOcontrol2
Meaning
Reserved
Default
0
0
0
0
1
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
0X08
LDO2OUT[6:0]
Function
LDOcontrol3
Meaning
Reserved
Default
0
0
1
1
1
1
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
0X09
LDO3OUT[6:0]
Function
LDOcontrol4
Meaning
Reserved
Default
0
0
0
1
1
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
0x0A
LDO4OUT[6:0]
Function
LDOcontrol5
Meaning
Reserved
Default
0
0
0
0
0
1
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
0x0B
LDO5OUT[6:0]
Function
LDOcontrol6
Meaning
Reserved
Default
0
0
0
0
0
1
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
0x0C
LDO6OUT[6:0]
Function
LDOcontrol7
Meaning
Reserved
Default
0
0
1
1
1
1
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
0x0D
LDO7OUT[6:0]
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DS5028A-06 August 2019
RT5028A
I2C Register Address
Bit7
Bit6
Bit5
Function
0x0E
Reserved
0
0
1
1
1
1
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
REBOOT/PWRHOLD delay time control
Delayed2[1:0]
Delayed1[1:0]
Default
1
0
1
0
0
0
0
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
THOLD
Reserved DisTHOLD
VIN UVLO (update default value after power on)
VOFF setting
Reserved
Reserved
Reserved
Reserved
Reserved
Default
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
B
B
B
B
Function
Meaning
PWRON time Parameters Setting / RESET delay
START_TIME
L_PRESS_TIME
SHDN_PRESS
RESET_DLY
Default
0
0
0
0
0
0
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
RESET_
SHDN_
PWRON
Function
Meaning
SHDN Control
Reserved
SHDN_
TIMING
SHDN_DLYTIME
Reserved DLY_5ms PRESS_ NORMOF
0x15
_EN
SHORT
F_EN
Default
0
1
1
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
B
A
A
A
A
A
A
A
Reserved
VINLV_
ENSHDN
VINLV_
SEQ_EN
Function
Powered Off conditions enable setting
Meaning
Reserved
Reserved
Reserved
Default
0
0
0
0
0
0
0
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
Function
Reserved Reserved
PMU On/Off Sequence1
Meaning
0x2C
Bit0
Default
Meaning
0x16
Bit1
Reserved
Function
0x14
Bit2
Meaning
Meaning
0x12
Bit3
LDOcontrol8
Function
0x10
Bit4
Buck2_Seq[3:0]
Buck1_Seq[3:0]
Default
0
0
1
0
0
0
0
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
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41
RT5028A
MTP Page-2
2
I C Register Address
Bit7
Bit6
Bit5
Function
Bit3
Bit2
Bit1
Bit0
PMU On/Off Sequence2
Meaning
0x2D
Bit4
Buck4_Seq[3:0]
Buck3_Seq[3:0]
Default
0
0
1
1
0
0
1
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
Function
PMU On/Off Sequence3
Meaning
0x2E
LDO2_Seq[3:0]
LDO1_Seq[3:0]
Default
0
0
1
1
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
Function
PMU On/Off Sequence4
Meaning
0x2F
LDO4_Seq[3:0]
LDO3_Seq[3:0]
Default
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
Function
PMU On/Off Sequence5
Meaning
0x30
LDO6_Seq[3:0]
LDO5_Seq[3:0]
Default
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
Function
PMU On/Off Sequence6
Meaning
0x31
LDO8_Seq[3:0]
LDO7_Seq[3:0]
Default
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
Function
Soft-Start Control
Meaning
Reversed
Reversed
Default
0
0
0
1
1
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
0x32
Soft-Start End Select @ MASK_GPIO = 1
Function
Meaning
0x33
Soft-Start Control
Buck Syn-Clock Control
VCO_VRC
VCO_DVS
Default
0
0
1
1
1
0
0
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
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is a registered trademark of Richtek Technology Corporation.
DS5028A-06 August 2019
RT5028A
2
I C Register Address
Bit7
Bit6
Function
0x34
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Buck Syn-Clock Spread Spectrum Control
Meaning
Reversed
Reversed
Reversed
Reversed
Reversed
Reversed
Reversed
SSOSC
Default
0
0
0
0
0
0
0
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Condition
A
A
A
A
A
A
A
A
Reset Condition
A
Reset by MTP (Register 0x12 VOFF Setting).
B
Reset when VIN < 1.7V.
Copyright © 2019 Richtek Technology Corporation. All rights reserved.
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43
RT5028A
Outline Dimension
1
1
2
2
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Symbol
Dimensions In Millimeters
Dimensions In Inches
Min
Max
Min
Max
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.150
0.250
0.006
0.010
D
6.900
7.100
0.272
0.280
D2
5.150
5.250
0.203
0.207
E
6.900
7.100
0.272
0.280
E2
5.150
5.250
0.203
0.207
e
L
0.400
0.350
0.016
0.450
0.014
0.018
W-Type 56L QFN 7x7 Package
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is a registered trademark of Richtek Technology Corporation.
DS5028A-06 August 2019
RT5028A
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
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