®
Preliminary
RT5036
Power Management IC with Single Cell Li-Battery Switching
Charger Integrated Power Path Controller
General Description
Features
The RT5036 is a highly integrated smart power
management IC which includes: switch-mode single cell
Li-Ion/Li-Polymer battery charger, LDO, synchronize Buck
regulator, Load Switch, and RTC-OSC for portable
applications. The RT5036 also features USB On-The-Go
(OTG) support.
The RT5036 optimizes the charging task by using a control
algorithm to vary the charge rate via different modes,
including pre-charge mode, fast charge mode, and constant
voltage mode. The key charge parameters can be
programmed via the I2C interface. The RT5036 resumes
the charge cycle whenever the battery voltage falls below
an internal threshold and automatically enters sleep mode
when the input power supply is removed.
Four integrated Synchronize Buck Regulators are
designed to provide MAX 1.6/1.6/1.2/1.2A application with
high efficiency.
Four integrated LDOs are designed to provide MAX 0.35/
0.35/0.35/0.35A application.
Two Load Switches are integrated with load Ron. And a
Real Time Clock (RTC) includes time counter and a
32768Hz oscillator for portable applications.
The RT5036 also provides rich protection functions : Over
Current Protection, Under Voltage Protection, Over Voltage
Protection, Over Temperature Protection, and Over Load
Protection.
Ordering Information
Battery Charger
High Accuracy Voltage/Current Regulation
Average Input Current Regulation(AICR) : 0.1/0.5/
0.7/0.9/1/1.5/2A
Minimum Input Voltage Regulation(MIVR) : 4.2V
to 4.8V
Charge Voltage Regulation: 3.65V to 4.4V
Charge Current Regulation: 0.5A to 2A
Synchronous 0.75/1.5MHz Fixed Frequency PWM
Controller With Up To 95% Duty Cycle
Reverse Leakage Protection To Prevent Battery
Drainage
Thermal Regulation
2
IRQ Output For Communication With I C
Battery Temperature Detection
Reverse Boost to Support OTG 1A
4 LDOs
MAX Output Current 0.35/0.35/0.35/0.35A
2
I C Programmable Output Level
4 LV Buck Regulators
MAX Output Current 1.6/1.6/1.2/1.2A
2
I C Programmable Output Level
No Schottky Barrier Diode Required
1.5M/3MHz Fixed Frequency Operation
Auto Discharge Function
RTC Timer and Oscillator
2 Load Switches
Applications
RT5036
Package Type
QW : WQFN-40L 5x5 (W-Type)
Lead Plating System
G : Green (Halogen Free and Pb Free)
Cellular Telephones
Personal Information Appliances
Tablet PC, Power Bank
Portable Instruments
Note :
Richtek products are :
RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.
Suitable for use in SnPb or Pb-free soldering processes.
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS5036-P06_RK
January 2015
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
1
RT5036
Preliminary
Pin Configurations
Marking Information
RT5036GQW : Product Number
(TOP VIEW)
IRQ
SCL
SDA
STB_EN
XTALIN
XTALOUT
PWRON
CLKOUT
RESETB
VOUTSB1
RT5036
GQW
YMDNN
YMDNN : Date Code
40 39 38 37 36 35 34 33 32 31
VINCHG
VMIDCHG
LXCHG
VBOOTCHG
VDDA
VBATS
ISENSN
ISENSP
PPCTRL
TS
1
30
2
29
3
28
27
4
5
26
PGND
6
25
7
24
8
41
23
22
9
21
10
VINB1
LXB1
LXB2
VINB2
VINB4
LXB4
LXB3
VINB3
VOUTSB2
VOUTSB4
VINL1
VOL1
VOL2
VINL234
VOL3
VOL4
VOUTLSW2
VINLSW
VOUTLSW1
VOUTSB3
11 12 13 14 15 16 17 18 19 20
WQFN-40L 5x5
Functional Pin Description
Pin No.
Pin Name
Pin Function
1
VINCHG
Charger Input Voltage For Adaptor/USB Power Source.
2
VMIDCHG
Connection Point Between Reverse Blocking and High Side MOSFET.
3
LXCHG
Internal Switch Node To Output Inductor Connection of Switching Charger
4
VBOOTCHG
Bootstrap Power Node For Switching Charger
5
VDDA
Internal Power For Analog Blocks, Put 1F To GND.
6
VBATS
Battery Voltage Regulation Node for Charger.
7
ISENSN
Charging Current Sensing Negative Node.
8
ISENSP
Charging Current Sensing Positive Node
9
PPCTRL
External Power Path Control. Used to control external power P-MOSFET
to achieve power path operation.
10
TS
Battery Temperature Detection.
11
VINL1
Input Power for LDO1.
12
VOL1
Output Voltage Regulation Node for LDO1.
14
VINL234
Input Power for LDO2, LDO3, LDO 4.
13
VOL2
Output Voltage Regulation Node for LDO2.
15
VOL3
Output Voltage Regulation Node for LDO3.
16
VOL4
Output Voltage Regulation Node for LDO4.
17
VOUTLSW2
Output Pin for Load Switch 2.
18
VINLSW
Input Pin for Load Switches GOOD.
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DS5036-P06_RK
January 2015
RT5036
Preliminary
Pin No.
Pin Name
Pin Function
19
VOUTLSW1
Output Pin for Load Switch 1.
20
VOUTSB3
Output Voltage Regulation Node for Buck3.
21
VOUTSB4
Output Voltage Regulation Node for Buck4.
22
VOUTSB2
Output Voltage Regulation Node for Buck2.
23
VINB3
Input Power for Buck3.
24
LXB3
Internal Switch Node to Output Inductor Connection for Buck3.
25
LXB4
Internal Switch Node to Output Inductor Connection for Buck4.
26
VINB4
Input Power for Buck4.
27
VINB2
Input Power for Buck2.
28
LXB2
Internal Switch Node to Output Inductor Connection for Buck2.
29
LXB1
Internal Switch Node to Output Inductor Connection for Buck1.
30
VINB1
Input Power for Buck1.
31
VOUTSB1
Output Voltage Regulation Node for Buck1.
32
RESETB
33
CLKOUT
Power-On Reset Output and Reset Key Input. Open drain, Connect A
Pull-Up Resister. The pin is high impedance after RT5036 booting
completely, otherwise, the pin is short to GND. Low pulse to triggers soft
reset event.
RTC 32768Hz Clock Output. Open drain.
34
PWRON
Power On Key Input. Low pulse to triggers power-on event.
35
XTALOUT
Crystal Output. This pin’s parasitic capacitance should be kept as low as
possible. Noise interference should also be avoided.
36
XTALIN
Crystal Input. This pin’s parasitic capacitance should be kept as low as
possible. Noise interference should also be avoided.
37
STB_EN
Standby Mode control pin. From low to high will trigger standby mode and
from high to low will leave standby mode.
38
SDA
Data Input For I C. Open Drain, Connect A Pull-Up Resister.
39
SCL
Clock Input For I C. Open Drain, Connect A Pull-Up Resister
40
IRQ
IRQ Output Node. Open drain.
PGND
The exposed pad must be soldered to a large PCB and connected to
PGND for maximum thermal dissipation and current flow.
41 (Exposed Pad)
2
2
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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January 2015
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3
RT5036
Preliminary
Function Block Diagram
VDDA
Analog Base
LDO1 350mA
XTALIN
XTALOUT
CLKOUT
VOL1
Real-Time
Clock (RTC)
LDO2 350mA
VINB4
LDO3 350mA
LXB4
VINL1
DCDC4
1.2A
LDO4 350mA
VOUTSB4
VINL234
VOL2
VOL3
VOL4
Load SW1
300mA
VINLSW
VOUTLSW1
Load SW2
300mA
VOUTLSW2
VINB3
LXB3
DCDC3
1.2A
2
Controller I C
Programmable
VOUTSB3
VINB2
VINCHG
LXB2
DCDC2
1.6A
VMIDCHG
VBOOTCHG
VOUTSB2
LXCHG
VINB1
Charger 2A
OTG 1A
LXB1
DCDC1
1.6A
ISENSP
ISENSN
PPCTRL
VBATS
VOUTSB1
PWRON
SCL
SDA
IRQ
STB_EN
TS
State
Machine
PGND
RESETB
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DS5036-P06_RK
January 2015
RT5036
Preliminary
Flow Chart
Power Channel Flow Chart
Power-Off
No
No
Plug Adaptor
Check
PWRON
Check
Yes
Yes
Power-On
Sequence
Yes
Falling edge at
STB_EN
No
No
No
RESETB
Check
Buck1 to Buck4,
LDO1 to LDO4
level reset to
default value
Normal Operation
Rising-edge at
2
STB_EN pin or I C Set
STB_Trigger =
OverTemp
Check
Protection
Check
Yes
Standby Mode
Yes
No
RESET_Actio
n Check
Yes
No
Yes
PWROFF
Check
Yes
No
No
RESETB
Check
Buck1 to Buck4,
LDO1 to LDO4
level reset to
Normal mode
default value
Yes
delay1 power-off
then delay2
power-on PMIC
RESET_Action
Check
Power-Off
delay1 Power-Off
Note : RESETB Check : From “LOW“ to “HIGH” rising input into RESETB pin with 100ms debouncing time
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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January 2015
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5
RT5036
Preliminary
Stand-By and Wake-Up Flow Chart
PMU operates with
BuckxOutput_N[6:0]/
LDOxOutput_N[6:0]/
LSWxOutput_N[6:0]/
Buckx_EN_N/
LDOx_EN_N/
LSWx_EN_N/
2
I C Setting
BuckxOutput_S[6:0]/
LDOxOutput_S[6:0]/
LSWxOutput_S[6:0]/
Buckx_EN_S/
LDOx_EN_S/
LSWx_EN_S/
No
Rising-edge at STB_EN pin or
2
I C Set STB_Trigger =
Yes
Yes
PMU operates with
BuckxOutput_S[6:0]/
LDOxOutput_S[6:0]/
LSWxOutput_S[6:0]/
Buckx_EN_S/
LDOx_EN_S/
LSWx_EN_S/
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Falling-edge at STB_EN pin
No
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DS5036-P06_RK
January 2015
RT5036
Preliminary
Protection Flow Chart
Power-Off
No
No
Plug Adaptor
Check
Yes
PWRON
Check
Power-On Sequence
Yes
Falling edge at
STB_EN
No
No
Yes
Rising-edge at
STB_EN pin or I2C Set
STB_Trigger =
Normal Operation
Yes
No
No
No
No
Buckx
Output LV
0 to 1 at
LDOx_EN
LDOx
Output LV
Yes
Buckx
Power-Off
BCKxLV_
ENSHDN
LDOx
Power-Off
No
No
VDDA LV
Yes
Yes
VSYSLV_
ENSHDN
VDDALV_
ENSHDN
No
LSWx
Output LV
0 to 1 at
LSWx_EN
Yes
LDOxLV_
ENSHDN
LSWx
Power-Off
LSWxLV_
ENSHDN
VSYS LV
No
Yes
No
Standby Mode
Yes
Yes
0 to 1 at
Buckx_EN
Yes
No
PWROFF
Over Temp.
Yes
Yes
PWRON_
ENSHDN
OT_ENSHDN
Power-Off
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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January 2015
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7
RT5036
Preliminary
Charger Flow Chart
No
Yes
VBAT < VPREC?
Charge with IPREC
No
WT_PRC[1:0] Timer
Expired?
Fast-Charge
Yes
No
WT_FC[2:0] Timer
Expired?
Yes
Charger Disabled
No
Keep in CV Mode
ICHRG < IEOC?
No
No
Termination is
Enabled?
End of Charge
VBAT 4.5V
--
4.5
--
V
VVINCHG < VISENSN
--
VISENSN
--
V
V
Minimum Input Voltage Regulation (MIVR)
Minimum Input Voltage
Regulation
VMIVR
I2C per 0.1V
VMIVR Accuracy
Average Input Current
Regulation (AICR) Accuracy
IAICR
mA
VDDA Regulator
VDDA Voltage
VDDA UVLO
VDDA Falling
2.4
2.5
2.6
VDDA UVLO Hysteresis
VDDA Rising
--
0.2
--
3.65
--
4.4
V
1
--
1
%
Battery Voltage Regulation
Battery Voltage Regulation
VBATREG Accuracy
VBATREG
I2C Programmable Per
25mV
0 to 85C
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RT5036
Preliminary
Parameter
Symbol
Re-Charge
Threshold
(V BATREG
VREC)
Re-Charge Deglitch
tREC
Charging Current Regulation
Output Charging
ICHG
Current
ICHG Accuracy
Pre-Charge
VPREC
Threshold
VPREC Accuracy
Test Conditions
V VBATS Falling, (V BAT REG
V REC ) = programmable
2
I C Per 0.1A, RSENSE = 20m
RSENSE = 20m
2
I C Per 0.1V, rising threshold
Min
Typ
Max
Unit
100
--
300
mV
--
128
--
ms
0.7
--
2
A
-100
--
100
mA
2.3
--
3.8
V
5
--
5
%
150
--
450
mA
20
--
20
%
150
--
600
mA
100
--
100
mA
32
--
256
s
4
--
16
Hrs
0.5
--
4
Hrs
--
0.5
--
mA
--
256
--
ms
2
Pre-Charge Current
IPREC
I C Per 100mA, from VBATS
U100 mode : IPREC will fix 50mA
IPREC Accuracy
Charge Termination Detection
2
End of Charge
Current
IEOC
I C per 50mA, RSENSE = 20m
U100 mode : IEOC will fix 50mA
IEOC Accuracy
RSENSE = 20m
Deglitch Time for
EOC
ICHG < IEOC, VISENSN > VREC
tEOC
2
I C 32/64/128/256us
Charger Timer Protection
2
FastCharge Timer
I C per 2 Hrs
2
PreCharge Timer
Battery Detection
Current
Battery Detection
Time
NTC Monitor
I C 0.5/1/2/4 Hrs
IBATDET
tBATDET
As RNTC is disable, after EOC
Done
As RNTC is disable, after EOC
Done
HOT Threshold
VVTS_HOT
VTS falling, the ratio of VOL1,
VINCHG > V IN(MIN)
--
28
--
%VOL1
WARM Threshold
VVTS_W ARM
VTS falling, the ratio of VOL1,
VINCHG > V IN(MIN)
--
34
--
%VOL1
COOL Threshold
VVTS_COOL
VTS rising, the ratio of VOL1,
VINCHG > V IN(MIN)
--
64
--
%VOL1
COLD Threshold
VVTS_COLD
VTS rising, the ratio of VOL1,
VINCHG > V IN(MIN)
--
74
--
%VOL1
2
--
2
%VOL1
--
1
--
%VPTS
Accuracy of VTS
Low Temperature
Hysteresis
V VT S
Disable Threshold
VVTS_OFF
TS function disable
--
--
5
%VPTS
Battery Absent
Detection
VBAT_ABS
VTS rising, the ratio of VPTS,
VINCHG > V IN(MIN)
--
90
--
%VPTS
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January 2015
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11
RT5036
Parameter
Preliminary
Symbol
Test Conditions
Min
T yp
Max
Unit
PWM Switching Charger
Reverse Block
On-Resistance
High-Side
On-Resistance
Low-Side
On-Resistance
RREV
From VINCHG to VMIDCHG, as
IAICR disable or I AICR = 2A
--
90
--
m
RHS
From VMIDCHG to LXCHG
--
200
--
m
RLS
From CHGLX to PGND
--
90
--
m
V VINCHG = 5V, VISENSN = 4V, and
ICHG = 1.5A,
--
85
--
%
--
1.5
--
MHz
10
--
10
%
--
95
--
%
0
--
--
%
2.4
3
3.6
A
3.625
--
5.2
V
3
--
3
%
VMIDCHG = 5V, V ISENSN = 4V, and
Loading = 1A,
--
85
--
%
As V ISENSN > 3.5V
1
--
--
A
2.4
3.0
3.6
A
--
5.5
--
V
--
200
--
mV
2.9
--
3.6
V
--
--
0.4
V
Charging Efficiency
Oscillator Frequency
fOSC
2
I C for 0.75/1.5 MHz
Frequency Accuracy
Maximum Duty
Cycle
At Minimum Voltage Input
Minimum Duty Cycle
Peak OCP as
Charger Mode
Reverse Boost Mode Operation
To VMIDCHG, I2 C per 25mV
Output Voltage
Level
VMIDCHG setting ≧ VVBATS + 0.4
Output Voltage
Accuracy
Efficiency
MAX Output Current
for VINCHG
Peak Over Current
Protection
VMIDCHG OVP as
Reverse Boost
VMIDCHG OVP
Hysteresis
Minimum Battery
Voltage for Boost.
2
VBATMIN
As Boost Start-Up. I C
programmable Per 0.1V
Output Low Voltage
VOL
IDS = 10mA
SCL /SDA Input
Threshold Voltage
VIH
Logic High Threshold
1.4
--
--
V
VIL
Logic Low Threshold
--
--
0.4
V
--
--
400
kHz
2
I C Characteristics
SCL Clock
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RT5036
Preliminary
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
--
--
0.4
V
Control I/O Pin
Output Low Voltage
(IRQ, RESETB)
VOL
IDS = 10mA
VIH
Logic High Threshold
1.4
--
--
V
VIL
Logic Low Threshold
--
--
0.4
V
2.7
--
5.5
V
0.8
--
3.3
V
--
60
--
dB
350
--
--
mA
500
--
--
mA
--
--
150
mV
Internal Off Discharge
--
1
--
k
VINLSW1, VINLSW2
2.7
--
5.5
V
--
0.2
--
V
600
--
--
mA
2.7
--
5.5
V
Loading = 0mA, no switch, Each
one
--
25
40
A
Each one
--
0.1
1
A
I2C per 25mV
0.8
--
3.3
V
VVINB1 to 4 = 2.7V to 5.5V,
VOUT 1V
VVINB1 to 4 = 2.7V to 5.5V,
VOUT 1V
3
--
3
%
30
--
30
mV
VVINB1 to 4 = 3.6V
--
0.20
--
VVINB1 to 4 = 3.6V
--
0.20
--
1.6
--
--
A
2
--
--
A
Logic Input Threshold
Voltage (PWRON)
LDO1 to LDO4, LSW1, LSW2
VINL1,VINL234 Input
Voltage Range
VVINL1,234
LDO1 to LDO4
Adjustable Output Range
I2C per 25mV
PSRR
VVINL1, 234 = 4V, F = 1kHz,
CVOL1 to 4 = 1F
LDO1 to LDO4 MAX
Current
Output Current Limit for
LDO1 to LDO4
Drop Out Voltage
VVINL1, 234 = 3V, IOUT = 150mA
VVINLSW1, 2 = 3.3V,
IOUT = 500mA
LSW Drop Out Voltage
Output Current Limit for
LSW1, LSW2
Synchronize Buck Regulator1 to Buck Regulator4
VINB1 to VINB4 Input
Voltage Range
VBUCKVIN
Quiescent Current from
VINB1 to VINB4
Shutdown Current from
VINB1 to VINB4
Buck1 to Buck4
Adjustable Output Range
VVOUTSB1 to 4
Output Voltage Accuracy
Output Voltage Accuracy
High-Side
On-Resistance
Low -Side
On-Resistance
Buck 1, 2 Output Current
capability
DC
Buck 1, 2 Output Current
capability
Peak
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January 2015
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13
RT5036
Parameter
Preliminary
Symbol
Test Conditions
Min
Typ
Max
Unit
Output Voltage
Accuracy
VVINL1 to 4 = 2.7V to 5.5V,
VOUT > 1V
3
3
%
Output Voltage
Accuracy
VVINL1 to 4 = 2.7V to 5.5V,
VOUT 1V
30
30
mV
Buck 3, 4 Output
Current capability
DC
1.2
--
--
A
Buck 3, 4 Output
Current capability
Peak
1.5
--
--
A
Oscillator Frequency
VVINB1 to 4 = 3.6V,
Loading = 200mA
--
1.5
--
MHz
100
--
--
%
--
150
--
s
--
--
10
ms
0.1
--
%/V
2.4
--
4.5
V
--
--
3
A
--
32.768
--
kHz
10
--
10
ppm
VDDA
0.3
--
--
V
--
--
0.3
V
--
0.5
1
s
Maximum Duty Cycle
Soft-Start Time
Discharge Time
TSS
COUT of Buck = 10F,
(Note 5)
Line Regulation
RTC
RTC Operation Voltage
RTC Quiescent
Current
RTCPWR > UVLO Threshold,
XIN = XOUT = 14pF
RTC Clock
RTC Clock Accuracy
RTC Operation Voltage = 1.6V to
3.3V
RTC Clock Output
High
Pin C32K Source Out 0.1mA
RTC Clock Output Low
Pin C32K Sink 0.1mA
RTC OSC Startup
Time
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. Guarantee By Design.
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RT5036
Preliminary
Typical Application Circuit
5
VDDA
VINL1
11
VSYS / VOUTBSx
1µF
RT5036
1µF
36 XTALIN
VOL1 12
35 XTALOUT
VINL234
26
VSYS
10µF
2.2µH
VOUTBS4
VOL1
1µF
14
VSYS / VOUTBSx
2.2µF
VINB4
VOL2 13
VOL2
1µF
25 LXB4
VOL3
15
VOL3
10µF
1µF
21
23
VSYS
10µF
2.2µH
VOUTBS3
VOUTSB4
VOL4
16
VOL4
1µF
VINB3
VINLSW
18
VSYS / VOUTBSx
2.2µF
24 LXB3
10µF
VOUTLSW1
19
1µF
20
27
VSYS
10µF
2.2µH
VOUTBS2
VOUTSB3
VOUTLSW2
1µF
VINCHG
30
10µF
2.2µH
VOUTBS1
1
4.3V to 5.5V
10µF
28 LXB2
22
VMIDCHG
VOUTSB2
VINB1
VBOOTCHG
LXCHG
29 LXB1
ISENSP
2
4
3
47nF
1µH
8
10µF
20m
VIO
RPULL1
33
34
PWRON
Button
0.1µF
VIO
RPULL2
40
39
38
AP
37
32
VIO
RPULL3
VOUTSB1
PPCTRL
CLKOUT
VBATS
1µF
VSYS
7
6
1µF
PWRON
To System
22µF
10µF
9
+
Li Battery
Must connect to
VOL1
IRQ
SCL
RTS
SDA
STB_EN
RESETB
TS
10
RNTC
H/W
Reset
Button
41 (Exposed Pad)
PGND
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DS5036-P06_RK
ISENSN
From Adapter / USB
4.7µF
10µF
31
VOUTLSW2
VINB2
10µF
VSYS
17
VOUTLSW1
January 2015
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RT5036
Preliminary
Timing Diagram
PMIC - POWER On/Off DIAGRAM
Timing Based On/Off Sequence
Normal power-off
Normal powe-on
START_TIME
SHDN_PRESS
PWRON
TSS
BUCK1
TSS
BUCK2
……
BUCK4
TSS
TSS
LDO1
...
……
LDO8
RESETB_DLY
RESETB
Level Based On/Off Sequence
Normal power on
START_TIME
Normal power off
SHDN_PRESS
PWRON
~80 %
BUCK1
BUCK2
……
~80 %
~10%
~80 %
~10%
BUCK4
~80 %
~10%
LDO1
……
LDO8
RESETB_
DLY
RESETB
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is a registered trademark of Richtek Technology Corporation.
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RT5036
Preliminary
Abnormal Off
Normal power on
START_TIME
Abnormal power off
IRQ Even Occur
PWRON
IRQ
SHDN_DLYTIME
BUCK1
TSS
BUCK2
……
BUCK4
TSS
LDO1
……
LDO8
RESETB
_DLY
RESETB
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RT5036
Preliminary
Standby mode and wake up by power-on
Sequentially (STANDBY_OFF = 1) example : Enable2, Enable4 turn-off
Turn into Normal
Operation by the falling
edge
Turn into Standby
by the rising edge
STB_EN pin
STB_DLY
STB_DLY
(Enable1)
(Enable2)
(Enable3)
TSS
TSS
STB_DLY
STB_DLY
TSS
STB_DLY
(Enable4)
…
……
(Enable8)
Enable 4 to 8
STB_DLY
Enable 4
to 8 STB_DLY
RESETB
_DLY
RESETB keep high as
standby mode
RESETB
Immediately (STANDBY_OFF = 0) example : Enable2, Enable4 turn-off
Turn into Standby
by the rising edge
Turn into Normal
Operation by the falling
edge
STB_EN pin
STB_DLY
(Enable1)
(Enable2)
TSS
TSS
(Enable3)
STB_DLY
TSS
STB_DLY
(Enable4)
……
TSS
Enable 4 to 8
STB_DLY
(Enable8)
RESETB
_DLY
RESETB
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RESETB keep high as
standby mode
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January 2015
RT5036
Preliminary
Typical Operating Characteristics
Buck1 Load Regulation
1.115
Buck1 Output = 1.1V, Force PWM
1.110
1.105
80
1.100
70
1.095
1.090
VBAT = 4.2V
VBAT = 3.7V
VBAT = 3.3V
1.085
1.080
Buck1 Output = 1.1V, Force PWM
90
Efficiency (%)
VBUCK1 (V)
Buck1 Efficiency
100
50
40
30
1.075
20
1.070
10
1.065
VBAT = 4.2V
VBAT = 3.7V
VBAT = 3.3V
60
0
0
0.4
0.8
1.2
1.6
0
0.4
0.8
I OUT (A)
Buck2 Load Regulation
1.105
1.090
70
Efficiency (%)
VBUCK2 (V)
80
1.085
1.080
VBAT = 4.2V
VBAT = 3.3V
VBAT = 3.7V
1.070
1.065
Buck2 Output = 1.1V, Force PWM
90
1.095
1.075
VBAT = 4.2V
VBAT = 3.7V
VBAT = 3.3V
60
50
40
30
20
1.060
10
1.055
0
0
0.4
0.8
1.2
1.6
0
0.4
0.8
I OUT (A)
1.2
1.6
I OUT (A)
Buck3 Load Regulation
1.114
Buck3 Efficiency
100
Buck3 Output = 1.1V, Force PWM
Buck3 Output = 1.1V, Force PWM
90
1.112
80
Efficiency (%)
1.110
VBUCK3 (V)
1.6
Buck2 Efficiency
100
Buck2 Output = 1.1V, Force PWM
1.100
1.2
I OUT (A)
1.108
1.106
VBAT = 4.2V
VBAT = 3.7V
VBAT = 3.3V
1.104
1.102
VBAT = 3.3V
VBAT = 3.7V
VBAT = 4.2V
70
60
50
40
30
20
1.100
10
1.098
0
0
0.2
0.4
0.6
0.8
1
I OUT (A)
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January 2015
1.2
0
0.2
0.4
0.6
0.8
1
1.2
I OUT (A)
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RT5036
Preliminary
Buck4 Load Regulation
1.52
Buck4 Efficiency
100
Buck4 Output = 1.5V, Force PWM
Buck4 Output = 1.5V, Force PWM
90
1.51
80
Efficiency (%)
VBUCK4 (V)
1.50
1.49
VBAT = 4.2V
VBAT = 3.7V
VBAT = 3.3V
1.48
1.47
70
VBAT = 4.2V
VBAT = 3.7V
VBAT = 3.3V
60
50
40
30
20
1.46
10
1.45
0
0
0.2
0.4
0.6
0.8
1
I OUT (A)
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1.2
0
0.2
0.4
0.6
0.8
1
1.2
I OUT (A)
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RT5036
Preliminary
Application Information
Switching Charger
Charge Mode Operation
The switching charger integrates a synchronous PWM
controller with power MOSFETs to provide Minimum Input
Voltage Regulation (MIVR), Average Input Current
Regulation (AICR), high accuracy current and voltage
regulation, and charge termination. The charger also
features OTG-Boost (On-The-Go).
The switching charger has two operation modes: charge
mode, and boost mode (OTG-Boost). In charge mode,
the switching charger supports a precision charging
system for single cell. In boost mode, the switching
charger works as the boost converter and boosts the
voltage from battery to VINCHG pin for sourcing the OTG
devices.
Notice that the switching charger does not integrate input
power source (AC adapter or USB input) charging
detection. Thus, the switching charger does not set the
charge current automatically. The charge current needs
to be set via I2C interface by the host. The switching charger
application mechanism and I2C compatible interface are
introduced in later sections.
VINCHG
Gate
Driver 1
Protection
OVP, UVLO,
OTP, Timer
VDDA
LXCHG
PGND
SCL
SDA
2
I C
Table 1. MIVR Register Setting Table
MIVR[2:0]
V MIVR
000
Disable
001
4.2V
010
4.3V
011
4.4V
100
4.5V (default)
101
4.6V
110
4.7V
111
4.8V
Charge Profile
Gate
Driver 2
State
Machine
The switching charger features Minimum Input Voltage
Regulation function to prevent input voltage drop due to
insufficient current provided by the adaptor or USB input.
If MIVR function is enabled, the input voltage decreases
when the over current of the input power source occurs.
VINCHG is regulated at a predetermined voltage level
which can be set as 4.2V to 4.8V per 0.1V by I2C interface.
At this time, the current drawn by the switching charger
equals to the maximum current value that the input power
can provide at the predetermined voltage level, instead of
the set value.
VMIDCHG
VBOOTCHG
Loop
Control
Base VDD,
Ibias, VREF,
OSC
Minimum Input Voltage Regulation (MIVR)
Current Sense
ISENSP
ISENSN
PGND
IRQ
Figure 1. Switching Charger Function Block Diagram
The switching charger provides a precision Li-ion or Lipolymer charging solution for single-cell applications. Input
current limit, charge current, termination current, charge
voltage and input voltage MIVR are all programmable via
the I2C interface. In charge mode, the switching charger
has five control loops to regulate input current, charge
current, charge voltage, input voltage MIVR and device
junction temperature. During the charging process, all five
loops (if MIVR is enabled) are enabled and the dominant
one will take over the control.
For normal charging process, the Li-ion or Li-polymer
battery is charged in three charging modes depending on
the battery voltage. At the beginning of the charging
process, the switching charger is in pre-charge mode.
When the battery voltage rises above pre-charge threshold
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RT5036
Preliminary
voltage (VPREC), the switching charger enters fast-charge
mode. Once the battery voltage is close to the regulation
voltage (VBATREG), the switching charger enters constant
voltage mode.
Pre-Charge Mode
For life-cycle consideration, the battery cannot be charged
with large current under low battery condition. When the
VBATS pin voltage is below pre-charge threshold voltage
(VPREC), the charger is in pre-charge mode with a weak
charge current witch equals to the pre-charge current
(IPREC). In pre-charge mode, the charger basically works
as a Linear Charger. The pre-charge current also acts as
the current limit when the VBATS pin is shorted.
The Pre-Charge current levels are 150mA to 450mA
programmed by I2C per 100mA.
Table 3. IPREC Register Setting Table
IPREC[1:0]
Pre-Charge Current
00
150mA (Default)
01
250mA
10
350mA
11
450mA
Fast-Charge Mode and Settings
As the VBATS pin rises above VPREC, the charger enters
fast-charge mode and starts switching. Notice that the
switching charger does not integrate input power source
(AC adapter or USB input) detection. Thus, the switching
charger does not set the charge current automatically.
Unlike the linear charger (LDO), the switching charger
(Buck converter) is a current amplifier. The current drawn
by the switching charger is different from the current into
the battery. The user can set the Average Input Current
Regulation (AICR) and output charge current (ICHRG)
respectively.
Table 2. VPREC Register Setting Table
VPREC[2:0]
Pre-Charge Threshold
0000
2.3V
0001
2.4V
0010
2.5V
0011
2.6V
0100
2.7V
0101
2.8V
0110
2.9V
0111
3V
1000
3.1V
1001
3.2V
1010
3.3V
1011
3.4V
1100
3.5V (Default)
1101
3.6V
1110
3.7V
1111
3.8V
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Cycle-by-Cycle Current Limit
The charger of the switching charger has an embedded
cycle-by-cycle current limit for inductor. Once the inductor
current touches the threshold, the charger stops charging
immediately to prevent over current from damaging the
device. Notice that, the mechanism cannot be disabled
by any way.
Average Input Current Regulation (AICR)
The AICR setting is controlled by I2C. The AICR100 mode
limits the input current to 100mA. The AICR500 mode
limits the input current to 500mA.. If the application does
not need input current limit, it can be disabled also.
The AICR levels are as below table and programmed by
I2C and suitable for USB port and several TA types (5V/
0.7A, 5V/1A, 5V/2A).
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RT5036
Preliminary
Table 4. AICR Register Setting Table
AICR[2:0]
IAICR
000
Disable
001
0.1A
010
0.5A
011
0.7A
100
0.9A (Default)
101
1A
110
1.5A
111
2A
Charge Current (ICHRG)
The charge current into the battery is determined by the
sense resistor (RSENSE) and ICC setting by I2C. The voltage
between the ISENSP and ISENSN pins is regulated to
the voltage control by ICC setting.
As the RSENSE is 20mΩ, the Fast-Charge currents are
700mA to 2A programmed by I2C per 100mA.
Constant Voltage Mode and Settings
The switching charger enters constant voltage mode when
the ISENSN voltage is close to the output-charge voltage
(VBATREG). Once in this mode, the charge current begins
to decrease. For default settings (charge current
termination is disabled), the switching charger does not
turn off and always regulates the battery voltage at VBATREG.
However, once the charge current termination is enabled,
the charger terminates if the charge current is below
termination current (IEOC) in constant-voltage mode. The
charge current termination function is controlled by the
I2C interface. After termination, a new charge cycle restarts
when one of the following conditions is detected :
The VBATS pin voltage falls below the VBATREG as
VREC threshold.
VINCHG Power-On Reset (POR).
Charge or Termination Enable bit toggle or Charger reset
(via I2C interface).
Table 5. ICHG Register Setting Table
Output Charge Voltage (VBATREG)
ICHG[3:0]
VCC
ICHG RSENSE is 20m
0000
10mV
0.5A
0001
12mV
0.6A
0010
14mV
0.7A
0011
16mV
0.8A
0100
18mV
0.9A
0101
20mV
1A
0110
22mV
1.1A
0111
24mV
1.2A
1000
26mV
1.3A
1001
28mV
1.4A
1010
30mV
1.5A (Default)
EOC[2:0]
VEOC
IEOC R SENSE is 20m
1011
32mV
1.6A
000
Disable
Disable
1100
34mV
1.7A
001
3mV
150mA
1101
36mV
1.8A
010
4mV
200mA
1110
38mV
1.9A
011
5mV
250mA (default)
1111
40mV
2A
100
6mV
300mA
101
8mV
400mA
110
10mV
500mA
111
12mV
600mA
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DS5036-P06_RK
January 2015
The output-charge voltage is set by the I2C interface. Its
range is from 3.65V to 4.4V per 25mV.
Termination Current (IEOC)
If the charger current termination is enabled (TE bit =
“1”), the end-of-charge current is determined by both the
termination current sense voltage (VEOC) and sense
resistor (RSENSE). As RSENSE is 20mΩ, IEOC is set by the
I2C interface from 150mA to 600mA per 50mA.
Table 6. EOC Register Setting Table
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RT5036
Preliminary
Input Voltage Protection in Charge Mode
During charge mode, there are two protection mechanisms
against if input power source capability is less than the
charging current setting. One is AICR and the other is
minimum input voltage regulation. A suitable level of AICR
can prevent VINCHG drop by the insufficient capability.
As the AICR setting is not suitable, MIVR will regulate
the VINCHG in the setting level and sink the maximum
current of power source.
Sleep Mode (VVINCHG − VVBATS < VSLP)
The switching charger enters sleep mode if the voltage
drop between the VINCHG and VBATS pins falls below
VSLP. In sleep mode, the reverse blocking switch and
PWM are all turned off. This function prevents battery drain
during poor or no input power source.
OVP threshold. When OVP occurs, the boost converter
stops switching and turns off immediately.
Battery Protection
Battery Over-Voltage Protection in Charge Mode
The switching charger monitors the ISENSN voltage for
output over voltage protection. In charge mode, if the
ISENSN voltage rises above VOVP_BAT x VBATREG, such as
when the battery is suddenly removed, the switching
charger stops charging and then sets fault status bits
and sends out fault pulse at the STAT pin. The condition
is released when the ISENSN voltage falls below (VOVP_BAT
− ΔVOVP_BAT) x VOVP_BAT. The switching charger then
resumes charging process with default settings and the
fault is cleared.
Bucks
Input Over Voltage Protection
When VINCHG rises above the input over voltage threshold,
the switching charger stops charging and then sets fault
status bits. The condition is released when VINCHG falls
below OVP threshold. The switching charger then
resumes charging operation.
The RT5036 includes a synchronous step-down DC/DC
converter that can support the input voltage range from
2.7V to 5.5V. The output current is up to 600mA. The
output voltage can be programmable by I2C. Following
shows the function block of the RT5036 buck.
Reverse Boost Mode Operation (OTG)
Trigger and Operation
The switching charger features OTG-Boost support. When
OTG function is enabled, the synchronous boost control
loop takes over the power MOSFETs and reverses the
power flow from the battery to the VINCHG pin. In normal
boost mode, the VMIDCHG pin is regulated to 5V (typ.)
to support other OTG devices connected to the USB
connector.
Output Over-Voltage Protection
In boost mode, the output over voltage protection is
triggered when the VMIDCHG voltage is above the output
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RT5036
Preliminary
VINB1 to VINB4
UVLO Bias
Supply
VOUTSB1 to
VOUTSB4
Bandgap
Thermal
Shutdown
VREF
Current Limit
Detect
PWM
Control
Logic
Gate
Driver
LXB1 to
LXB4
PGND
Soft-Start
Oscillator
Negative
Inductor Current
Detect
Figure 2. Buck Function Block Diagram
Normally, the high-side MOSFET is turned on by the PWM
control logic block which drives the gate driver block when
VOUTSB1 to VOUTSB4 is lower than the internal
reference voltage. After VOUTSB1 to VOUTSB4 is higher
than the internal reference voltage, the high side MOSFET
will be turned off. While the high side MOSFET is turned
off, the low side MOSFET is turned on until the current of
the inductor is around zero by the negative inductor current
detection block.
When the current of high side MOSFET is over the rating
current, the high side MOSFET is turned off. When the
temperature is over the rating temperature, the high side
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DS5036-P06_RK
January 2015
MOSFET is turned off until the temperature is dropped by
the thermal shutdown block. After the thermal shutdown
is released, VOUTSB1 to VOUTSB4 will be soft-started
again.
IRQ Operation
RT5036 summarize all IRQ items in the register table. All
IRQ_status registers are implemented as reset after read.
And IRQ pin is released only after IRQ_PRez bit is set. If
IRQ Mask bit is High, the IRQ_status bit will not update
status. IRQ_enable will mask IRQ_status to trigger IRQ
Low, so the system can decide which interrupt is
necessary.
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RT5036
Preliminary
I2C Interface
RT5036 I2C slave address = 7'b0111000.
I2C interface support fast mode (bit rate up to 400kb/s). The write or read bit stream (N ≥ 1) is shown below :
Read N bytes from RT5036
Slave Address
Register Address
S
0
1
Data 2
A
Data for Address = m
LSB
MSB
Data N
LSB
A
A
Register Address
S
0
R/W
A
MSB
Data 1
LSB
A
Assume Address = m
P
Data for Address = m+N-1
Data for Address = m+1
Write N bytes to RT5036
Slave Address
LSB
A
Assume Address = m
MSB
Data 1
MSB
A Sr
A
R/W
Slave Address
MSB
Data 2
LSB
A
Data for Address = m
MSB
A
Data for Address = m+1
Data N
LSB
A P
Data for Address = m+N-1
Driven by Master,
Driven by Slave (RT5033),
P Stop,
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S Start,
Sr Repeat Start
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RT5036
Preliminary
I2C Registers Table
Switching Charger Parts
Name
Function
Addr
ID
ID
0x00
Reset
0x36
Bit
Mode
name
Reset Value Description
[7:4]
R
VENDOR_ID
0011
Vendor Identification
[3:0]
R
CHIP_REV_ID
0110
CHIP_REV_ID
Name
Function
Addr
CHGControl1
Charger Control1
0x01
Reset
0x90
Bit
Mode
name
Reset Value Description
AICR setting :
000 - Disable
001 - 0.1A
010 - 0.5A
100
011 - 0.7A
100 - 0.9A (default)
101 - 1.0A
110 - 1.5A
111 - 2A
The OCP level of buck mode selection bit
1
0 - OCP = 3A,
1 - OCP = 4A
[7:5]
R/W
IAICR[2:0]
4
R/W
Higher_OCP
3
R/W
TE
0
Termination enable
1 - Enable charge current termination,
0 - Disable charge current termination
2
R/W
Sel_SWFreq
0
The switching frequency selection bit (Charger/OTG)
0 - the switching frequency is 1.5MHz,
1 - the switching frequency is 0.75MHz
1
R/W
HZ
0
0
R/W
OPA_MODE
0
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January 2015
1-High impedance mode, 0-Not high impedance mode
(default 0)
1 - Boost mode for OTG
0 - Charger mode (default 0)
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RT5036
Preliminary
Name
Function
Addr
Reset
CHGControl2
Charger Control2
0x02
0x58
name
Reset Value
Bit
Mode
Description
Battery regulation voltage. The delta-V of the Battery
regulation voltage is 25mV.
00 0000 - CHG: 3.65V, OTG: 3.625V
00 0001 - CHG: 3.675V, OTG: 3.65V
00 0010 - CHG: 3.7V, OTG : 3.675V
00 1101 - CHG: 3.975V, OTG: 3.95V
...
00 1110 - CHG: 4V, OTG: 3.975V
00 1111 - CHG: 4.025V, OTG: 4V
...
01 0110 - CHG: 4.2V, OTG: 4.175V (default)
01 1010 - CHG: 4.3V, OTG: 4.275V
…
01 1011 - CHG: 4.325V, OTG: 4.3V
01 1100 - CHG: 4.350V, OTG: 4.325V
01 1101 - CHG: 4.375V, OTG: 4.35V
01 1110 - CHG: 4.4V, OTG: 4.375V
…
11 0111 - CHG: 4.4V, OTG: 5.0V
…
11 1110 - CHG: 4.4V, OTG: 5.175V
11 1111 - CHG: 4.4V, OTG: 5.2V
Reserved
[7:2]
R/W
CV[5:0]
010110
[1:0]
R/W
Reserved
00
Name
Function
Addr
Reset
CHGControl3
Charger Control3
0x04
0xFF
name
Reset Value
Description
Bit
Mode
7
R/W
PP_BCK_SEL
1
EOC termination behavior selection. It’s only works
when SW_HW_CTRL = 1
0 : Disable Buck and supply power from power path
PMOS.
1 : Disable Power Path MOS (Power supplied from
Buck). (Default)
6
R/W
CHGOTG_EN
1
Charger OTG enable
0 – Charger and OTG mode are disabled,
1 – Charger and OTG mode can be enabled
[5:3]
R/W
WT_FC[2:0]
111
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28
Fast charge Timer
000 – 4hrs
001 – 6hrs
010 – 8hrs
011 – 10hrs
is a registered trademark of Richtek Technology Corporation.
DS5036-P06_RK
January 2015
RT5036
Preliminary
Bit
Mode
name
Reset Value
[5:3]
R/W
WT_FC[2:0]
111
[2:1]
R/W
WT_PRC[1:0]
11
0
R/W
EN_TMR
1
Name
Function
Addr
Reset
CHGControl4
Charger Control4
0x05
0x83
name
Reset Value
Description
Bit
Mode
[7:5]
R/W
MIVR[2:0]
100
[4:3]
R/W
IPREC[1:0]
00
[2:0]
R/W
EOC[2:0]
011
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS5036-P06_RK
January 2015
Description
100 – 12hrs
101 – 14hrs
110 – 16hrs
111 – 16hrs
Pre-charge charge Timer
00 – 0.5 hrs
01 – 1hrs
10 – 2hrs
11 – 4hrs
0 - Disable internal timer function,
1 - Enable internal timer function (default 1)
VMIVR
000 - Disable
001 - 4.2V
010 - 4.3V
…
100 – 4.5V (default)
101 - 4.6V
110 - 4.7V
111 - 4.8V
Pre-Charge Current
00 - 150mA (default)
01 - 250mA
10 - 350mA
11 - 450mA
Termination Current (IEOC RSENSE is 20m )
000 - Disable
001 - 150mA
010 - 200mA
011 - 250mA (default)
100 - 300mA
101 - 400mA
110 - 500mA
111 - 600mA
is a registered trademark of Richtek Technology Corporation.
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29
RT5036
Preliminary
Name
Function
Addr
Reset
CHGControl5
Charger Control5
0x06
0xAC
Description
Charging regulation current
External Sensing R : Charge current sense voltage
(current equivalent for 20m sense resistor)
0000 - 10mV (0.5A)
0001 - 12mV (0.6A)
0010 - 14mV (0.7A)
0011 - 16mV (0.8A)
………….
1010 - 30mV (1.5A) (default)
………….
1100 - 34mV (1.7A)
1101 - 36mV (1.8A)
1110 - 38mV (1.9A)
1111 - 40mV (2A)
Pre-Charge Threshold (Rising threshold with hysteresis
of 200mV)
0000 - 2.3V
0001 - 2.4V
…
0100 - 2.7V
0101 - 2.8V
…
1100 – 3.5 (default)
1101 – 3.6V
1110 – 3.7V
1111 - 3.8V
Bit
Mode
name
Reset Value
[7:4]
R/W
ICHG[3:0]
1010
[3:0]
R/W
VPREC[3:0]
1100
Name
Function
Addr
Reset
CHGControl6
Charger Control6
0x07
0xBC
Description
Bit
Mode
Name
Reset Value
7
R/W
Reserved
1
Reserved
6
R/W
TMR_PAUSE
0
0 – Internal timer keeps counting (default)
1 – Internal timer stops counting
5
R/W
[4:3]
[2:0]
R/W
Reverse Block
ON/OFF
Reserved
11
R/W
BATLV
100
1
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30
0 – Turn Off Reverse Block as OTG mode
1 – Turn On Reverse Block as OTG mode
Reserved
Low battery voltage threshold (Falling threshold with
hysteresis of 400mV)
000 : 2.5V
001 : 2.6V
010 : 2.7V
011 : 2.8V (default)
100 : 2.9V
101 : 3V
110 : 3.1V
111 : 3.2V
is a registered trademark of Richtek Technology Corporation.
DS5036-P06_RK
January 2015
RT5036
Preliminary
Name
Function
Addr
Reset
CHGControl7
Charger Control7
0x08
0x01
Description
Bit
Mode
Name
Reset Value
7
R/W
CC_JEITA
0
Charging current setting bit for JEITA
1 – ICHG / 2,
0 – ICHG,
6
R/W
OTG_OLP_BLK
0
When OTG OLP occurs,
0 : Enter HZ mode (Default)
1 : Disable UUG only and reverse boost keeps working.
[5:4]
R/W
Reserved
00
[3:2]
R/W
VRECHG
00
1
R/W
Reserved
0
0
R/W
TS_EN
1
Name
Function
Addr
Reset
RESET of CHG
RESET of CHG
0x09
0x00
Description
Bit
Mode
Name
Reset Value
7
R/W
CHG_RST
0
[6:0]
R/W
Reserved
0000000
Reserved
Re-Charge Level
00 – CV-0.1V
01 – CV-0.2V.
10 – CV-0.3V.
11 – CV-0.3V.
Reserved
TS shutdown ENABLE for TSHOT and TSCOLD.
0 : Disable TS shutdown function.
1 : Enable TS shutdown function. (Default)
Write this bit to reset charger related registers
1 – Charger in reset mode,
0 – No effect, Read : always get “0”
Reserved
Name
Function
Addr
Reset
CHG_IRQ1
Charger IRQ1
0x10
0x00
Bit
Mode
Name
Reset Value
Description
7
R
Reversed
0
6
R
VINOVPI
0
5
R
IEOCI
0
4
R
PPBATLVI
0
Reversed
CHGVIN over voltage protection. Set when CHGVIN >
VIN_OVP is detected
Charging is terminated. It would not be triggered if TE bit
is low.
BAT is in low level (power path need to be turned off)
3
R
VINCHG_Plugin
0
1 : VINCHG connected, 0 : Not connected
2
R
VINCHG_Plugout
0
1 : VINCHG removed, 0 : Not removed
1
R
CHBADADPI
0
Charger fault. Bad VIN source (Input source detect)
0
Detection result of battery absence detection
0 : Battery exists
1 : Detected battery-absence from battery detection of
either one：
a. TS > 90%*VPTS
b. Battery detection when EOC
c. Battery absence when adapter plug-in
0
R
BAT_Absence
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS5036-P06_RK
January 2015
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
31
RT5036
Preliminary
Name
Function
Addr
Reset
CHG_IRQ2
Charger IRQ2
0x11
0x00
Bit
Mode
Name
Reset Value
Description
7
R
CHRVPI
0
Charger fault. Reverse protection fault (VIN < BATS +
VSLP)
6
R
Reserved
0
Reserved
5
R
CHBATOVI
0
Charger fault. Battery OVP
4
R
CHTERMI
0
The charging current is lower than end-of-charge
current. The charger keeps charging.
3
R
CHRCHGI
0
Re-Charge request.
2
R
CHTMRFI
0
Charger fault. Time-out (fault)
[1:0]
R
Reserved
00
Reserved
Name
Function
Addr
Reset
CHG_IRQ3
Charger IRQ3
0x12
0x00
Description
Bit
Mode
Name
Reset Value
7
R
BSTVMIDOVP
0
Boost fault. VMID OVP
5
R
CHBSTLOWVI
0
Charge or Boost fault. Battery voltage is too low
[4:1]
R
Reserved
0000
0
R
CHG_STAT2 _ALT
0
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32
Reserved
Any Event in CHG_STAT2 changes, IRQ indicator.
is a registered trademark of Richtek Technology Corporation.
DS5036-P06_RK
January 2015
RT5036
Preliminary
Name
Function
CHG_IRQ1_MASK Charger IRQ1 Mask
Addr
Reset
0x13
0x0C
Description
Bit
Mode
Name
Reset Value
7
R/W
Reversed
0
Reversed
6
R/W
VINOVPIM
0
CHGVIN OVP fault interrupt mask
0 – interrupt is not masked,
1 – interrupt is masked
5
R/W
IEOCM
0
Charge terminated interrupt mask
0 – Interrupt is not masked
1 – Interrupt is masked
4
R/W
PPBATLVM
0
BAT is in low level (power path need to be turned off)
0 – Interrupt is not masked
1 – Interrupt is masked
1
VINCHG connected, IRQ interrupt mask
(UVP detects VINCHG > UVLO)
0 – Interrupt is not masked
1 – Interrupt is masked
3
R/W
VINCHG_PluginM
2
R/W
VINCHG_PlugoutM
1
VINCHG removed, IRQ interrupt mask
(UVP detects VINCHG < UVLO)
0 – Interrupt is not masked
1 – Interrupt is masked
1
R/W
Reversed
0
Reversed
0
R/W
BAT_Absence
0
BAT absence interrupt mask.
0 – Interrupt is not masked
1 – Interrupt is masked
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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January 2015
is a registered trademark of Richtek Technology Corporation.
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33
RT5036
Name
CHG_IRQ2_
MASK
Bit
Mode
Preliminary
Function
Charger IRQ2
Mask
Name
Addr
Reset
0x14
0x80
Reset Value
Description
7
R/W
CHRVPIM
1
Charger reverse protection interrupt mask
0 – Interrupt is not masked
1 – Interrupt is masked
6
R/W
Reserved
0
Reserved
5
R/W
CHBATOVIM
0
Charger battery over voltage interrupt mask
0 – Interrupt is not masked
1 – Interrupt is masked
4
R/W
CHTERMIM
0
Charge current is lower than EOC current interrupt
mask
0 – Interrupt is not masked,
1 – Interrupt is masked
3
R/W
CHRCHGIM
0
Charger Re-Charge request interrupt mask
0 – Interrupt is not masked,
1 – Interrupt is masked
2
R/W
CHTMRFIM
0
Charger timeout interrupt mask
0 – Interrupt is not masked,
1 – Interrupt is masked
[1:0]
R/W
Reserved
00
Reserved
Function
Charger IRQ3
Mask
Name
Addr
Reset
0x15
0x0F
Reset Value
Description
Name
CHG_IRQ3_
MASK
Bit
Mode
7
R/W
BSTVMIDOVPM
0
Boost VMID over voltage interrupt mask
0 – Interrupt is not masked,
1 – Interrupt is masked
5
R/W
BSTLOWVIM
0
Boost mode low battery voltage interrupt mask
0 – Interrupt is not masked,
1 – Interrupt is masked
4
R/W
Reserved
0
Reserved
0
R/W
CHG_STAT2
_ALTM
0
Any Event in CHG_STAT2 changes, interrupt mask
0 – Interrupt is not masked,
1 – Interrupt is masked
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is a registered trademark of Richtek Technology Corporation.
DS5036-P06_RK
January 2015
RT5036
Preliminary
Name
Function
Addr
Reset
CHG_STAT
Charger status
0x16
0x02
Name
Reset Value
Bit
Mode
7
R/W
EXT_PMOS_CTRL
0
6
R
VBAT_VL
0
Description
Control external PPC PMOS on/off
0 - Disable PMOS
1 - Enable PMOS
Battery voltage level:
0: Battery voltage is lower than pre-charge level
1: Battery voltage is higher than pre-charge level
[5:4]
R
CHG_STAT
00
Charging Status
00：Ready to charge
01：Charge in progress
10：Charge Done
11：Charge Fault
3
R
BOOST_STAT
0
1 : Boost mode, 0 : Not in Boost mode
2
R
Reserved
0
1
R/W
SW_HW_CTRL
1
0
R/W
CHG_ENB
0
Reserved
Power path control by SW or HW
0 - Software decide
1 - Hardware decide
Charge Disable
1 - charger is disabled,
0 - charger is enabled
Name
Function
Addr
Reset
CHG_STAT2
Charger STAT2
0x17
0x00
Name
Reset Value
Description
Bit
Mode
7
R
PWR_RDY
0
Power status bit
0 : CHGVIN > VOVP
or CHGVIN < ISENSN + VSLP (Power Fault)
1 : CHGVIN < VOVP & CHGVIN > ISENSN + VSLP
(Power Ready)
6
R
CHTREGI
0
Charger warning.
0 - Thermal regulation loop inactive.
1 - Thermal regulation loop active.
5
R
CHMIVRI
0
Charger warning.
0 - MIVR regulation loop inactive.
1 – MIVR regulation loop active.
4
R
CHGAICRI
0
Charger warning. AICR regulation loop active.
0 - AICR regulation loop inactive.
1 - AICR regulation loop active.
0
Battery HOT Fault
0 –TS not in HOT region
1 – TS in HOT region, and charger disabled
automatically.
3
R
TSHOT
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS5036-P06_RK
January 2015
is a registered trademark of Richtek Technology Corporation.
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35
RT5036
Preliminary
Bit
Mode
Name
Reset Value
2
R
TSWAR
0
Battery WARM Fault
0 –TS not in WARM region
1 – TS in WARM region
1
R
TSCOOL
0
Battery COOL Fault
0 –TS not in COOL region
1 – TS in COOL region
TSCOLD
0
Battery COLD Fault
0 – TS not in COLD region
1 – TS in COLD region, and charger disabled
automatically.
Name
Function
Addr
Reset
CHG_STAT2_MASK
Charger
STAT2_MASK
0x18
0x70
Description
0
R
Description
Bit
Mode
Name
Reset Value
7
R/W
PWR_RDYM
0
Charger Power ON Ready, interrupt mask
0 – Interrupt is not masked,
1 – Interrupt is masked
1
Charger warning. Thermal regulation loop active,
interrupt mask
0 – Interrupt is not masked,
1 – Interrupt is masked
1
Charger warning. Input voltage MIVR loop active,
interrupt mask
0 – Interrupt is not masked,
1 – Interrupt is masked
6
5
R/W
R/W
CHTREGIM
CHMIVRIM
4
R/W
CHGAICRIM
1
Charger warning. AICR regulation loop active, interrupt
mask
0 – Interrupt is not masked,
1 – Interrupt is masked
3
R/W
TSHOTM
0
Battery HOT Fault, , interrupt mask
0 – Interrupt is not masked,
1 – Interrupt is masked
2
R/W
TSWARMM
0
Battery WARM Fault, interrupt mask
0 – Interrupt is not masked,
1 – Interrupt is masked
1
R/W
TSCOOLM
0
Battery COOL Fault, interrupt mask
0 – Interrupt is not masked,
1 – Interrupt is masked
0
R/W
TSCOLDM
0
Battery COLD Fault, interrupt mask
0 – Interrupt is not masked,
1 – Interrupt is masked
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS5036-P06_RK
January 2015
RT5036
Preliminary
PMIC Parts
Name
BUCK1 Control
Normal
Bit
Mode
Function
BUCK1 Output
Control
Name
Addr
Reset
0x41
0x0C
Reset Value
Description
IRQ pin reset trigger. From low to high will reset IRQ pin
and keep it in low within Tmsk, and after Tmsk expired.
IRQ_PRez will be set to “0”
Buck1 output voltage regulation (default by OTP
0000000 – 0.8V, 25mV per step
0000001 – 0.825V
-0010000 – 1.2V
-0011100 – 1.5V.
-1100101 – 3.3V
1111111 – 3.3V
7
R/W
IRQ_PRez
0
[6:0]
R/W
Buck1
Output_N[6:0]
0001100
Name
Function
Addr
Reset
BUCK1 Control
Standby
BUCK1 Output
Control
0x71
0x0C
Description
Bit
Mode
Name
Reset Value
7
R/W
Reversed
0
[6:0]
R/W
Buck1
Output_S [6:0]
0001100
Name
Bit
Mode
Function
BUCK2
Output
Control
Name
7
R/W
Reversed
0
[6:0]
R/W
Buck2
Output_N
[6:0]
0001100
BUCK2 Control
Normal
January 2015
-0011100 – 1.5V.
-1100101 – 3.3V
1111111 – 3.3V
Addr
Reset
0x42
0x0C
Reset Value
Description
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS5036-P06_RK
Reversed
Buck1 output voltage regulation (default by OTP)
0000000 – 0.8V, 25mV per step
0000001 – 0.825V
-0010000 – 1.2V
Reversed
Buck2 output voltage regulation (default by OTP)
0000000 – 0.8V, 25mV per step
0000001 – 0.825V
-0010000 – 1.2V
-0011100 – 1.5V
-1100101 – 3.3V
1111111 – 3.3V
is a registered trademark of Richtek Technology Corporation.
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37
RT5036
Preliminary
Name
Function
Addr
Reset
BUCK2 Control
Standby
BUCK2 Output
Control
0x72
0x0C
Description
Bit
Mode
Name
Reset Value
7
R/W
Reversed
0
[6:0]
R/W
Buck2 Output_S
[6:0]
0001100
Name
BUCK3 Control
Normal
Bit
Mode
Function
BUCK3 Output
Control
Name
Reversed
Buck2 output voltage regulation (default by OTP)
0000000 – 0.8V, 25mV per step
0000001 – 0.825V
-0010000 – 1.2V
-0011100 – 1.5V.
-1100101 – 3.3V
1111111 – 3.3V
Addr
Reset
0x43
0x64
Reset Value
Description
7
R/W
Reversed
0
[6:0]
R/W
Buck3 Output_N
[6:0]
1100100
Name
Function
Addr
Reset
BUCK3 Control
Standby
BUCK3 Output
Control
0x73
0x58
Description
Bit
Mode
Name
Reset Value
7
R/W
Reversed
0
[6:0]
R/W
Buck3 Output_S
[6:0]
1011000
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38
Reversed
Buck3 output voltage regulation (default by OTP)
0000000 – 0.8V, 25mV per step
0000001 – 0.825V
-0010000 – 1.2V
-0011100 – 1.5V.
-1100101 – 3.3V
1111111 – 3.3V
Reversed
Buck3 output voltage regulation (default by OTP)
0000000 – 0.8V, 25mV per step
0000001 – 0.825V
-0010000 – 1.2V
-0011100 – 1.5V.
-1100101 – 3.3V
1111111 – 3.3V
is a registered trademark of Richtek Technology Corporation.
DS5036-P06_RK
January 2015
RT5036
Preliminary
Name
BUCK4 Control
Normal
Function
BUCK4 Output
Control
Addr
Reset
0x44
0x1C
Description
Bit
Mode
Name
Reset Value
7
R/W
Reversed
0
[6:0]
R/W
Buck4 Output_N
[6:0]
0011100
Name
Function
Addr
Reset
BUCK4 Control
Standby
BUCK4 Output
Control
0x74
0x10
Description
Bit
Mode
Name
Reset Value
7
R/W
Reversed
0
[6:0]
R/W
Buck4
Output_S[6:0]
0010000
Name
BUCK VRC Control
Normal
Bit
Mode
Function
BUCK VRC
Control
Name
Reversed
Buck4 output voltage regulation (default by OTP)
0000000 – 0.8V, 25mV per step
0000001 – 0.825V
-0010000 – 1.2V
-0011100 – 1.5V.
-1100101 – 3.3V
1111111 – 3.3V
Reversed
Buck4 output voltage regulation (default by OTP)
0000000 – 0.8V, 25mV per step
0000001 – 0.825V
-0010000 – 1.2V
-0011100 – 1.5V.
-1100101 – 3.3V
1111111 – 3.3V
Addr
Reset
0x45
Option
Reset Value
Description
[7:6]
R/W
Buck1 VRC_N[1:0]
00
VRC Setting
00 – 25mV/10s, 01 – 50mV/10s, 10 – 75mV/10s,11
– 100mV/10s,
[5:4]
R/W
Buck2 VRC_N[1:0]
00
VRC Setting
00 – 25mV/10s, 01 – 50mV/10s, 10 – 75mV/10s,11
– 100mV/10s,
[3:2]
R/W
Buck3 VRC_N[1:0]
00
VRC Setting
00 – 25mV/10s, 01 – 50mV/10uS, 10 – 75mV/10s,11
– 100mV/10s,
[1:0]
R/W
Buck4 VRC_N[1:0]
00
VRC Setting
00 – 25mV/10s, 01 – 50mV/10s, 10 – 75mV/10s,11
– 100mV/10s,
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS5036-P06_RK
January 2015
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
39
RT5036
Preliminary
Name
Function
Addr
Reset
BUCK VRC
Control Standby
BUCK VRC
Control
0x75
Option
Name
Reset Value
Description
Bit
Mode
[7:6]
R/W
Buck1 VRC_S[1:0]
00
VRC Setting
00 – 25mV/10s, 01 – 50mV/10s, 10 – 75mV/10s,
11 – 100mV/10s,
[5:4]
R/W
Buck2 VRC_S[1:0]
00
VRC Setting
00 – 25mV/10s, 01 – 50mV/10s, 10 – 75mV/10s,
11 – 100mV/10s,
[3:2]
R/W
Buck3 VRC_S[1:0]
00
VRC Setting
00 – 25mV/10s, 01 – 50mV/10s, 10 – 75mV/10s,
11 – 100mV/10s,
[1:0]
R/W
Buck4 VRC_S[1:0]
00
VRC Setting
00 – 25mV/10s, 01 – 50mV/10s, 10 – 75mV/10s,
11 – 100mV/10s,
Function
BUCK VRC
Enable
Addr
Reset
0x46
0xF0
Name
Reset Value
Description
Name
BUCK VRC Enable
Normal
Bit
Mode
7
R/W
Buck1VRC_EN_N
1
6
R/W
Buck2VRC_EN_N
1
5
R/W
Buck3VRC_EN_N
1
4
R/W
Buck4VRC_EN_N
1
[3:0]
R/W
Reversed
0000
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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40
Buck1 VRC Normal
0 – Disable – voltage ramps up to target voltage with
one time
1 – Enable – voltage ramps up to target voltage with
slope control
Buck2 VRC Normal
0 – Disable – voltage ramps up to target voltage with
one time
1 – Enable – voltage ramps up to target voltage with
slope control
Buck3 VRC Normal
0 – Disable – voltage ramps up to target voltage with
one time
1 – Enable – voltage ramps up to target voltage with
slope control
Buck4 VRC Normal
0 – Disable – voltage ramps up to target voltage with
one time
1 – Enable – voltage ramps up to target voltage with
slope control
Reversed
is a registered trademark of Richtek Technology Corporation.
DS5036-P06_RK
January 2015
RT5036
Preliminary
Name
Function
Addr
Reset
BUCK VRC Enable
Standby
BUCK VRC
Enable
0x76
0xF0
Name
Reset Value
Description
Bit
Mode
Buck1 VRC Normal
0 – Disable – voltage ramps up to target voltage with one
time
1 – Enable – voltage ramps up to target voltage with
slope control
Buck2 VRC Normal
0 – Disable – voltage ramps up to target voltage with one
time
1 – Enable – voltage ramps up to target voltage with
slope control
Buck3 VRC Normal
0 – Disable – voltage ramps up to target voltage with one
time
1 – enable – voltage ramps up to target voltage with
slope control
Buck4 VRC Normal
0 – Disable – voltage ramps up to target voltage with one
time
1 – Enable – voltage ramps up to target voltage with
slope control
7
R/W
Buck1VRC_EN_S
1
6
R/W
Buck2VRC_EN_S
1
5
R/W
Buck3VRC_EN_S
1
4
R/W
Buck4VRC_EN_S
1
[3:0]
R/W
Reversed
0000
Name
Function
Addr
Reset
BUCK Mode
BUCK Mode
0x47
0x0F
Description
Reversed
Bit
Mode
Name
Reset Value
7
R/W
Buck1mode
0
Buck1 mode
0 – Force PWM
1 – Auto Mode (PSM/PWM)
6
R/W
Buck2mode
0
Buck2 mode
0 – Force PWM
1 – Auto Mode (PSM/PWM)
5
R/W
Buck3mode
0
Buck3 mode
0 – Force PWM
1 – Auto Mode (PSM/PWM)
4
R/W
Buck4mode
0
Buck4 mode
0 – Force PWM
1 – Auto Mode (PSM/PWM)
3
R/W
Buck1oms
1
Buck1 output off mode state
0 – floating
1 – Ground-discharged
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS5036-P06_RK
January 2015
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
41
RT5036
Preliminary
Bit
Mode
Name
Reset Value
Description
2
R/W
Buck2oms
1
Buck2 output off mode state
0 – Floating
1 – Ground-discharged
1
R/W
Buck3oms
1
Buck3 output off mode state
0 – Floating
1 – Ground-discharged
0
R/W
Buck4oms
1
Buck4 output off mode state
0 – Floating
1 – Ground-discharged
Name
Function
Addr
Reset
LDO1Control
Normal
Bit
Mode
LDO1 Output
Control
Name
0x48
0x64
Reset Value
Description
7
R/W
Reversed
0
[6:0]
R/W
LDO1
Output_N[6:0]
1100100
Name
Function
Addr
Reset
LDO1Control
Standby
LDO1 Output
Control
0x78
0x58
Description
Bit
Mode
Name
Reset Value
7
R/W
Reversed
0
[6:0]
R/W
LDO1 Output_S
[6:0]
1011000
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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42
Reversed
LDO1 output voltage regulation (default by OTP)
0000000 – 0.8V, 25mV per step
0000001 – 0.825V
-0010000 – 1.2V
-0011100 – 1.5V.
-1100101 – 3.3V
1111110 – 3.3V
1111111 – Full On
Reversed
LDO1 output voltage regulation (default by OTP)
0000000 – 0.8V, 25mV per step
0000001 – 0.825V
-0010000 – 1.2V
-0011100 – 1.5V.
-1100101 – 3.3V
1111110 – 3.3V
1111111 – Full On
is a registered trademark of Richtek Technology Corporation.
DS5036-P06_RK
January 2015
RT5036
Preliminary
Name
LDO2 Control
Normal
Bit
Mode
Function
LDO2 Output
Control
Name
Addr
Reset
0x49
0x0C
Reset Value
Description
7
R/W
Reversed
0
[6:0]
R/W
LDO2 Output_N
[6:0]
0001100
Name
Function
Addr
Reset
LDO2 Control
Standby
LDO2 Output
Control
0x79
0x0C
Description
Bit
Mode
Name
Reset Value
7
R/W
Reversed
0
[6:0]
R/W
LDO2 Output_S
[6:0]
0001100
Name
LDO3 Control
Normal
Bit
Mode
Function
LDO3 Output
Control
Name
Reset
0x4A
0x50
Reset Value
Description
R/W
Reversed
0
[6:0]
R/W
LDO3 Output_N
[6:0]
1010000
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
January 2015
Reversed
LDO2 output voltage regulation (default by OTP)
0000000 – 0.8V, 25mV per step
0000001 – 0.825V
-0010000 – 1.2V
-0011100 – 1.5V.
-1100101 – 3.3V
1111110 – 3.3V
1111111 –Full On
Addr
7
DS5036-P06_RK
Reversed
LDO2 output voltage regulation (default by OTP)
0000000 – 0.8V, 25mV per step
0000001 – 0.825V
-0010000 – 1.2V
-0011100 – 1.5V.
-1100101 – 3.3V
1111110 – 3.3V
1111111 –Full On
Reversed
LDO3 output voltage regulation (default by OTP)
0000000 – 0.8V, 25mV per step
0000001 – 0.825V
-0010000 – 1.2V
-0011100 – 1.5V.
-1100101 – 3.3V
1111110 – 3.3V
1111111 – Full On
is a registered trademark of Richtek Technology Corporation.
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43
RT5036
Preliminary
Name
Function
Addr
Reset
LDO3 Control
Standby
LDO3 Output
Control
0x7A
0x28
Description
Bit
Mode
Name
Reset Value
7
R/W
Reversed
0
[6:0]
R/W
LDO3 Output_S
[6:0]
0101000
Name
LDO4 Control
Normal
Bit
Mode
Function
LDO4 Output
Control
Name
Reversed
LDO3 output voltage regulation (default by OTP)
0000000 – 0.8V, 25mV per step
0000001 – 0.825V
-0010000 – 1.2V
-0011100 – 1.5V.
-1100101 – 3.3V
1111110 – 3.3V
1111111 – Full On
Addr
Reset
0x4B
0x28
Reset Value
Description
7
R/W
Reversed
0
[6:0]
R/W
LDO4
Output_N[6:0]
0101000
Name
Function
Addr
Reset
LDO4 Control
Standby
LDO4 Output
Control
0x7B
0x28
Description
Bit
Mode
Name
Reset Value
7
R/W
Reversed
0
[6:0]
R/W
LDO4
Output_S[6:0]
0101000
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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44
Reversed
LDO4 output voltage regulation (default by OTP)
0000000 – 0.8V, 25mV per step
0000001 – 0.825V
-0010000 – 1.2V
-0011100 – 1.5V.
-1100101 – 3.3V
1111110 – 3.3V
1111111 – Full On
Reversed
LDO4 output voltage regulation (default by OTP)
0000000 – 0.8V, 25mV per step
0000001 – 0.825V
-0010000 – 1.2V
-0011100 – 1.5V.
-1100101 – 3.3V
1111110 – 3.3V
1111111 –Full On
is a registered trademark of Richtek Technology Corporation.
DS5036-P06_RK
January 2015
RT5036
Preliminary
Name
Function
Addr
Reset
LDO VRC Control
Normal
LDO VRC Control
0x4C
Option
Description
Bit
Mode
Name
Reset Value
[7:6]
R/W
LDO1 VRC_N[1:0]
00
VRC Setting
00 – 25mV/10s, 01 – 50mV/10s, 10 – 75mV/10s,
11 – 100mV/10s,
[5:4]
R/W
LDO2 VRC_N[1:0]
00
VRC Setting
00 – 25mV/10s, 01 – 50mV/10s, 10 – 75mV/10s,
11 – 100mV/10s,
[3:2]
R/W
LDO3 VRC_N[1:0]
00
VRC Setting
00 – 25mV/10s, 01 – 50mV/10s, 10 – 75mV/10s,
11 – 100mV/10s,
[1:0]
R/W
LDO4 VRC_N[1:0]
00
VRC Setting
00 – 25mV/10s, 01 – 50mV/10s, 10 – 75mV/10s,
11 – 100mV/10s,
Name
Function
Addr
Reset
LDO VRC Control
Standby
LDO VRC Control
0x7C
Option
Description
Bit
Mode
Name
Reset Value
[7:6]
R/W
LDO1 VRC_S[1:0]
00
VRC Setting
00 – 25mV/10s, 01 – 50mV/10s, 10 – 75mV/10s,
11 – 100mV/10s,
[5:4]
R/W
LDO2 VRC_S[1:0]
00
VRC Setting
00 – 25mV/10s, 01 – 50mV/10s, 10 – 75mV/10s,
11 – 100mV/10s,
[3:2]
R/W
LDO3 VRC_S[1:0]
00
VRC Setting
00 – 25mV/10s, 01 – 50mV/10s, 10 – 75mV/10s,
11 – 100mV/10s,
[1:0]
R/W
LDO4 VRC_S[1:0]
00
VRC Setting
00 – 25mV/10s, 01 – 50mV/10s, 10 – 75mV/10s,
11 – 100mV/10s,
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS5036-P06_RK
January 2015
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
45
RT5036
Preliminary
Name
Function
Addr
Reset
LDO VRC Enable
Normal
LDO VRC Enable
0x4D
0x00
Name
Reset Value
Description
Bit
Mode
7
R/W
LDO1VRC_EN_N
0
6
R/W
LDO2VRC_EN_N
0
5
R/W
LDO3VRC_EN_N
LDO1 VRC
0 – Disable – voltage ramps up to target voltage with
one time
1 – Enable – voltage ramps up to target voltage with
slope control
LDO2 VRC
0 – Disable – voltage ramps up to target voltage with
one time
1 – Enable – voltage ramps up to target voltage with
slope control
0
LDO3 VRC
0 – Disable – voltage ramps up to target voltage with
one time
1 – Enable – voltage ramps up to target voltage with
slope control
LDO4 VRC
0 – Disable – voltage ramps up to target voltage with
one time
1 – Enable – voltage ramps up to target voltage with
slope control
4
R/W
LDO4VRC_EN_N
0
[3:0]
R/W
Reserved
0000
Name
Function
Addr
Reset
LDO VRC Enable
Standby
LDO VRC Enable
0x7D
0x00
Name
Reset Value
Description
Bit
7
6
5
Mode
R/W
R/W
R/W
LDO1VRC_EN_S
LDO2VRC_EN_S
LDO3VRC_EN_S
0
LDO1 VRC
0 – Disable – voltage ramps up to target voltage with
one time
1 – Enable – voltage ramps up to target voltage with
slope control
0
LDO2 VRC
0 – Disable – voltage ramps up to target voltage with
one time
1 – Enable – voltage ramps up to target voltage with
slope control
0
LDO3 VRC
0 – Disable – voltage ramps up to target voltage with
one time
1 – Enable – voltage ramps up to target voltage with
slope control
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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46
Reserved
is a registered trademark of Richtek Technology Corporation.
DS5036-P06_RK
January 2015
RT5036
Preliminary
Bit
Mode
Name
Reset Value
Description
LDO4 VRC
0 – Disable – voltage ramps up to target voltage with one
time
1 – Enable – voltage ramps up to target voltage with
slope control
4
R/W
LDO4VRC_EN_S
0
[3:0]
R/W
Reserved
0000
Function
Addr
Reset
Name
Reserved
Bit
Mode
LDOs/LSW Off
Mode
Name
7
R/W
LDO1oms
1
LDO1 output off mode state
0 – Floating
1 – Ground-discharged
6
R/W
LDO2oms
1
LDO2 output off mode state
0 – Floating
1 – Ground-discharged
5
R/W
LDO3oms
1
LDO3 output off mode state
0 – Floating
1 – Ground-discharged
4
R/W
LDO4oms
1
LDO4 output off mode state
0 – Floating
1 – Ground-discharged
[3:2]
R/W
Reserved
00
Reserved
1
R/W
LSW2oms
1
LSW2 output off mode state
0 – Floating
1 – Ground-discharged
0
R/W
LSW1oms
1
LSW1 output off mode state
0 – Floating
1 – Ground-discharged
Name
Function
Addr
Reset
Bucks/LDOs
On/Off Normal
Bucks/LDOs
On/Off
0x4F
Option
Description
LDOs/LSW Mode
0x4E
0XF3
Reset Value
Description
Bit
Mode
Name
Reset Value
7
R/W
LDO1_EN_N
0
6
R/W
LDO2_EN_N
0
5
R/W
LDO3_EN_N
0
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS5036-P06_RK
January 2015
LDO1 Enable Control Bit.
0 – OFF
1 – ON
LDO2 Enable Control Bit.
0 – OFF
1 – ON
LDO3 Enable Control Bit.
0 – OFF
1 – ON
is a registered trademark of Richtek Technology Corporation.
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47
RT5036
Preliminary
Bit
Mode
Name
Reset Value
4
R/W
LDO4_EN_N
0
3
R/W
Buck1_EN_N
0
2
R/W
Buck2_EN_N
0
1
R/W
Buck3_EN_N
0
0
R/W
Buck4_EN_N
0
Name
Function
Addr
Reset
Bucks/LDOs
On/Off Standby
Bucks/LDOs
On/Off standby
0x7F
Option
Bit
Mode
Name
Reset Value
7
R/W
LDO1_EN_S
0
6
R/W
LDO2_EN_S
0
5
R/W
LDO3_EN_S
0
4
R/W
LDO4_EN_S
0
3
R/W
Buck1_EN_S
0
2
R/W
Buck2_EN_S
0
1
R/W
Buck3_EN_S
0
0
R/W
Buck4_EN_S
0
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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48
Description
LDO4 Enable Control Bit.
0 – OFF
1 – ON
Buck1 Enable Control Bit.
0 – OFF
1 – ON
Buck2 Enable Control Bit.
0 – OFF
1 – ON
Buck3 Enable Control Bit.
0 – OFF
1 – ON
Buck4 Enable Control Bit.
0 – OFF
1 – ON
Description
LDO1 Enable Control Bit.
0 – OFF
1 – ON
LDO2 Enable Control Bit.
0 – OFF
1 – ON
LDO3 Enable Control Bit.
0 – OFF
1 – ON
LDO4 Enable Control Bit.
0 – OFF
1 – ON
Buck1 Enable Control Bit.
0 – OFF
1 – ON
Buck2 Enable Control Bit.
0 – OFF
1 – ON
Buck3 Enable Control Bit.
0 – OFF
1 – ON
Buck4 Enable Control Bit.
0 – OFF
1 – ON
is a registered trademark of Richtek Technology Corporation.
DS5036-P06_RK
January 2015
RT5036
Preliminary
Name
Function
Addr
Reset
LSWs On/Off
LSWs On/Off
0x50
0x00
Name
Reset Value
Description
Wake-up Control
0 –Adapter Plug-in or RTC Count Down to 0 or PWRON
Reboot can’t wake-up from standby mode
1 – Adapter Plug-in or RTC Count Down to 0 or PWRON
Reboot can wake-up from standby mode
Bit
Mode
7
R/W
WK_CTRL
0
[6:4]
R/W
Reserved
000
3
R/W
LSW2_EN_S
0
2
R/W
LSW1_EN_S
0
1
R/W
LSW2_EN_N
0
0
R/W
LSW1_EN_N
0
Function
Addr
Reset
0x51
0xA0
Name
REBOOT/StandBy REBOOT/StandBy
Ctrl
Ctrl
Bit
Mode
Name
R/W
Delay2[1:0]
10
[5:4]
R/W
Delay1[1:0]
10
[3:2]
R/W
RESET Action
10
[1:0]
R/W
Reserved
00
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
January 2015
LSW2 Enable Control Bit.
0 – OFF
1 – ON
LSW1 Enable Control Bit.
0 – OFF
1 – ON
LSW2 Enable Control Bit.
0 – OFF
1 – ON
LSW1 Enable Control Bit.
0 – OFF
1 – ON
Reset Value
[7:6]
DS5036-P06_RK
Reserved
Standby
Standby
Normal
Normal
Description
Delay2 setting00 : 100ms
01 : 500ms
10 : 1s
11 : 2s
Delay1 setting
00 : 100ms
01 : 500ms
10 : 1s
11 : 2s
00 : Reset BUCK1 to BUCK4 and LDO1 to LDO4 output
level to default
01 : delay1 power-off PMIC
10 : delay1 power-off then delay2 power-on PMIC
11 : reserved
Reserved
is a registered trademark of Richtek Technology Corporation.
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49
RT5036
Preliminary
Name
Function
Addr
Reset
PWRON/RESETB
Time Setting
PWRON/RESETB
Time Setting
0x52
0X16
Description
Bit
Mode
Name
Reset Value
[7:6]
R/W
Reserved
00
Reserved
Long-press time setting (after Power-On)
00 : 1s
01 : 1.5s
10 : 2s
11 : 2.5s
Sending short/long-press IRQ to CPU Ex : 1.5s
= low time < 1.5s (short IRQ)
= low time > 1.5s but < 6s (shutdown time) (long
IRQ)
= low time > 6s (shutdown time) (shutdown)
Key-press forced shutdown time setting
00 : 4s (pressing time-low level)
01 : 6s
10 : 8s
11 : 10s
RESETB signal delay after the last power startup is
done
00 : 100ms
01 : 200ms
10 : 400ms
11 : 800ms
[5:4]
R/W
L_PRESS_TIME[1:0]
01
[3:2]
R/W
SHDN_PRESS
01
[1:0]
R/W
RESETB_DLY
Option
Name
Function
Addr
Reset
SHDN/standby
Control
Shutdown/standby
Control
0x53
0X48
Name
Reset Value
Description
0
Power Off is set by CPU. 100ms delay to power off
after setting.
0 : Normal operation
1 : Disable the PMIC output
1
Disable Buck/LDO only for normal power off
(SHDN_CTRL = 1)
0 : disable at the same time
1 : contrary to the startup timing (first_on-last_off)
00
Shutdown delay time after send the PWRON
key-press-forced-shutdown IRQ (when IRQ is
disable, there is no delay)
00: 0ms (default)
01 : 100ms
10 : 500ms
11 : 1s
Bit
7
6
[5:4]
Mode
R/W
R/W
R/W
SHDN_CTRL
SHDN_TIMING
SHDN_DLYTIME
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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50
is a registered trademark of Richtek Technology Corporation.
DS5036-P06_RK
January 2015
RT5036
Preliminary
Bit
Mode
Name
Reset Value
3
R/W
STANDBY_OFF
1
[2:1]
R/W
StandBy_EN [1:0]
00
0
R/W
STB_Trigger
0
Description
Standby off control
(0 : off at the same time, 1 : off sequentially)
Standby En/Disable and each power re-startup
interval time
00 : standby mode disable
01 : enable and 1ms
10 : enable and 2ms
11 : enable and 4ms
0 : normal operation
1 : Standby Mode control. From low to high will
trigger standby mode and from high to low will
leave standby mode.
Name
Function
Addr
Reset
SHDN Off Enable
Setting1
SHDN Off Enable
Setting1
0x54
0X00
Description
Bit
Mode
Name
Reset Value
7
R/W
BCK1LV_ENSHDN
0
6
R/W
BCK2LV_ENSHDN
0
5
R/W
BCK3LV_ENSHDN
0
4
R/W
BCK4LV_ENSHDN
0
3
R/W
LDO1LV_ENSHDN
0
2
R/W
LDO2LV_ENSHDN
0
1
R/W
LDO3LV_ENSHDN
0
0
R/W
LDO4LV_ENSHDN
0
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS5036-P06_RK
January 2015
Buck1 output voltage low SHDN
0 : disable this event.
1 : enable this event.
Buck2 output voltage low SHDN
0 : disable this event.
1 : enable this event.
Buck3 output voltage low SHDN
0 : disable this event.
1 : enable this event.
Buck3 output voltage low SHDN
0 : disable this event.
1 : enable this event.
LDO1 output voltage low SHDN
0 : disable this event.
1 : enable this event.
LDO2 output voltage low SHDN
0 : disable this event.
1 : enable this event.
LDO3 output voltage low SHDN
0 : disable this event.
1 : enable this event.
LDO4 output voltage low SHDN
0 : disable this event.
1 : enable this event.
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
51
RT5036
Preliminary
Name
Function
Addr
Reset
SHDN Off
Enable Setting2
SHDN Off
Enable Setting2
0x55
0X06
Bit
Mode
Name
Reset Value
7
R/W
LSW2LV_ENSHDN
0
6
R/W
LSW1LV_ENSHDN
0
5
R/W
VSYSLV_ENSHDN
0
[4:3]
R/W
Reserved
00
2
R/W
PWRON_ENSHDN
1
1
R/W
OT_ENSHDN
1
0
R/W
VDDALV_ENSHDN
0
Name
Function
Addr
Reset
OFF/ON Event
OFF/ON Event
0x56
0XF0
Bit
Mode
Name
Reset Value
[7:4]
R
OFF_Event
1111
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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52
Description
LSW2 output voltage low SHDN
0 : disable this event.
1 : enable this event.
LSW1 output voltage low SHDN
0 : disable this event.
1 : enable this event.
VSYS low SHDN
0 : disable this event.
1 : enable this event.
Reserved
PWRON key-pressed forced SHDN
0 : disable this event.
1 : enable this event.
Over temperature SHDN
0 : disable this event.
1 : enable this event.
VDDA voltage low SHDN
0 : disable this event.
1 : enable this event.
Description
Powered off because of (Only shows last
power-off event)
0000 : VDDA voltage low (VOFF) (Set by
reg)
0001 : Buck1 output voltage low
0010 : Buck2 output voltage low
0011 : Buck3 output voltage low
0100 : Buck4 output voltage low
0101 : PWRON key-pressed forced
shutdown
0110 : Power Off register setting
0111 : Over temperature event
1000 : from RESETB pin event or PMIC
booting unsuccessfully
1001: LDO1 output voltage low
1010: LDO2 output voltage low
1011: LDO3 output voltage low
1100: LDO4 output voltage low
1101: LSW2 output voltage low
1110: LSW1 output voltage low
1111 : SYSLV
is a registered trademark of Richtek Technology Corporation.
DS5036-P06_RK
January 2015
RT5036
Preliminary
Bit
Mode
Name
Reset Value
3
R
Reserved
0
Reserved
2
R
Standby Status
0
Show Standby Status :
0 : PMIC is not in standby mode
1: PMIC is in standby mode
ON_Event
00
Powered on because of (Only shows last power-on
event)
00 : VIN Plug-in
01 : PWRON key
10 : RESET Delay1 OFF then Delay2 Power-on
11 : Reserved
Name
Function
Addr
Reset
Bucks/LDOs_IRQ
Bucks/LDOs_IRQ
0x57
0X00
[1:0]
R
Description
Bit
Mode
Name
Reset Value
Description
7
R
BCK1LV_IRQ
0
Buck1 output voltage is lower than 66%, IRQ indicator.
6
R
BCK2LV_IRQ
0
Buck2 output voltage is lower than 66%, IRQ indicator.
5
R
BCK3LV_IRQ
0
Buck3 output voltage is lower than 66%, IRQ indicator.
4
R
BCK4LV_IRQ
0
Buck4 output voltage is lower than 66%, IRQ indicator.
3
R
LDO1LV_IRQ
0
LDO1 output voltage is lower than 50%, IRQ indicator.
2
R
LDO2LV_IRQ
0
LDO2 output voltage is lower than 50%, IRQ indicator.
1
R
LDO3LV_IRQ
0
LDO3 output voltage is lower than 50%, IRQ indicator.
0
R
LDO4LV_IRQ
0
LDO4 output voltage is lower than 50%, IRQ indicator.
Name
Function
Addr
Reset
LSWs/BASE_IRQ
LSWs/BASE_IRQ
0x58
0X00
Bit
Mode
Name
Reset Value
Description
7
R
LSW2LV_IRQ
0
LSW2 output voltage is lower than 66%, IRQ indicator.
6
R
LSW1LV_IRQ
0
LSW1 output voltage is lower than 66%, IRQ indicator.
5
R
PMICSYSLV_IRQ
0
PMIC VSYS voltage is lower than SYSLV setting, IRQ
indicator.
[4:2]
R
Reversed
000
1
R
OT_IRQ
0
0
R
VDDALV_IRQ
0
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS5036-P06_RK
January 2015
Reversed
Charger thermal shutdown fault. Set when the die
temperature exceeds thermal shutdown threshold or
PMIC Internal over-temperature was triggered, IRQ
indicator.
VDDA voltage is lower VDDAUVLO, IRQ indicator.
is a registered trademark of Richtek Technology Corporation.
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53
RT5036
Preliminary
Name
Function
Addr
Reset
POWER_KEY_IRQ
POWER_KEY_IRQ
0x59
0X00
Bit
Mode
Name
Reset Value
Description
7
R
KPSHDN_IRQ
0
PWRON Key-press forced shutdown, IRQ indicator.
6
R
PWRONR_IRQ
0
PWRON Key-press rising edge, IRQ indicator.
5
R
PWRONF_IRQ
0
PWRON Key-press falling edge, IRQ indicator.
4
R
PWRONSP_IRQ
0
PWRON key short press, IRQ enable (32μs deglitch
time)
3
R
PWRONLP_IRQ
0
PWRON key long press, IRQ enable (32μs deglitch
time)
[2:0]
R
Reversed
000
Name
Function
Addr
Reset
Bucks/LDOs
_IRQ_Mask
Bucks/LDOs
_IRQ_Mask
0x5A
0XFF
Description
Reversed
Bit
Mode
Name
Reset Value
7
R/W
BCK1LVM
1
Buck1 low voltage protection interrupt mask.
0 – Interrupt is not masked.
1 – Interrupt is masked.
6
R/W
BCK2LVM
1
Buck2 low voltage protection interrupt mask.
0 – Interrupt is not masked.
1 – Interrupt is masked.
5
R/W
BCK3LVM
1
Buck3 low voltage protection interrupt mask.
0 – Interrupt is not masked.
1 – Interrupt is masked.
4
R/W
BCK4LVM
1
Buck4 low voltage protection interrupt mask.
0 – Interrupt is not masked.
1 – Interrupt is masked.
3
R/W
LDO1LVM
1
LDO1 low voltage protection interrupt mask.
0 – Interrupt is not masked.
1 – Interrupt is masked.
2
R/W
LDO2LVM
1
LDO2 low voltage protection interrupt mask.
0 – Interrupt is not masked.
1 – Interrupt is masked.
1
R/W
LDO3LVM
1
LDO3 low voltage protection interrupt mask.
0 – Interrupt is not masked.
1 – Interrupt is masked.
0
R/W
LDO4LVM
1
LDO4 low voltage protection interrupt mask.
0 – Interrupt is not masked.
1 – Interrupt is masked.
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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54
is a registered trademark of Richtek Technology Corporation.
DS5036-P06_RK
January 2015
RT5036
Preliminary
Name
Function
Addr
Reset
LSW s/BASE
_IRQ_Mask
Bucks/LDOs
_IRQ_Mask
0x5B
0XE0
Description
Bit
Mode
Name
Reset Value
7
R/W
LSW2LVM
1
LSW2 low voltage protection interrupt mask.
0 – Interrupt is not masked.
1 – Interrupt is masked.
6
R/W
LSW1LVM
1
LSW1 low voltage protection interrupt mask.
0 – Interrupt is not masked.
1 – Interrupt is masked.
5
R/W
PMICSYSLVM
1
PMIC VSYS low voltage protection interrupt mask.
0 – Interrupt is not masked.
1 – Interrupt is masked.
[4:2]
R/W
Reversed
000
1
R/W
OTM
0
Over Temperature protection interrupt mask.
0 – Interrupt is not masked.
1 – Interrupt is masked.
0
R/W
VDDALVM
0
VDDA low voltage protection interrupt mask.
0 – Interrupt is not masked.
1 – Interrupt is masked.
Name
Function
Addr
Reset
POWER_KEY
_IRQ_Mask
POWER_KEY
_IRQ_Mask
0x5C
0X78
Reversed
Bit
Mode
Name
Reset Value
Description
7
R/W
KPSHDN
_IRQM
0
PWRON Key-press forced shutdown interrupt mask.
0 – Interrupt is not masked.
1 – Interrupt is masked.
6
R/W
PWRONR
_IRQM
1
PWRON Key-press rising edge, IRQ interrupt mask.
0 – Interrupt is not masked.
1 – Interrupt is masked.
5
R/W
PWRONF
_IRQM
1
PWRON Key-press falling edge, IRQ interrupt mask.
0 – Interrupt is not masked.
1 – Interrupt is masked.
4
R/W
PWRONSP
_IRQM
1
PWRON key short press, IRQ interrupt mask.
0 – Interrupt is not masked.
1 – Interrupt is masked.
3
R/W
PWRONLP
_IRQM
1
PWRON key long press, IRQ interrupt mask.
0 – Interrupt is not masked.
1 – Interrupt is masked.
[2:0]
R/W
Reversed
000
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS5036-P06_RK
January 2015
Reversed
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
55
RT5036
Name
Preliminary
Function
Buck Syn-Clock
Buck Syn-Clock
Syn-Clock Frequency Syn-Clock Frequency
Control
Control
Addr
Reset
0x65
0x40
Bit
Mode
Name
Reset Value
[7:5]
R/W
VSYSUVLO[2:0]
010
[4:1]
R/W
Reversed
0000
0
R/W
1.5/3.0MHz
0
Function
Addr
Reset
0x80
0x64
Description
Name
LSW2 control Normal LSW2 Output Control
Bit
Mode
Name
Reset Value
7
R/W
Reversed
0
[6:0]
R/W
LSW2 Output_N[6:0]
1100100
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56
Description
VSYS UVLO 2.8~3.5V per 0.1V (Falling threshold
with hysteresis of 300mV)
000 – 2.8V
001 – 2.9V
010 – 3.0V (default)
011 – 3.1V
100 – 3.2V
101 – 3.3V
110 – 3.4V
110 – 3.5V
Reversed
Select Buck Syn-Clock Syn-Clock Frequency
0:1.5MHz
1:30MHz
Reversed
LSW2 output voltage regulation (default by OTP)
0000000 – 0.8V, 25mV per step
0000001 – 0.825V
-0010000 – 1.2V
-0011100 – 1.5V.
-1100101 – 3.3V
1111110 – 3.3V
1111111 – Full On
is a registered trademark of Richtek Technology Corporation.
DS5036-P06_RK
January 2015
RT5036
Preliminary
Name
Function
Addr
Reset
LSW2 control Standby
LSW2 Output
Control
0x82
0x58
Description
Bit
Mode
Name
Reset Value
7
R/W
Reversed
0
[6:0]
R/W
LSW2 Output_S [6:0]
1011000
Function
Addr
Reset
Name
Bit
Mode
LSW1 Output
Control
Name
7
R/W
Reversed
LSW1 control Normal
[6:0]
R/W
0x81
0x64
Reset Value
Description
0
Function
Addr
Reset
0x83
0x7F
Description
Bit
Mode
Name
Reset Value
7
R/W
Reversed
0
LSW1 Output_S [6:0]
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS5036-P06_RK
LSW1 output voltage regulation (default by OTP)
0000000 – 0.8V, 25mV per step
0000001 – 0.825V
-0010000 – 1.2V
-0011100 – 1.5V.
-1100101 – 3.3V
1111110 – 3.3V
1111111 – Full On
1100100
LSW1 control Standby LSW1 Output Control
R/W
Reversed
LSW1 Output_N[6:0]
Name
[6:0]
Reversed
LSW2 output voltage regulation (default by OTP)
0000000 – 0.8V, 25mV per step
0000001 – 0.825V
-0010000 – 1.2V
-0011100 – 1.5V.
-1100101 – 3.3V
1111110 – 3.3V
1111111 – Full On
January 2015
1111111
Reversed
LSW1 output voltage regulation (default by OTP)
0000000 – 0.8V, 25mV per step
0000001 – 0.825V
-0010000 – 1.2V
-0011100 – 1.5V.
-1100101 – 3.3V
1111110 – 3.3V
1111111 – Full On
is a registered trademark of Richtek Technology Corporation.
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57
RT5036
Preliminary
Name
Function
Addr
Reset
LSW VRC Control
LSW VRC Control
0x84
Option
Description
Bit
Mode
Name
Reset Value
[7:6]
R/W
LSW2 VRC_N[1:0]
00
VRC Setting
00 – 25mV/10s, 01 – 50mV/10s, 10 – 75mV/10s,
11 – 100mV/10s,
[5:4]
R/W
LSW1 VRC_N[1:0]
00
VRC Setting
00 – 25mV/10s, 01 – 50mV/10s, 10 – 75mV/10s,
11 – 100mV/10s,
[3:2]
R/W
LSW2 VRC_S[1:0]
00
VRC Setting
00 – 25mV/10s, 01 – 50mV/10s, 10 – 75mV/10s,
11 – 100mV/10s,
[1:0]
R/W
LSW1 VRC_S[1:0]
00
VRC Setting
00 – 25mV/10s, 01 – 50mV/10s, 10 – 75mV/10s,
11 – 100mV/10s,
Name
Function
Addr
Reset
LSW VRC Enable
LSW VRC Enable
0x85
0x00
Name
Reset Value
Description
Bit
7
Mode
R/W
LSW2VRC_EN_N
0
LSW2 VRC in Normal Mode
0 – disable – voltage ramps up to target voltage with
one time
1 – enable – voltage ramps up to target voltage with
slope control
6
R/W
LSW1VRC_EN_N
0
LSW1 VRC in Normal Mode
0 – disable – voltage ramps up to target voltage with
one time
1 – enable – voltage ramps up to target voltage with
slope control
[5:4]
R/W
Reserved
00
Reserved
0
LSW2 VRC in Standby Mode
0 – disable – voltage ramps up to target voltage with
one time
1 – enable – voltage ramps up to target voltage with
slope control
3
R/W
LSW2VRC_EN_S
2
R/W
LSW1VRC_EN_S
0
LSW1 VRC in Standby Mode
0 – disable – voltage ramps up to target voltage with
one time
1 – enable – voltage ramps up to target voltage with
slope control
[1:0]
R/W
Reserved
00
Reserved
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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58
is a registered trademark of Richtek Technology Corporation.
DS5036-P06_RK
January 2015
RT5036
Preliminary
Name
Function
Addr
Reset
RTCADJ
RTC Frequency
Adjust
0x90
0XBC
Description
Bit
Mode
Name
Reset Value
7
R/W
RTC_EN
1
[6:0]
R/W
RTCADJ[6:0]
0111100
Name
Function
Addr
Reset
RTCT_SEC
RTC Timing_SEC
0x91
0X00
Enable RTC
0 – RTC disabled
1 – RTC enabled
finely tune the RTC time counting
Frequency by adjusting (RTCAJ - ? 60)/2 ppm.
Hence, the tuning range is - 30ppm to 33ppm.
Bit
Mode
Name
Reset Value
Description
7
R
BUSY
0
1 : RTC is busy, and the writing access is not allowed
6
R
Reversed
0
[5:0]
R/W
RTCT_SEC[5:0]
00000
Reversed
Stores the SECOND field of RTC time. That is 0 to
59.
Name
Function
Addr
Reset
RTCT_MINUTE
RTC
Timing_MINUTE
0x92
0X00
Description
Bit
Mode
Name
Reset Value
[7:6]
R/W
Reversed
00
[5:0]
R/W
RTCT_MIN[5:0]
00000
Stores the MINUTE field of RTC time. That is 0 to 59.
Name
Function
Addr
Reset
RTCT_HOUR
RTC Timing_HOUR
0x93
0X00
Bit
Mode
Name
Reset Value
7
R/W
12/24hours
0
6
R/W
AM/PM
0
5
R/W
Reversed
0
[4:0]
R/W
RTCT_HOUR[4:0]
00000
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS5036-P06_RK
January 2015
Reversed
Description
12hours/24hours selection.
0 – 24hours.
1 – 12 hours.
AM/PM selection.
0 – AM
1 –PM
If the 24hours is selected, user can't set this bit.
Stores the HOUR field of RTC time. That is 0 to 23
(24hour format).
is a registered trademark of Richtek Technology Corporation.
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59
RT5036
Preliminary
Name
Function
Addr
Reset
RTCT_YEAR
RTC YEAR
0x94
0X0D
Description
Bit
Mode
Name
Reset Value
[7:6]
R/W
Reversed
00
[5:0]
R/W
RTCT_ YEAR [5:0]
0001101
Name
Function
Addr
Reset
RTCT_MONTH
RTCT_MONTH
0x95
0X01
Description
Reversed
Stores the YEAR field of RTC time. That is 0 to 63.
RTCT_ YEAR [5:0] = 0 means 2000.
Bit
Mode
Name
Reset Value
[7:4]
R/W
Reversed
0000
Reversed
[3:0]
R/W
RTCT_MON[3:0]
0001
Stores the MONTH field of RTC time. That is 1 to 12.
RTCT_MON = 1 means January.
Name
Function
Addr
Reset
RTC DATE/WEEK
RTC DATE/WEEK
0x96
0X41
Name
Reset Value
Description
Stores the DAY-of-WEEK field of RTC time. That is 0
to 6.
RTCT_WEK = 0 means Sunday.
RTCT_WEK = 1 means Monday.
RT5036 cannot calculate automatically the field
based on other fields. (YEAR, MONTH,DATE).
Bit
Mode
[7:5]
R/W
RTCT_WEEK[2:0]
010
[4:0]
R/W
RTCT_DAY[4:0]
00001
Name
Function
Addr
Reset
STB Mode_Setting
Standby(STB) Mode
Setting
0x97
0X00
Description
Stores the DATE field of RTC time. That is 1 to 31.
Bit
Mode
Name
Reset Value
[7:1]
R/W
Reversed
0000000
0
R/W
STB_CTRL
0
Function
Addr
Reset
0x98
0X00
Description
Name
STB_Alarm_SEC
STB_Alarm_SEC
Bit
Mode
Name
Reset Value
[7:6]
R/W
Reversed
00
[5:0]
R/W
STB_Alarm_
SEC[5:0]
00000
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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60
Reversed
STB_CTRL = 0 means count down (CD) mode.
STB_CTRL = 1 means clock alarm (Alarm) mode.
Reversed
Stores the SECOND field of standby alarm time. That
is 0 to 59.
is a registered trademark of Richtek Technology Corporation.
DS5036-P06_RK
January 2015
RT5036
Preliminary
Name
Function
Addr
Reset
STB_Alarm
_MINUTE
STB_Alarm_MINUTE
0x99
0X00
Description
Bit
Mode
Name
Reset Value
[7:6]
R/W
Reversed
00
[5:0]
R/W
Reversed
Stores the MINUTE field of standby alarm
time. That is 0 to 59.
STB_Alarm_MIN[5:0]
00000
Name
Function
Addr
Reset
STB_Alarm_HOUR
STB_Alarm_HOUR
0x9A
0X00
Bit
Mode
Name
Reset Value
Description
12hours/24hours selection.
0 – 24hours.
1 – 12 hours.
AM/PM selection.
0 – AM
1 –PM
If the 24hours is selected, user can't set this
bit.
7
R/W
STB_Alarm_12/24hours
0
6
R/W
STB_Alarm_AM/PM
0
5
R/W
Reversed
0
[4:0]
R/W
STB_Alarm_HOUR[4:0]
0000
Stores the HOUR field of standby alarm time.
That is 0 to 23 (24hour format).
Name
Function
Addr
Reset
STB_Alarm_YEAR
STB_Alarm_ YEAR
0x9B
0X0D
Reversed.
Bit
Mode
Name
Reset Value
Description
[7:6]
R/W
Reversed
00
[5:0]
R/W
STB_Alarm_YEAR[5:0]
001101
Reversed
Stores the YEAR field of standby alarm time.
That is 0 to 63. STB_Alarm_YEAR = 0
means the year 2000.
Hence, RT5036 can setting maximum year is
2063.
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS5036-P06_RK
January 2015
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
61
RT5036
Preliminary
Name
Function
Addr
Reset
STB_Alarm_MONTH
STB_Alarm_MONTH
0x9C
0X01
Description
Bit
Mode
Name
Reset Value
[7:4]
R/W
Reversed
0000
Reversed
[3:0]
R/W
STB_Alarm_MON[3:0]
0001
Stores the MONTH field of standby alarm time.
That is 1 to 12. STB_Alarm_MON = 1 means
January.
Name
Function
Addr
Reset
STB_Alarm_DAY
STB_Alarm_ DAY
0x9D
0X01
Description
Bit
Mode
Name
Reset Value
[7:5]
R
Reversed
00
Reversed
STB_Alarm_DAY[4:0]
0001
Stores the DATE field of standby alarm time.
That is 1 to 31, depending on the month.
STB_Alarm_DAY [4:0] = 1 means 1st day of each
month. RT5036 supports leap year counting.
Name
Function
Addr
Reset
STB_CD_SEC
STB_CD_SEC
0x9E
0X00
Description
[4:0]
R/W
Bit
Mode
Name
Reset Value
[7:6]
R/W
Reversed
00
[5:0]
R/W
STB_CD_SEC[5:0]
00000
Name
Function
Addr
Reset
STB_CD_MINUTE
STB_CD_MINUTE
0x9F
0X00
Description
Bit
Mode
Name
Reset Value
[7:6]
R/W
Reversed
00
[5:0]
R/W
STB_CD_MIN[5:0]
00000
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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62
Reversed
Stores the SECOND field of standby count down
time. That is 0 to 59.
Reversed
Stores the MINUTE field of standby count down
time. That is 0 to 59.
is a registered trademark of Richtek Technology Corporation.
DS5036-P06_RK
January 2015
RT5036
Preliminary
Name
Function
Addr
Reset
STB_CD_HOUR
STB_CD_HOUR
0xA0
0X00
Bit
Mode
Name
Reset Value
Description
12hours/24hours selection.
0 – 24hours.
1 – 12 hours.
AM/PM selection.
0 – AM
1 –PM
If the 24hours is selected, user can't set this bit.
7
R/W
STB_CD_12/24hours
0
6
R/W
STB_CD_AM/PM
0
5
R/W
Reversed
0
[4:0]
R/W
STB_CD_HOUR[4:0]
0000
Stores the HOUR field of standby count down time.
That is 0 to 23 (24hour format).
Name
Function
Addr
Reset
STB_CD_DATE_L
STB_CD_DATE_L
0xA1
0X00
Description
Reversed
Bit
Mode
Name
Reset Value
[7:0]
R/W
STB_CD_DAY[7:0]
00000000
Name
Function
Addr
Reset
STB_CD_DAY_H
STB_CD_DAY_H
0xA2
0X00
Description
The low byte of day down counter
Bit
Mode
Name
Reset Value
[7:4]
R/W
Reversed
0000
Reversed
[3:0]
R/W
STB_CD_ DAY [11:8]
0000
The high byte of day down counter
Name
Function
Addr
Reset
STB_WKUP_IRQ
Standby
WakeUp_IRQ
0xA4
0X00
Description
Bit
Mode
Name
Reset Value
[7:2]
R
Reversed
000000
1
R
CD_IRQ
0
Standby mode wakes up by count down (CD) IRQ
indicator.
0
R
CA_IRQ
0
Standby mode wakes up by clock alarm (CA) IRQ
indicator.
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS5036-P06_RK
January 2015
Reversed
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
63
RT5036
Preliminary
Name
Function
Addr
Reset
STB_WKUP_Mask
Standby WakeUp
_IRQ _Mask
0xA5
0X03
Description
Bit
Mode
Name
Reset Value
[7:2]
R/W
Reversed
000000
1
R/W
CDM
1
Standby mode wakes up by count down interrupt mask.
0 – interrupt is not masked.
1 – Interrupt is masked.
0
R/W
CAM
1
Standby mode wakes up by clock alarm interrupt mask.
0 – interrupt is not masked.
1 – Interrupt is masked.
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
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64
Reversed
is a registered trademark of Richtek Technology Corporation.
DS5036-P06_RK
January 2015
Preliminary
RT5036
Thermal Considerations
Layout Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
Some PCB layout guidelines for optimal performance of
RT5036 list as following. Following figure shows the real
PCB layout considerations and it is based on the real
component size whose unit is millimeter (mm).
PD(MAX) = (TJ(MAX) − TA) / θJA
Keep the main power traces as wide and short as
possible.
The output inductor and bootstrap capacitor should be
placed close to the chip and LXCHG pins.
The battery voltage sensing point should be placed after
the output capacitor, and kept wide for maximum precharge current.
To optimize current sense accuracy, connect the traces
to RSENSE with Kelvin sense connection.
Put the input capacitor as close as possible to the device
pins.
LXB1 to LXB4 node is with high frequency voltage swing
and should be kept small area. Keep analog components
away from LXB1 to LXB4 node to prevent stray capacitive
noise pick-up.
Connect VOUTSB1 to VOUTSB4 pin network behind
the output capacitors.
Connect all analog grounds to a common node and then
connect the common node to the power ground behind
the output capacitors.
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
WQFN-40L 5x5 package, the thermal resistance, θJA, is
27.5°C/W on a standard JEDEC 51-7 four-layer thermal
test board. The maximum power dissipation at TA = 25°C
can be calculated by the following formula :
PD(MAX) = (125°C − 25°C) / (27.5°C/W) = 3.63W for
WQFN-40L 5x5 package
The maximum power dissipation depends on the operating
ambient temperature for fixed T J(MAX) and thermal
resistance, θJA. The derating curve in Figure 3 allows the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
Maximum Power Dissipation (W)1
4.0
Four-Layer PCB
3.5
Place the input and output capacitors as close to the
input and output pins as possible.
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 3. Derating Curve of Maximum Power Dissipation
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
DS5036-P06_RK
January 2015
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
65
RT5036
Preliminary
C0805
VOUT1
DCDC1
Inductor 4*4mm
C0402
BOOT
RESET#
VOUTSB1
PWRON
CLKOUT
XTALIN
STB_EN
VINCHG
XTALOUT
C0805
VMIDCHG
SDA
IRQ
SCL
C0805
VINB1
VINCHG
C1206
VINCHG
DCDC2
Inductor 4*4mm
DCDC2
VINB1
VMIDCHG
LXB1
LXCHG
LXB2
C0805
VINB2
C0805
VOUT2
C0805
VINB4
C0805
VOUT4
VINB2
VBOOTCHG
VINB4
VDDA
VBATS
LXB4
ISENSN
LXB3
ISENSP
VINB3
PPCTRL
VOUTSB2
VOUTSB4
DCDC4
Inductor 4*4mm
DCDC4
C0402
VOUTLSW1
C0402
VINLSW
C0402
VOUTLSW2
C0402
VOL4
C0402
VOL3
C0402
VINL234
C0402
VOL2
VSYS
C1206
C0402
VOL1
C0402
VINL1
Rsense
R1632
C0805
VINB3
C0402
ISENSP
VOUTSB3
VINLSW
VOUTLSW1
VOL4
VOL3
VOL2
VOL1
VINL1
VINL234
TS
VOUTLSW2
Charger
Inductor 4*4mm
DCDC1
DCDC3
Inductor 4*4mm
DCDC3
SOT-23
C0805
VOUT3
TOP
2nd Layer
GND
3rd Layer
GND & I/O
C0805
VBAT
VBAT
Bottom
Figure 4. PCB Layout Guide
Copyright ©2015 Richtek Technology Corporation. All rights reserved.
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66
is a registered trademark of Richtek Technology Corporation.
DS5036-P06_RK
January 2015
RT5036
Preliminary
Outline Dimension
D
SEE DETAIL A
D2
L
1
E2
E
e
b
1
1
2
2
DETAIL A
Pin #1 ID and Tie Bar Mark Options
A
A3
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
A1
Symbol
Dimensions In Millimeters
Dimensions In Inches
Min
Max
Min
Max
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.150
0.250
0.006
0.010
D
4.950
5.050
0.195
0.199
D2
3.250
3.500
0.128
0.138
E
4.950
5.050
0.195
0.199
E2
3.250
3.500
0.128
0.138
e
L
0.400
0.350
0.016
0.450
0.014
0.018
W-Type 40L QFN 5x5 Package
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
DS5036-P06_RK
January 2015
www.richtek.com
67
RT5036
Preliminary
Datasheet Revision History
Version
P00
P01
Date
Item
2014/1/21
2014/3/6
Description
First Edition
Functional Pin Description
Typical Application Circuit
Application Information
Modify
2
I C Registers Table
P02
2014/3/25
I2C Registers Table
Modify
General Description
Features
P03
2014/6/9
Power Channel Flow Chart
Electrical Characteristics
Modify
Typical Application Circuit
I2C Registers Table
Features
P04
2014/7/31
Electrical Characteristics
Modify
Application Information
P05
2014/8/14
I2C Registers Table
Modify
P06
2015/1/6
Typical Operating Characteristics
Copyright © 2015 Richtek Technology Corporation. All rights reserved.
www.richtek.com
68
Add Typical Operating Characteristics
(from RT5037_RK-P01)
is a registered trademark of Richtek Technology Corporation.
DS5036-P06_RK
January 2015
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