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RT5047GSP

RT5047GSP

  • 厂商:

    RICHTEK(台湾立绮)

  • 封装:

    SOIC8_150MIL_EP

  • 描述:

    IC REG BOOST ADJ 0.55A 8SOP

  • 数据手册
  • 价格&库存
RT5047GSP 数据手册
RT5047 Single Output LNB Supply and Control Voltage Regulator Features General Description The RT5047 is a highly integrated voltage regulator and interface IC, specifically design for supplying power and control signals from advanced satellite set-top box (STB) modules to the LNB down-converter in the antenna dish or to the multi-switch box. The device is consists of the independent current-mode boost controller and low dropout linear regulator along with the circuitry required for 22KHz tone shaping to support DiSEqCTM1.x communications.  Wide Input Supply Voltage Range : 8V to 16V Output Current Limit of 550mA with 45ms timer Low Noise LNB Output Voltage (13.3V and 18.3V by SEL Pin) 3% High Accuracy for 0mA to 500mA Current Output Push-Pull Output Stage minimizes 13.3V to 18.3V and 18.3V to 13.3V Output Transition Time External 22kHz Tone Input Meet DiSEqCTM 1.x Protocol Output Short Circuit Protection  Over-temperature Protection        The RT5047 has fault protection (over-current, over-temperature and under-voltage lockout). The RT5047 are available in a SOP-8 (Exposed Pad) package to achieve optimized solution for thermal dissipation. Ordering Information Applications   RT5047 Package Type SP : SOP-8 (Exposed Pad-Option 2) LNB Power Supply and Control for Satellite Set-Top Box Analog and Digital Satellite Receivers/ Satellite TV, Satellite PC cards Pin Configurations (TOP VIEW) Lead Plating System G : Green (Halogen Free and Pb Free) Note : 2 LX 3 VIN 4 Richtek products are :  GND TONE 7 NC 6 SEL 5 EN 9 RoHS compliant and compatible with the current SOP-8 (Exposed Pad) requirements of IPC/JEDEC J-STD-020.  8 LNB BOOST Suitable for use in SnPb or Pb-free soldering processes. Simplified Application Circuit D1 L1 VIN CBST CIN1 LX BOOST VIN CIN2 D3 Max. 550mA LNB EN RT5047 VLNB D2 CLNB D4 TONE SEL GND Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5047-00 March 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 1 RT5047 Marking Informaton RT5047 GSPYMDNN RT5047GSP : Product Number YMDNN : Date Code Functional Pin Description Pin No. Pin Name Pin Function 1 LNB Output Voltage for LNB. 2 BOOST Boost Output and Tracking Supply Voltage to LNB. 3 LX Switching Node of DC/DC Boost Converter. 4 VIN Power Supply Input. 5 EN LNB Output Enable. 6 SEL LNB Output Voltage Selection Pin (Low is for 13.3V, high is for 18.3V). 7 NC No Internal Connection. Pull to GND by 4.7k resistor. 8 TONE 9 (Exposed Pad) GND 22kHz TONE Input. Ground. The Exposed Pad must be soldered to a large PCB and connected to GND for maximum power dissipation. Function Block Diagram LX VIN BOOST OCP1 UVLO VR1 VFB1 RF1 EN Oscillator Error Amp PWM Controller RF2 2-steps Voltage Setting OSC VD2 VFB2 Dynamic Dropout Control Linear Regulator LNB VUD OCP2 DAC SEL Bandgap Reference VD1 TONE 22kHz Tone Shape VFB2 OTP VR1 Reference Voltage GND Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 2 is a registered trademark of Richtek Technology Corporation. DS5047-00 March 2015 RT5047 Operation The RT5047 integrates a current mode boost converter and linear regulator. Use the SEL pin to control the LNB voltage and the boost converter track is at least greater 850mV than LNB voltage. The boost converter is the high efficiency PWM architecture with 700kHz operation frequency. The linear regulator has the capability to source current up to 550mA during continuous operation. All the loop compensation, current sensing, and slope compensation functions are provided internally. OCP Both the boost converter and the linear regulator have independent current limit. In the boost converter (OCP1), this is achieved through cycle-by-cycle internal current limit (typ. 3A). In the linear regulator (OCP2), when the linear regulator exceeds OCP more than 48ms, the LNB output will be disabled and re-start after 1.8s. Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5047-00 March 2015 Tone Circuit This circuit is used for tone generation. Use the TONE pin to control output amplitude of LNB. OTP When the junction temperature reaches the critical temperature (typically 150C), the boost converter and the linear regulator are immediately disabled. UVLO The UVLO circuit compares the VIN with the UVLO threshold (7.7V rising typically) to ensure that the input voltage is high enough for reliable operation. The 350mV (typ.) hysteresis prevents supply transients from causing a shutdown. PWM Controller The loop compensation, current sensing, and slope compensation functions are provided internally. is a registered trademark of Richtek Technology Corporation. www.richtek.com 3 RT5047 Absolute Maximum Ratings (Note 1)  Supply Input Voltage, VIN ------------------------------------------------------------------------------------------- 0.3V to 30V  Output Voltage LNB, LX and BOOST Pins --------------------------------------------------------------------- 0.3V to 30V  Others Pin to GND ---------------------------------------------------------------------------------------------------- 0.3V to 6V  Power Dissipation, PD @ TA = 25C SOP-8 (Exposed pad) ------------------------------------------------------------------------------------------------ 3.44W  Package Thermal Resistance (Note 2) SOP-8 (Exposed pad), JA ------------------------------------------------------------------------------------------ 29C/W SOP-8 (Exposed pad), JC------------------------------------------------------------------------------------------ 2C/W  Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------------- 260C  Junction Temperature ------------------------------------------------------------------------------------------------ 150C  Storage Temperature Range --------------------------------------------------------------------------------------- 65C to 150C Recommended Operating Conditions (Note 3)  Supply Input Voltage ------------------------------------------------------------------------------------------------- 8V to 16V  Ambient Temperature Range--------------------------------------------------------------------------------------- 40C to 85C  Junction Temperature Range -------------------------------------------------------------------------------------- 40C to 125C Electrical Characteristics (VIN (typ.) = 12V, VIN = 8V to 16V, TA = 25C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit ERR Relative to selected VLNB target level, ILNB = 0 to 450mA -3 -- 3 % IIN_OFF EN = 0, LNB output disabled -- 0.3 0.5 mA IIN_ON EN = 1, VLNB = 18.3V, Tone = 0V -- 10 18 mA IIN_ON EN = 1, VLNB = 18.3V, 22kHz TONE Input -- 16 28 mA Boost Switch On Resistance RDS(ON) ILNB = 450mA -- 150 300 m Switching Frequency f SW 600 700 800 kHz Switch Current Limit ILIMSW VIN = 10V, VLNB = 20.5V -- 3 -- A Linear Regulator Voltage Drop VDROP VBOOST-VLNB, ILNB = 450mA -- 0.85 -- V Output Voltage Rise Time TR_LNB For VLNB = 13.3V18.3V, CLNB = 100nF, ILNB = 450mA -- 3 10 ms Output Voltage Pull-Down Time TF_LNB For VLNB = 18.3V13.3V, CLNB = 100nF, ILNB = 0mA -- 3 10 ms 20MHz Bandwidth Limit (GBD) -- 20 -- mVPP General LNB Output Accuracy, Load and Line Regulation Supply Current Ripple and Noise on LNB VRIP_PP Output Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 4 is a registered trademark of Richtek Technology Corporation. DS5047-00 March 2015 RT5047 Parameter Load Regulation Line Regulation Symbol Test Conditions Min Typ Max VLNB = 13.3V, ILNB = 50mA to 450mA -- 38 76 VLNB = 18.3V, ILNB = 50mA to 450mA -- 45 90 VIN = 9 to 14V, VLNB = 13.3V, ILNB = 50mA -10 -- 10 VIN = 9 to 14V, VLNB = 18.3V, ILNB = 50mA -10 -- 10 VOUT_LOAD VOUT_LINE Unit mV mV Protection Output Over-Current Limit ILIM_LNB1 VLNB = 13.3V/18.3V 500 550 650 mA Output Over-Current Disable Time TDIS_ON VLNB Short to GND -- 45 -- ms Output Over-Current Disable Time TDIS_OFF VLNB Short to GND (GBD) -- 1800 -- ms VIN Under-Voltage Lockout VUVLO Threshold VIN Falling -- 7.35 -- V VIN Turn On Threshold VIN Rising -- 7.7 8 V VIN Under-Voltage Lockout VUVLOHYS Hysteresis -- 350 -- mV OTP Threshold TOTP -- 140 -- C OTP Hysteresis TOTPHYS -- 15 -- C TONE Frequency FTONE 20 22 24 kHz TONE Amplitude, Peak to Peak VTONE_PP ILNB = 50 to 450mA, CLNB = 200nF 550 700 900 mVPP TONE Duty Cycle DCTONE ILNB = 0 to 450mA, CLNB = 570nF 40 50 60 % TONE Rise Time TRTONE ILNB = 0 to 450mA, CLNB = 570nF 5 10 15 s TONE Fall Time TFTONE ILNB = 0 to 450mA, CLNB = 570nF 5 10 15 s VTONE_H 1.2 -- -- V VTONE_L -- -- 0.4 V ITONELKG -- 5 10 A VEN_H 1.2 -- -- V VEN_L -- -- 0.4 V IENLKG -- 5 10 A VSEL_H 1.2 -- -- V VSEL_L -- -- 0.4 V ISELLKG -- 5 10 A VIN_TH TONE TONE Logic Input TONE Input Leakage ENABLE, SEL Pins EN Logic Input EN Input Leakage SEL Logic Input SEL Input Leakage Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5047-00 March 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 5 RT5047 Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. JA is measured at TA = 25C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. JC is measured at the exposed pad of the package. Note 3. The device is not guaranteed to function outside its operating conditions. Note 4. Operation at VIN = 16V may be limited by power loss in the linear regulator. Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 6 is a registered trademark of Richtek Technology Corporation. DS5047-00 March 2015 RT5047 Typical Application Circuit L1 10μH D1 SS14 VIN CBST 20μF /30μF CIN1 2x10μF LX BOOST VIN D3 SS14 CIN2 1μF Max. 550mA LNB EN RT5047 VLNB D2 SS14 CLNB 0.1μF D4 SMDJ20A TONE SEL GND Note : 1. D2, D3, D4, are used for surge protection. The clamping voltage of D4 is 30V, the break down voltage must be higher than 24V as recommended. 2. The capacitor C3 should not be less than 1F for the power stability. 3. EN, TONE and SEL are connected to microcontroller directly. Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5047-00 March 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 7 RT5047 Typical Operating Characteristics System Efficiency vs. Output Current Boost Efficiency vs. Output Current 95 95 90 90 Efficiency (%) 100 Efficiency (%) 100 85 80 75 85 80 75 70 70 65 65 VIN = 12V, V BOOST = 14.3V, V LNB = 13.3V VIN = 12V, VBOOST = 14.3V 60 0.00 0.10 0.20 0.30 0.40 0.50 60 0.00 0.60 0.10 Tone Amplitude vs. Temperature 0.40 0.50 0.60 Tone Amplitude vs. Output Current 0.90 0.90 0.85 0.85 Tone Amplitude (V) Tone Amplitude (V) 0.30 Output Current (A) Output Current (A) 0.80 0.75 0.70 0.65 0.80 0.75 0.70 0.65 0.60 0.60 VIN = 12V, VLNB = 13.3V, TONE enable VIN = 12V, VLNB = 13.3V, TONE enable 0.55 0.55 -50 -25 0 25 50 75 100 0 125 0.1 0.2 0.3 0.4 0.5 0.6 Output Current (A) Temperature (°C) Output Voltage v.s Temperature Output Voltage vs. Output Current 19 19 18 18 VLNB_ 18.3V VLNB_18.3 Output Voltage (V) Output Voltage (V) 0.20 17 16 15 14 VLNB_13.3 13 17 16 15 14 VLNB_13.3V 13 VIN = 12V VIN = 12V 12 12 -50 -25 0 25 50 75 100 Temperature (°C) Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 8 125 0.00 0.10 0.20 0.30 0.40 0.50 0.60 Output Current (A) is a registered trademark of Richtek Technology Corporation. DS5047-00 March 2015 RT5047 Under Voltage Lockout vs. Temperature Over Current Protect vs. Temperature 0.70 Under Voltage Lockout (V)1 8.00 Current (A) 0.65 0.60 0.55 7.80 7.60 7.40 7.20 VIN = 12V, VLNB = 13.3V 0.50 7.00 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 Temperature (°C) Temperature (°C) Tone Output Output Voltage Transition Rising 125 VLNB (5V/Div) VIN = 12V VSEL from 0V to 3.3V, CLNB = 0.1F, VLNB from 13V to 18V VLNB_ac (200mV/Div) VIN = 12V VSEL (2V/Div) Time (50s/Div) Time (500s/Div) Output Voltage Transition Falling Power On Sequence VLNB (5V/Div) VIN = 12V, VSEL from 3.3V to 0V, CLNB = 1F, VLNB from 18V to 13V VSEL (2V/Div) VIN (10V/Div) VBOOST (10V/Div) VLNB (10V/Div) Time (500s/Div) Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5047-00 March 2015 VIN = 12V Time (5ms/Div) is a registered trademark of Richtek Technology Corporation. www.richtek.com 9 RT5047 Over Current Protection VBOOST (5V/Div) VLNB (5V/Div) ILNB (500mA/Div) VIN = 12V Time (500ms/Div) Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 10 is a registered trademark of Richtek Technology Corporation. DS5047-00 March 2015 RT5047 Application Information Boost Converter/Linear Regulator with half of the inductor ripple current as shown in the The 5047 integrates a current-mode boost converter and linear regulator. Use the SEL pin to control the LNB voltage and the boost converter track is at least greater 800mV than the LNB voltage. The boost converter is high efficiency PWM architecture with 700kHz operation frequency. The linear regulator has the capability to source current up to 550mA during continuous operation. All the loop compensation, current sensing, and slope compensation functions are provided internally. following equation : The RT5047 has current limiting on the boost converter and the LNB output to protect the IC against short circuits. The internal MOSFET will turn off when the LX current is higher than 3A cycle-by-cycle. The LNB output will turn off when the output current higher than the 550mA and 45ms and turn-on after 1800ms automatically. Input Capacitor Selection The input capacitor reduces voltage spikes from the input supply and minimizes noise injection to the converter. A 30F capacitance is sufficient for most applications. Nevertheless, a higher or lower value may be used depending on the noise level from the input supply and the input current to the converter. Note that the voltage rating of the input capacitor must be greater than the maximum input voltage. Inductor Selection The inductance depends on the maximum input current. As a general rule, the inductor ripple current range is 20% to 40% of the maximum input current. If 40% is selected as an example, the inductor ripple current can be calculated according to the following equations : VOUT  IOUT(MAX)   VIN = 0.4  IIN(MAX) IIN(MAX) = IRIPPLE where η is the efficiency of the converter, IIN(MAX) is the maximum input current, and IRIPPLE is the inductor ripple current. The input peak current can IPEAK = 1.2 x IIN(MAX) note that the saturated current of the inductor must be greater than IPEAK. The inductance can eventually be determined according to the following equation : η   VIN    VOUT  VIN  2 L 0.4   VOUT   I OUT(MAX)fOSC 2 where f OSC is the switching frequency. For better system performance, a shielded inductor is preferred to avoid EMI problems. Boost Output Capacitor Selection The RT5047 boost regulator is internally compensated and relies on the inductor and output capacitor value for overall loop stability. The output capacitor is in the 30F to 50F range with a low ESR, as strongly recommended. The voltage rating on this capacitor should be in the 25V to 35V range since it is connected to the boost VOUT rail. The output ripple voltage is an important index for estimating chip performance. This portion consists of two parts. One is the product of the inductor current with the ESR of the output capacitor, while the other part is formed by the charging and discharging process of the output capacitor. As shown in Figure 1, VOUT1 can be evaluated based on the ideal energy equalization. According to the definition of Q, the Q value can be calculated as the following equation :   Q = 1   IIN  1 IL  IOUT    IIN  1 IL  IOUT   2  2 2    V  IN  1 = COUT  VOUT1 VOUT fOSC where f OSC is the switching frequency and IL is the inductor ripple current. Bring COUT to the left side to estimate the value of VOUT1 according to the following equation : VOUT1 = D  IOUT   COUT  fOSC then be obtained by adding the maximum input current Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5047-00 March 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 11 RT5047 where D is the duty cycle and η is the boost converter efficiency. Finally, take ESR into consideration, the overall output ripple voltage can be determined by the operation. The 350mV (typ.) hysteresis prevents supply transients from causing a shutdown. Once the input voltage exceeds the UVLO rising threshold, start-up following equation : begins. When the input voltage falls below the UVLO falling threshold, all IC internal functions will be turned off by the controller. VOUT = IIN  ESR  D  IOUT   COUT  fOSC The output capacitor, COUT, should be selected accordingly. ΔIL Input Current Inductor Current Output Current Time (1-D)TS Output Ripple Voltage (ac) Time ΔVOUT1 Over-Current Protection The RT5047 features an over-current protection function to prevent chip damage from high peak currents. Both the boost converter and the linear regulator have independent current limit. In the boost converter, this is achieved through cycle-by-cycle internal current limit. During the ON-period, the chip senses the inductor current that is flowing into the LX pin. The internal NMOS will be turned off if the peak inductor current reaches the current-limit value of 3A (typ.).When the linear regulator exceeds 550mA (typ.) more than 45ms, the LNB output will be disabled. During this period of time, if the current limit condition disappears, the OCP will be cleared and the part restarts. If the part is still in current limit after this time period, the linear regulator and boost converter will automatically disable to prevent the part from overheating. Figure 1. The Output Ripple Voltage without the Short Circuit Protection Contribution of ESR Schottky Diode Selection Schottky diodes are chosen for their low forward-voltage drop and fast switching speed. However, when making a selection, important parameters such as power dissipation, reverse voltage rating, and pulsating peak current should all be taken into consideration. A suitable Schottky diode’s reverse voltage rating must be greater than the maximum output voltage and its average current rating must exceed the average output current. The chosen diode should also have a sufficiently low leakage current level, since it increases with temperature. Under-Voltage Lockout (UVLO) The UVLO circuit compares the input voltage at VIN with the UVLO threshold (7.7V rising typically) to ensure that the input voltage is high enough for reliable Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 12 If the LNB output is shorted to ground, and more than 45ms, the RT5047 will be disabled 1.8s then enable automatically. Over-Temperature Protection When the junction temperature reaches the critical temperature (typically 140 oC), the boost converter and the linear regulator are immediately disabled. When the junction temperature cools down to a lower temperature threshold specified, the RT5047 will be allowed to restart by normal start operation. LNB Output Voltage The RT5047 has voltage control function on the LNB output. This function provides 4 levels for the common standards and compensation if the cable line has voltage drop. These voltage levels are defined in table 1. The rise time and fall time of the VLNB is 3mS (typ.). is a registered trademark of Richtek Technology Corporation. DS5047-00 March 2015 RT5047 Table 1 SEL Pin Status LNB Output Voltage 0 13.3V 1 18.3V Tone Generation The RT5047 provides the tone generation function, please refer to the Figure 2. Set the TONE pin with 22kHz logic signal, the LNB linear regulator output will carry a 22kHz, 700mV peak to peak signal for DiSEqC 1.x communication. It can meet base-band timings of 500s (±100s) for a one-third bit PWK coded signal period on a nominal 22kHz (±20 %). LNB 13.3V or 18.3V 700m V VLNB output TONE when TONE signal rise up VLNB close TONE after TONE signal detect time TONE signal detect time 3.3V TONE signal 0V Figure 2. Tone Generation Options Pull-Down Rate Control The output linear stage provides approximately 40mA of pull-down capability. This ensures that the output If loading is 1000mA 25ms volts are ramped from 18.3V to 13.3V in a reasonable amount of time. Over-Current Disable Time OCP1=1000mA OCP1=1000mA 25ms OCP2=550mA 20ms 20ms 1800ms If LNB is shorted to GND OCP1=250mA OCP1=250mA If the LNB output current exceeds 550mA, typical, for more than 45ms, then the LNB output will be disabled and device enters a TON = 45ms/TOFF = 1800ms OCP2=550mA 25ms 25ms OCP2=138mA OCP2=138mA 20ms 20ms 1800ms routine. It will be returned to normal operation after a successful soft-start process. Inrush Current At start-up or during a LNB reconfiguration event, a transient surge current above the normal DC operating level can be provided by the IC. This current increase can be as high as 550mA, typical, for as long as required, up to a maximum of 45ms. Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5047-00 March 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 13 RT5047 The RT5047 can handle up to 500mA during continuous operation. Thermal Considerations For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : PD(MAX) = (TJ(MAX)  TA) / JA where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and JA is the junction to ambient thermal resistance.For recommended operating condition specifications, the maximum junction temperature is 125C. The junction to ambient thermal resistance, JA, is layout dependent. For Maximum Power Dissipation (W) 1 DC Current 5.0 Four-Layer PCB 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 25 50 75 100 125 Ambient Temperature (°C) Figure 3. Derating Curve of Maximum Power Dissipation SOP-8 (Exposed Pad) package, the thermal resistance, JA, is 29C/W on a standard JEDEC 51-7 four-layer thermal test board. The maximum power dissipation at TA = 25C can be calculated by the following formula : PD(MAX) = (125C  25C) / (29C/W) = 3.44W for SOP-8 (Exposed Pad) package The maximum power dissipation depends on the operating ambient temperature for fixed TJ(MAX) and thermal resistance, JA. The derating curve in Figure 3 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 14 is a registered trademark of Richtek Technology Corporation. DS5047-00 March 2015 RT5047 Layout Consideration For high frequency switching power supplies, the PCB layout is important to get good regulation, high efficiency and stability. The following descriptions are the guidelines for better PCB layout.  For good regulation, place the power components as close as possible. The traces should be wide and short enough especially for the high-current loop.  Minimize the size of the LX node and keep it wide and shorter.  The exposed pad of the chip should be connected to a strong ground plane for maximum thermal consideration. The CIN, CBST and CLNB should be placed as closed as possible to R T 5 0 4 7 f o r good filter. D 3 and D 4 should be placed as closed as possible to VOUT for surge protection. VOUT D4 CLNB1 The exposed pad of the chip should be connected to analog ground plane for thermal consideration. D2 LNB TONE D3 BOOST CBST1 CBST2 CBST3 NC GND D1 LX SEL L1 VIN VIN CIN1 The TONE, SEL and EN pin should be connected to MCU or GND. Do not floating these pins. EN CIN2 The inductor should be placed as close as possible to the L X pin to minimize the noise coupling into other circuits. LX node copper area should be minimized for reducing EMI Place the power components as close as possible. The traces should be wide and short especially for the high-current loop. Figure 4. PCB Layout Guide Copyright © 2015 Richtek Technology Corporation. All rights reserved. DS5047-00 March 2015 is a registered trademark of Richtek Technology Corporation. www.richtek.com 15 RT5047 Outline Dimension Dimensions In Millimeters Symbol Dimensions In Inches Min Max Min Max A 4.801 5.004 0.189 0.197 B 3.810 4.000 0.150 0.157 C 1.346 1.753 0.053 0.069 D 0.330 0.510 0.013 0.020 F 1.194 1.346 0.047 0.053 H 0.170 0.254 0.007 0.010 I 0.000 0.152 0.000 0.006 J 5.791 6.200 0.228 0.244 M 0.406 1.270 0.016 0.050 X 2.000 2.300 0.079 0.091 Y 2.000 2.300 0.079 0.091 X 2.100 2.500 0.083 0.098 Y 3.000 3.500 0.118 0.138 Option 1 Option 2 8-Lead SOP (Exposed Pad) Plastic Package Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. Copyright © 2015 Richtek Technology Corporation. All rights reserved. www.richtek.com 16 is a registered trademark of Richtek Technology Corporation. DS5047-00 March 2015
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