®
RT5701
3MHz 4A High Efficiency Step-Down Converter with I2C
Interface
General Description
The RT5701 is a Peak-Current Mode Pulse-WidthModulated (PWM) step-down DC/DC converter with I2C
control interface. Capable of delivering 4A continuing output
current over a wide input voltage range from 2.5V to 5.5V,
the RT5701 is ideally suited for Automotive Infotainment
applications for low-voltage outputs to Micro controllers
and ASICs in Navigation, Information Display, and Audio
systems, Video systems and other battery operated
systems requiring very low Shutdown current and
Quiescent current consumption.
Internal synchronous rectifier with low RDS(ON) dramatically
reduces conduction loss at PWM mode. No external
Schottky barrier diode is required in practical application.
The RT5701 enters low-dropout mode when normal PWM
cannot provide regulated output voltage by continuously
turning on the upper P-MOSFET. The RT5701 enters shutdown mode and consumes less than 5μA when the EN
pin is pulled low. The switching ripple is easily smoothedout by small package filtering elements due to a fixed
operation frequency of 3MHz. This along with small
TSSOP-14 (Exposed Pad) package provides small PCB
area applications.
The RT5701 also includes Dynamic Voltage Scaling (DVS)
for system low power applications.
The I2C interface let the RT5701 controllable flexibly to
select VOUT voltage level, peak current limit level, PWM
control mode, and so on. Other features include soft-start,
auto discharge, lower internal reference voltage, overtemperature, and over-current protection.
Features
2.5V to 5.5V Input Range
Output Range from 0.3V to 5.5V
Bank 0 : 0.3V to 0.7V
Bank 1 : 0.6V to 1.4V
Bank 2 : 1.2V to 2.8V
Bank 3 : 2.4V to 5.5V
The Default Value is 1.5V (VSEL = High) and 1V
(VSEL = Low)
4A Continuing Output Current
Support DVS in the Same Bank
VOUT Adjusting Range (max, min) is Settable
High Efficiency
84% at 5V 1.5V with 1.5A Load
3MHz Fixed-Frequency PWM Operation
Auto-PSM/PWM or Force-PWM Selectable
Support Remote Ground Sensing for Accurate
Output Voltage
Dedicated Hardware Pin to Immediately Switch
Nominal Output Voltage Setting
Output Discharging when Turning Off
Over-Current Protection
OC Level Settable
Simplified Application Circuit
Input Power
RT5701
PVIN
LX
Output
Load
AVDD
GNDR
Enable
2
I C Control
VOUT Select
EN
SCL
VOUT
SDA
GND
VSEL
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RT5701
Over-Temperature Protection
Integrated Soft-Start Function
2
Enabling Control by Enable Pin and I C Register
Setting by Software
2
I C Interface
2
I C Communication allowed Even in Off-State
(EN = L)
Support Fast Mode (400kbps)
Registers Setting Retained in Off-State (EN = L)
RoHS Compliant and Halogen Free
Applications
Automotive Infotainment Systems
Microprocessor and DSP Core Supply
Industrial-Grade Point-of-Load
Cellular Telephones
Personal Information Appliances
Wireless and DSL Modems
MP3 Players
Portable Instruments
Ordering Information
RT5701
Package Type
CP : TSSOP-14 (Exposed Pad)
Lead Plating System
G : Green (Halogen Free and Pb Free)
Note :
Richtek products are :
RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.
Suitable for use in SnPb or Pb-free soldering processes.
Pin Configurations
(TOP VIEW)
VSEL
EN
SCL
GNDR
VOUT
NC
AVDD
14
2
13
3
4
12
GND
5
6
7
11
10
15
9
8
SDA
GND
LX
LX
NC
PVIN
PVIN
TSSOP-14 (Exposed Pad)
Marking Information
RT5701GCP : Product Number
RT5701
GCPYMDNN
YMDNN : Date Code
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RT5701
Functional Pin Description
Pin No.
Pin Name
Pin Function
VSEL
Nominal VOUT setting select input pin.
VSEL = Low selects {0x11.ENSEL0, 0x11.VoutSEL0[6:0], 0x14.PWM0,
0x1D.VOUT_BANK0[1:0]}.
VSEL = High selects {0x10.ENSEL1, 0x10.VoutSEL1[6:0], 0x14.PWM1,
0x1C.VOUT_BANK1[1:0]}.
If 0x1C.VOUT_BANK1[1:0] 0x1D.VOUT_BANK0[1:0], do not toggle VSEL
when EN = High.
2
EN
Enable Control Input. The IC enable control pin turns on the step-down
converter if the internal register ENSEL bit = 1. If ENSEL = 0, EN goes high still
cannot enable step-down converter. The EN pin includes a internal pull-down
current about 1A. When IC protection occurs and is latched in shutdown state,
toggling EN or re-power AVDD can reset the latch state.
3
SCL
I C Interface Clock Input.
4
GNDR
Remote Ground Sense Input.
5
VOUT
Step-Down Converter Output Voltage Sense Input.
NC
No Internal Connection.
13,15
(Exposed Pad)
GND
Ground. The exposed pad must be soldered to a large PCB and connected to
GND for maximum power dissipation.
7
AVDD
Analog and I C Interface Power Input.
8, 9
PVIN
Power Input. Input capacitor C IN must be placed as close to IC as possible.
LX
Switch Node.
SDA
I C Interface Data Input.
1
6, 10
11,12
14
2
2
2
Functional Block Diagram
AVDD
VSEL
EN
E-Fuse
Bandgap
Register File
DVS
PVIN
UVLO
Bias Supply
Thermal
Shutdown
VREF
PWM Control Logic
SCL
FB
2
I C
Oscillator
VOUT
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Gate Driver
LX
Soft-Start
SDA
GNDR
Current Limit Detect
Negative Inductor
Current Detect
GND
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RT5701
Operation
The RT5701 is a low voltage synchronous step-down
converter that can support the input voltage range from
2.5V to 5.5V and can deliver up to 4 A at an I2C selectable
voltage ranging from 0.3 V to 5.5 V, distributed into 4
banks of output voltages. The converter can operate in
Auto mode or forced PWM mode. Operating modes and
output voltage can be selected via I2C.
By adapting current mode architecture, converter decides
its switching duty by inductor current sense information,
compensation ramp and error amplifier output. The
converter turns on the high-side P-MOSFET whenever the
raising edge of the switching clock. After the decided duty
time, the high-side P-MOSFET would be turned off and
the low-side N-MOSFET would be turned on until the next
frequency clock raising in forced PWM mode or turn off
by ZC (Zero Current Detection) in auto mode. The error
amplifier may adjust its output, COMP, with selected
voltage reference and output feed-back voltage information.
Different selection of voltage reference and different loading
at output node regulate the required COMP voltage, which
regulating the output voltage.
VSEL Function for Immediately Voltage Change
To address different performance operating points and
startup conditions, the device offers two output voltage /
mode presets, which can be chosen via a dedicated VSEL
pin; this allows simple and zero latency output voltage
transition.
Operating Mode Selection
The converter can operate in Auto mode or forced PWM
mode. It can be selected by programming register
0x14.PWM0 for VSEL = Low or 0x14.PWM1 for VSEL =
High. If Auto mode is selected, the converter automatically
switches the operation mode between PWM and PSM
according to the load conditions. If forced PWM mode is
selected, the converter works only in PWM mode.
PWM (Pulse Width Modulation) Operating Mode
The converter operates in PWM (Pulse Width Modulation)
mode from medium to heavy load. In PWM mode, the
converter operates with its nominal switching frequency
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of 3MHz, and adapts its duty cycle to regulate the desired
output voltage. In this mode, the inductor current is in
CCM (Continuous Current Mode) and the voltage is
regulated by PWM.
Forced PWM (FPWM) Operating Mode
If forced PWM mode is selected, the converter works only
in PWM mode, and disables the transition from PWM to
PSM as the load decreases. The advantage of forced PWM
is that the switching frequency is fixed to be 3MHz, and
thus it is easy for EMI immunity design. The disadvantage
is that the efficiency at light load is poor due to the negative
inductor current.
Pulse Skipping Modulation (PSM) Operating Mode
When in Forced PWM operating mode without output
current loading, half of FPWM inductor current is negative
to balance total average zero output current. If that negative
inductor current could be saved, the efficiency will be
improved strongly. PSM is one Buck operation mode with
zero inductor current detection. Whenever zero current
occur, the low-side N-MOSFET is turned off immediately
and save the resident power into output capacitor (store
energy in higher VOUT). Then, the converter skips internal
synchronous clock and keeps sleep-state until output
voltage is discharged to below its target value. Once skips
occurs, the power MOSFETs of converter is turned off
and lots of sub-block circuits is in sleep state to save
quiescent consumption. If the output loading is increasing,
the discharge time is shortened, i.e. the switching
frequency depends on the output loading. The switch
frequency is decayed from 3MHz; the lighter output
loading, the lower switch frequency. As result, PSM VOUT
ripple would be slightly larger than FPWM but PSM gains
significant efficiency improvement.
Auto-Zero Current Detector
The Auto-Zero Current (AZC) detector circuit senses the
LX waveform to adjust the inductor zero current threshold
voltage automatically. In traditional trimmed zero current
detectors, the zero current threshold changes due to
VIN / VOUT variation. This would degrade efficiency due to
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RT5701
the extra power consumption by body diode or negative
inductor current. Regard with this defect, AZC adjusts
current threshold continuously when the RT5701 is
operating. With AZC circuit, the RT5701 could avoid
negative current in PSM mode and could achieve higher
efficiency performance.
Minimum Peak Current
Minimum peak current is an evolution version from
minimum on time. Rather than fixed minimum on time,
Minimum peak current produce the “effective minimum
on time” which could be adjusted according to VIN/VOUT
condition.
L
IMIN_Peak
TON =
VIN VOUT
It's an advantage to not provide too much energy at low
duty; also, to not provide too less energy at high duty.
When the converter is in PSM operation, every time pulse
skip duration finishes, the converter will provide current
energy for output loading by turning on P-MOSFET until
inductor current achieve minimum peak current.
reference voltage into another reference voltage in steps
smoothly. The slew rate of the internal reference voltage
is around 3mV / 10μs. Please note DVS function could
only be available in the same output voltage bank.
Remote Ground Sensing
The RT5701 can deliver output current up to 4A. Inevitably,
there is voltage drops due to the routing trace resistance
between output node and chip location, especially when
heavy loading. Also, voltage drops exist in ground trace.
Remote ground sensing pin, GNDR, can tell the converter
the lost drops to compensate to the correct and accuracy
voltage level.
Active Output Discharge
To make sure that no residual voltage remains in the power
supply rail, an active discharge path can ground the output
voltage. The output gets discharged by the LX pin with a
typical discharge resistor when the device shuts down.
This feature can be easily disabled or enabled with register
0x12.Discharge. By default the discharge path is active.
The default value of the feature is factory programmable.
Low Power Mode (LPM)
The RT5701 provides Low Power Mode (LPM) to save
more quiescent consumption. With maximum output
current ability, 1mA, LPM enhances the efficiency at load
below 100μA, more than the Pulse Skipping Mode (PSM)
does. This extremely efficiency improvement may extend
battery life, especially in stand-by mode of hand held
products.
Power Good
When the output voltage is higher than Power Good rising
threshold, the Power Good flag, register 0x01.SEN_PG
is high.
Under-Voltage Lockout (UVLO)
The converter can be enabled or disabled by IC pin, EN.
For more flexibility, users can turn on/off the converter by
I2C programming. There are ENSEL register bit located in
register 0x10.ENSEL1 and 0x11.ENSEL0 to control
internal enable signal for both VSEL selection high/low.
The UVLO continuously monitors the PVIN voltage to make
sure the device works properly. When the PVIN is high
enough to reach the UVLO high raising threshold voltage,
2.4V, the converter softly starts. When the PVIN decreases
to its UVLO low threshold voltage, 2.3V, the device will
shut down. The event is recorded in register
0x18.PVIN_UVLO. The record can be reset with I2C
interface or automatically reset by re-power-on AVDD.
Dynamic Voltage Scaling (DVS)
Output Under-Voltage Protection (UVP)
Users can select required output voltage bank and preferred
output voltage by I2C programming. When output voltage
is changed, the RT5701 provides Dynamic Voltage Scaling
(DVS) skill to prevent any undershoot or overshoot when
output voltage transition. The DVS means to adjust one
When the output voltage is lower than UVP threshold
(~50% of nominal target) after soft-start, the UVP is
triggered. The converter will be latched and the output
voltage will no longer be regulated during UVP latched
state. Re-power-on input voltage or EN pin can unlatch
Enabling
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RT5701
the protection state. Using I2C to shutdown the system
and then re-enable it will also unlatch UVP function. The
event is recorded in register 0x18.SCP. The record can
be reset with I2C interface or automatically reset by repower-on AVDD.
For short-circuit time > 5ms, the RT5701 will try to recover
in 4ms after the short-circuit occurs. If it still fails to recover
in 1ms later, it will try to recover in another 4ms cycle.
EN
VOUT
Over-Current Protection (OCP)
The converter senses the current signal when the highside P-MOSFET turns on. As a result, The OCP is cycleby-cycle current limitation. If the OCP occurs, the converter
holds off the next on pulse until inductor current drops
below the OCP limit. The event is recorded in register
0x18.OCP. The record can be reset with I2C interface or
automatically reset by re-power-on AVDD. The OCP level
can be set with 0x16.IPEAK[1:0].
Short-Circuit
Occurs
Auto
Recovery
4ms
4ms
1ms
If short-circuit occurs before enable, and the IC fails to
turn on in 1ms, it will recover in 4ms later.
EN
Over-Temperature Protection (OTP)
The converter has an over-temperature protection. When
the junction temperature is higher than the thermal
shutdown rising threshold, the system will be latched and
the output voltage will no longer be regulated until the
junction temperature drops under the falling threshold.
Output Under-Voltage Protection (UVP)
For short-circuit time < 4ms, the IC will automatically
recovers in 4ms after the short-circuit occurs.
VOUT
Short-Circuit
Occurs
Auto Recovery
4ms
1ms
EN
VOUT
Short-Circuit
Occurs
Auto
Recovery
4ms
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RT5701
Absolute Maximum Ratings
(Note 1)
Supply Input Voltage, PVIN and AVDD --------------------------------------------------------------------------------Switch Node DC Rating, LX ---------------------------------------------------------------------------------------------EN, VOUT, SCL, SDA Voltage -----------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C
TSSOP-14 (Exposed Pad) ----------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2)
TSSOP-14 (Exposed Pad), θJA ----------------------------------------------------------------------------------------TSSOP-14 (Exposed Pad), θJC ----------------------------------------------------------------------------------------Junction Temperature -----------------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------------------Storage Temperature Range --------------------------------------------------------------------------------------------ESD Susceptibility (Note 3)
HBM (Human Body Model) ----------------------------------------------------------------------------------------------MM (Machine Model) ------------------------------------------------------------------------------------------------------
Recommended Operating Conditions
6V
6V
−0.3V to 6V
3.32W
30.1°C/W
7.5°C/W
150°C
260°C
−65°C to 150°C
2kV
200V
(Note 4)
Supply Input Voltage, AVDD and PVIN --------------------------------------------------------------------------------Junction Temperature Range --------------------------------------------------------------------------------------------Ambient Temperature Range --------------------------------------------------------------------------------------------Input Capacitance ----------------------------------------------------------------------------------------------------------Output Capacitance -------------------------------------------------------------------------------------------------------Inductance --------------------------------------------------------------------------------------------------------------------
2.5V to 5.5V
−40°C to 125°C
−40°C to 105°C
10μF
22μF
0.33μH
Electrical Characteristics
(VIN = 3.6V, VOUT = 2.5V, L = 0.33μH, CIN = 10μF, COUT = 22μF, TA = −40°C to 105°C, unless otherwise specification)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Input Voltage Start-up
VIN
AVDD and PVIN
2.45
--
5.5
V
Input Voltage Range
VIN
IOUT = 2A
2.5
--
5.5
V
GNDR Current
IGNDR
IOUT = 0mA, No Switching
--
--
10
A
Shutdown Current
ISHDN
EN = GND
--
1
5
A
Adjustable Output Range for
VOUT
Internal Feedback Network
SDA = SCL = High at AVDD Power
On, 0x1D.VOUT_BANK[1:0] = 2’b10
1.2
--
2.8
V
Output Voltage Accuracy in
Normal Mode
VOUT
VIN = 2.5V to 5.5V, 0A < IOUT < 2.7A
2
--
2
%
Output Voltage Accuracy in
Low Power Mode
VOUT
VIN = 2.5V to 5.5V, 0A < IOUT < 1mA
5
--
5
%
P-Channel On-Resistance
RDS(ON)_P
IOUT = 200mA
--
40
--
m
N-Channel On-Resistance
RDS(ON)_N
IOUT = 200mA
--
20
--
m
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RT5701
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
P-Channel Current Limit
ILIM_P
0x16.IPEAK[1:0] = 2’b11
5.2
6.2
7.2
A
Under-Voltage Lockout
Threshold (Falling)
UVLO_F
PVIN Falling
2.15
2.3
2.45
V
UVLO Hysteresis gap
UVLO_Hys
--
0.1
--
V
Oscillator Frequency
fOSC
2.7
3
3.3
MHz
100
--
--
%
VOUT = 1V, From EN going high to
90% of nominal VOUT
--
420
--
s
VOUT Power Good
Threshold (Rising)
Nominal VOUT Ratio
--
90
--
%
Power Conversion
Efficiency
5V to 1.5V and Load = 1.5A
5V to 1V and Load = 1.5A
---
84
78
---
%
Line Regulation
--
0.25
--
%/V
Load Regulation
--
0.25
--
%/A
5V to 2.5V and Load Current step
1.5A in 10s Rising Time
--
50
--
mV
EN = GND
--
40
--
Maximum Duty Cycle
Start-Up Time
tST
Load Transient Drop
Output Discharge Resistor
ROD
Thermal Shutdown
Threshold
TSD
--
150
--
°C
Thermal Shutdown
Hysteresis
TSD
--
20
--
°C
--
1
--
A
Logic-High
1.05
--
--
Logic-Low
--
--
0.4
Min
Typ
Max
High-Level
1.05
--
--
Low-Level
--
--
0.4
--
--
400
kHz
Hold Time (Repeated) START
Condition.
t
After this Period, the First Clock HD;STA
Pulse is Generated
0.6
--
--
s
LOW Period of the SCL Clock
tLOW
1.3
--
--
s
HIGH Period of the SCL Clock
tHIGH
0.6
--
--
s
EN, VSEL Pull Low Current
EN, VSEL
Input Voltage
V
I2C for Fast Mode
(AVDD = 3.6V, TA = −40°C to 105°C, unless otherwise specification)
Parameter
SDA, SCL Input
Voltage
Symbol
Test Conditions
Unit
V
Fast Mode
SCL Clock Rate
fSCL
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RT5701
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Set-Up Time for a Repeated
START Condition
tSU;STA
0.6
--
--
s
Data Hold Time
tHD;DAT
0
--
0.9
s
Data Set-Up Time
tSU;DAT
100
--
--
ns
Set-Up Time for STOP
Condition
tSU;STO
0.6
--
--
s
Bus Free Time between a
STOP and START Condition
tBUF
1.3
--
--
s
Rising Time of both SDA and
SCL Signals
tr
20
--
300
ns
Falling Time of both SDA and
SCL Signals
tf
20
--
300
ns
2
--
--
mA
SDA and SCL Output Low Sink
IOL
Current
SDA or SCL Voltage = 0.4V
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
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RT5701
Typical Application Circuit
RT5701
8, 9
VBAT
LX
PVIN
11, 12
L1
0.33µH
COUT
22µF
CIN1
10µF
R3
220
7
VBAT
AVDD
CIN2
1µF
GNDR
VOUT
VBAT
GND
RSCL
1k
RSDA
1k
2
I C
3 SCL
14 SDA
EN
VSEL
VOUT
Load
4
5
13, 15 (Exposed Pad)
2
1
Enable
Vout Select
Figure 1. Typical Application Circuit for I2C Control
RT5701
8, 9
VBAT
PVIN
LX
11, 12
COUT
22µF
CIN1
10µF
R3
220
VBAT
GNDR
7
AVDD
VOUT
CIN2
1µF
GND
AVDD
L1
0.33µH
3 SCL
14 SDA
EN
VSEL
VOUT
Load
4
5
13, 15 (Exposed Pad)
2
1
Enable
Vout Select
Figure 2. Typical Application Circuit for Internal Resistor Control without I2C
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RT5701
Typical Operating Characteristics
Buck Efficiency vs. Output Current
100
Buck Efficiency vs. Output Current
100
PWM
PWM
90
90
80
VBAT =
VBAT =
VBAT =
VBAT =
VBAT =
VBAT =
VBAT =
70
60
50
40
30
3V
3.3V
3.6V
3.9V
4.2V
4.5V
5V
Efficiency (%)
Efficiency (%)
80
20
70
VBAT =
VBAT =
VBAT =
VBAT =
VBAT =
VBAT =
VBAT =
60
50
40
30
20
10
10
VOUT = 1.5V, L = 0.33μH, COUT = 22μF
0
0.001
0.01
0.1
1
VOUT = 1V, L = 0.33μH, COUT = 22μF
0
0.001
10
0.01
Output Current (A)
Auto-PSM
10
Auto-PSM
90
VBAT =
VBAT =
VBAT =
VBAT =
VBAT =
VBAT =
VBAT =
70
60
50
40
80
3V
3.3V
3.6V
3.9V
4.2V
4.5V
5V
Efficiency (%)
80
Efficiency (%)
1
Buck Efficiency vs. Output Current
100
90
30
20
VBAT =
VBAT =
VBAT =
VBAT =
VBAT =
VBAT =
VBAT =
70
60
50
40
3V
3.3V
3.6V
3.9V
4.2V
4.5V
5V
30
20
10
10
VOUT = 1.5V, L = 0.33μH, COUT = 22μF
0
0.001
0.01
0.1
1
VOUT = 1V, L = 0.33μH, COUT = 22μF
0
0.001
10
0.01
Output Current (A)
1.60
1.55
1
10
Buck Output Voltage vs. Output Current
1.20
3V
3.3V
3.6V
3.9V
4.2V
4.5V
5V
VBAT =
VBAT =
VBAT =
VBAT =
VBAT =
VBAT =
VBAT =
1.15
Output Voltage (V)
VBAT =
VBAT =
VBAT =
VBAT =
VBAT =
VBAT =
VBAT =
1.65
0.1
Output Current (A)
Buck Output Voltage vs. Output Current
1.70
Output Voltage (V)
0.1
Output Current (A)
Buck Efficiency vs. Output Current
100
1.50
1.45
1.40
1.10
1.05
3V
3.3V
3.6V
3.9V
4.2V
4.5V
5V
1.00
0.95
0.90
0.85
1.35
VOUT = 1.5V, COUT = 22μF
VOUT = 1V, COUT = 22μF
0.80
1.30
0
0.5
1
1.5
2
2.5
3
3.5
Output Current (A)
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3V
3.3V
3.6V
3.9V
4.2V
4.5V
5V
December 2014
4
0
0.5
1
1.5
2
2.5
3
3.5
4
Output Current (A)
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RT5701
Buck Output Voltage vs. Input Voltage
Buck Output Voltage vs. Input Voltage
1.70
1.20
ILOAD = 0A
ILOAD = 1A
ILOAD = 2A
ILOAD = 3A
ILOAD = 4A
1.60
1.55
ILOAD = 0A
ILOAD = 1A
ILOAD = 2A
ILOAD = 3A
ILOAD = 4A
1.15
Output Voltage (V)
Output Voltage (V)
1.65
1.50
1.45
1.40
1.35
1.10
1.05
1.00
0.95
0.90
0.85
VOUT = 1.5V, COUT = 22μF
VOUT = 1V, COUT = 22μF
1.30
0.80
3
3.5
4
4.5
5
5.5
3
3.5
Input Voltage (V)
4.5
5
5.5
Input Voltage (V)
Buck Output Voltage vs. Input Voltage
Buck Output Voltage vs. Input Voltage
1.70
1.20
Low Power Mode
Low Power Mode
1.65
1.15
ILOAD = 0mA
ILOAD = 1mA
1.60
Output Voltage (V)
Output Voltage (V)
4
1.55
1.50
1.45
1.40
1.35
ILOAD = 0mA
ILOAD = 1mA
1.10
1.05
1.00
0.95
0.90
0.85
VOUT = 1.5V, COUT = 22μF
1.30
VOUT = 1V, COUT = 22μF
0.80
3
3.5
4
4.5
5
5.5
3
4
4.5
5
Input Voltage (V)
Input Voltage (V)
Buck Output Ripple Voltage
Buck Output Ripple Voltage
Light Load
5.5
Heavy Load
LX
(2V/Div)
LX
(2V/Div)
VOUT_ac
(10mV/Div)
VOUT_ac
(10mV/Div)
VBAT = 3.6V, VOUT = 1.5V,
IOUT = 300mA, L = 0.33μH, COUT = 22μF
Time (250ns/Div)
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3.5
VBAT = 3.6V, VOUT = 1.5V,
IOUT = 3A, L = 0.33μH, COUT = 22μF
Time (250ns/Div)
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Buck Output Ripple Voltage
Buck Output Ripple Voltage
Heavy Load
Light Load
LX
(2V/Div)
LX
(2V/Div)
VOUT_ac
(10mV/Div)
VOUT_ac
(10mV/Div)
VBAT = 3.6V, VOUT = 1V,
IOUT = 3A, L = 0.33μH, COUT = 22μF
VBAT = 3.6V, VOUT = 1V,
IOUT = 300mA, L = 0.33μH, COUT = 22μF
Time (250ns/Div)
Time (250ns/Div)
Load Transient Response
Load Transient Response
IOUT
(2A/Div)
IOUT
(2A/Div)
VOUT_AC
(50mV/Div)
VOUT_AC
(50mV/Div)
VBAT = 3.6V, VOUT = 1.5V,
IOUT = 2.5 to 4A, L = 0.33μH, COUT = 22μF
Time (250μs/Div)
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VBAT = 3.6V, VOUT = 1V,
IOUT = 2.5 to 4A, L = 0.33μH, COUT = 22μF
Time (250μs/Div)
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RT5701
Application Information
The basic RT5701 application circuit is shown in Typical
Application Circuit. External component selection is
determined by the maximum load current and begins with
the selection of the inductor value and operating frequency
followed by CIN and COUT.
Inductor Selection
The inductor value and operating frequency determine the
current ripple according to a specific input and output
voltage. The ripple current, ΔIL, increases with higher VIN
and decreases with higher inductance, as shown in
equation below :
V
V VOUT
IL = 1 OUT IN
f
VIN
L
where f is the switch frequency and L is the inductance.
Having a lower ripple current reduces not only the ESR
losses in the output capacitors, but also the output voltage
ripple. Higher operating frequency combined with smaller
ripple current is necessary to achieve high efficiency. The
largest ripple current occurs at the highest VIN. To
guarantee that the ripple current stays below the specified
ΔIL(MAX), the inductor value should be chosen according to
the following equation :
VIN(MAX) VOUT
V
L = 1 OUT
f VIN(MAX)
IL(MAX)
The inductor's current rating (defined by a temperature
rise from 25°C ambient to 40°C) should be greater than
the maximum load current and its saturation current should
be greater than the short-circuit peak current limit. Refer
to Table 1 for the suggested inductor selection.
Table 1. Suggested Inductors for Typical Application Circuit
Inductor Value
Component Supplier / Part Number
Dimensions
(LxWxH mm)
ISAT(L-30%) / DCR
0.33H
Coilcraft / XFL4015-331
4.0x4.0x1.5
7A / 6.8m
0.47H
Coilcraft / XFL4015-471
4.0x4.0x1.5
5.4A / 7.6m
0.47H
SUMIDA / CDMCDS-R47MC
2.5x2.0x1.2
4.8A / 15.0 m
0.47H
TDK / TFM252010G
2.5x2.0x1.0
4.5A / 24.0m
Input and Output Capacitor Selection
An input capacitor, C IN, is needed to filter out the
trapezoidal current at the source of the high-side MOSFET.
To prevent large ripple current, a low ESR input capacitor
sized for the maximum RMS current should be used. The
RMS current is given by :
V
VIN
IRMS = IOUT(MAX) OUT
1
VIN
VOUT
This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT(MAX) / 2. This simple worst-case condition is
commonly used for design. Choose a capacitor rated at a
higher temperature than required. Several capacitors may
also be paralleled to meet the size or height requirements
of the design. Ceramic capacitors have high ripple current,
high voltage rating and low ESR, which makes them ideal
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14
for switching regulator applications. However, they can
also have a high voltage coefficient and audible
piezoelectric effects. The high Q of ceramic capacitors
with trace inductance can lead to significant ringing. When
a ceramic capacitor is used at the input and the power is
supplied by a wall adapter through long wires, a load step
at the output can induce ringing at the input, VIN. At best,
this ringing can couple to the output and be mistaken as
loop instability. At worst, a sudden inrush of current
through the long wires can potentially cause a voltage
spike at VIN large enough to damage the part. Thus, care
must be taken to select a suitable input capacitor.
The selection of COUT is determined by the required ESR
to minimize output voltage ripple. Moreover, the amount
of bulk capacitance is also a key for COUT selection to
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ensure that the control loop is stable. Loop stability can
be checked by viewing the load transient response. The
output voltage ripple, VOUT, is determined by :
1
VOUT IL ESR +
8 fOSC COUT
where fOSC is the switching frequency and IL is the inductor
ripple current.
The output voltage ripple will be the highest at the
maximum input voltage since IL increases with input
voltage. Multiple capacitors placed in parallel may be
needed to meet the ESR and RMS current handling
requirement. Ceramic capacitors have excellent low ESR
characteristics, but can have a high voltage coefficient
and audible piezoelectric effects. The high Q of ceramic
capacitors with trace inductance can also lead to significant
ringing. Nevertheless, high value, low cost ceramic
capacitors are now becoming available in smaller case
sizes. Their high ripple current, high voltage rating and
low ESR make them ideal for switching regulator
applications.
VSEL Function Selection
Figure 3 shows the detailed logic of VSEL function. There
are several parameters can be set its initial condition,
such as output voltage, operation mode (Auto PSM/PWM
or Forced-PWM) and output voltage bank. Users can set
separately into VSEL high state and VSEL low state to
design the required performance.
EN
0x10.ENSEL1
0x11.ENSEL0
1
MUX2
Enable Control
ENSEL
0
VSEL
0x10.VoutSEL1[6:0]
0x11.VoutSEL0[6:0]
0x14.PWM1
0x14.PWM0
0x1C.VOUT_BANK1[1:0]
1
MUX2
1
MUX2
DVS
VREF Control
Buck
Converter
FPWM
0
PWM
1
MUX2
0x1D.VOUT_BANK0[1:0]
VoutSEL[6:0]
0
Auto
VOUT_BANK
1
MUX2
0
Feedback
Network
0
Mode Control
Feedback
Control
Chosen by VSEL
Figure 3. VSEL Logic
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RT5701
Setting the Output Voltage with Internal Feedback
Network
The Flow Chart from Power-ON to Soft-Start
Besides defined initial output voltages in VSEL high and
VSEL low, the RT5701 can manually change voltage
reference from 0.3V to 0.7V by I2C programming. The
difference among bank0 to bank3 is internal feedback
configuration. Then the output voltage can be designed
as following equation :
To summarize the above functions and judgments such
as VSEL function, internal feedback network selection at
power-on state, following chart shows the actions and
protections to clarify the time sequence and priority.
VOUT = VREF 2 (BANK)
where VREF stand for reference voltage; BANK is 0 to 3,
for bank0 to bank3 separately.
AVDD
Power On
PVIN UVLO
Check
No
No
Power Ready Detection
AVDD >1.6V?
UVLO Protect
PVIN > 2.4V?
Yes
Yes
AVDD Deglitch
Deglitch time ~ 2µs
ENABLE
Logic Check
Vout Selection
VSEL = High?
Yes
No
Output
VOUT = 1.5V
Output
VOUT = 1.0V
No
Internal ENABLE =
High?
Yes
IC Load Initial Value
Settling time ~ 500µs
RT5701
Soft-Start Begin
Soft-Start time ~ 400µs
Figure 4. Flow chart of power-on state
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I2C Interface
The RT5701 default I2C slave address = 7'b0011100. I2C interface support fast mode (bit rate up to 400kb/s). The write
or read bit stream (N ≥ 1) is shown below :
Read N bytes from RT5701
Slave Address
Register Address
S
0
A
R/W
MSB
Slave Address
A Sr
1
A
A
Assume Address = m
MSB
LSB
Data 1
Data for Address = m
Data 2
LSB
MSB
Data N
LSB
A
A
P
Data for Address = m+N-1
Data for Address = m+1
Write N bytes to RT5701
Slave Address
Register Address
S
0
MSB
A
A
Assume Address = m
R/W
Data 1
LSB
MSB
Data 2
LSB
A
A
Data for Address = m
MSB
Data for Address = m+1
Data N
LSB
A P
Driven by Master
Driven by Slave (RT5701)
P Stop
S Start
Data for Address = m+N-1
Sr Repeat Start
SDA
tLOW
tF
tSU;DAT
tR
tF
tHD;STA
tSP
tR
tBUF
SCL
tHD;STA
S
tHD;DAT
tHIGH
tSU;STA
tSU;STO
Sr
P
S
Figure 5. Definition of Timing for Hs-mode Devices on the I2C-bus
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RT5701
I2C Register Map
Register
Address
Register
Address
Meaning
0x01
b[7]
(MSB)
b[6]
b[5]
b[4]
b[3]
b[2]
b[1]
b[0]
(LSB)
SEN_TSD Reserved Reserved Reserved Reserved Reserved Reserved SEN_PG
Default
0
Read/Write
R
x
x
x
x
x
x
0
R
Report junction temperature > thermal shutdown threshold.
SEN_TSD
0 : TJ < 150C
1 : TJ > 150C
Report VOUT Power GOOD or not.
SEN_PG
0 : V OUT < 90% of target.
1 : V OUT is within nominal range.
Register
Address
0x10
Register
Address
b[7]
(MSB)
Meaning
ENSEL1
Default
1
0
0
1
Read/Write
R/W
R/W
R/W
R/W
ENSEL1
b[6]
b[5]
b[4]
b[2]
b[1]
b[0]
(LSB)
0
1
1
1
R/W
R/W
R/W
R/W
b[3]
VoutSEL1[6:0]
When VSEL = High, it is used to gate the EN pin of the step-down converter. This makes
2
the step-down converter can enable/disable by I C and Software.
When EN pin = High and this bit = 1, step-down converter can be enabled. Otherwise,
step-down converter would be disabled.
0 : Disable (even if EN=High, step-down converter still cannot be enabled.)
1 : Enable
VoutSEL1[6:0]
Register
Address
0x11
When VSEL = High, it is used to set Vout voltage level.
Vout voltage level = (303.125mV + 3.125mV x VoutSEL1[6:0]) x 2 ^ (0x1C.VOUT_BANK1
[1:0])
Register
Address
b[7]
(MSB)
Meaning
ENSEL0
Default
1
0
1
1
Read/Write
R/W
R/W
R/W
R/W
ENSEL0
b[6]
b[5]
b[4]
b[2]
b[1]
b[0]
(LSB)
1
1
1
1
R/W
R/W
R/W
R/W
b[3]
VoutSEL0[6:0]
When VSEL = Low, it is used to gate the EN pin of the step-down converter. This makes
2
the step-down converter can enable/disable by I C and Software.
When EN pin = High and this bit = 1, step-down converter can be enabled. Otherwise,
step-down converter would be disabled.
0 : Disable (even if EN=High, step-down converter still cannot be enabled.)
1 : Enable
VoutSEL0[6:0]
When VSEL = Low, it is used to set Vout voltage level.
Vout voltage level = (303.125mV + 3.125mV x VoutSEL0[6:0]) x 2 ^ (0x1D.VOUT_BANK0
[1:0])
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Register
Address
Register
Address
Meaning
0x12
b[7]
(MSB)
b[6]
b[5]
b[4]
b[3]
b[2]
b[1]
b[0]
(LSB)
Reserved Reserved Reserved Discharge Reserved Reserved Reserved Reserved
Default
x
x
x
Read/Write
1
x
x
x
x
R/W
Control the enabling of the LX discharge path when step-down converter is turned off.
0 : Disable discharge path.
Discharge
1 : Enable discharge path.
Note. If there is a standby power at VOUT pin, it is suggest to disable this function.
Register
Address
0x14
Register
Address
b[7]
(MSB)
b[6]
Meaning
PWM0
PWM1
Default
1
1
Read/Write
R/W
R/W
b[5]
b[4]
b[3]
b[2]
b[1]
b[0]
(LSB)
Reserved Reserved Reserved Reserved Reserved Reserved
x
x
x
x
x
x
When VSEL = Low, it is used to control PWM operation mode of step-down converter
PWM0
0 : step-down converter would automatically switch the operation mode among CCM
(forced PWM), DCM, and PSM.
1 : step-down converter works only at the forced PWM.
When VSEL = High, it is used to control PWM operation mode of step-down converter
PWM1
0 : step-down converter would automatically switch the operation mode among CCM
(forced PWM), DCM, and PSM.
1 : step-down converter works only at the forced PWM.
Register
Address
Register
Address
0x16
Meaning
Default
Read/Write
b[7]
(MSB)
b[6]
IPEAK[1:0]
1
1
R/W
b[5]
b[4]
b[3]
b[2]
b[1]
b[0]
(LSB)
Reserved Reserved Reserved Reserved Reserved Reserved
x
x
x
x
x
x
R/W
Set inductor peak current limit.
00 : 4.7A
IPEAK[1:0]
01 : 5.2A
10 : 5.7A
11 : 6.2A
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RT5701
Register
Address
0x18
Register
Address
b[7]
(MSB)
Meaning
OCP
Default
Read/Write
0
R/W
b[6]
b[5]
Reserved Reserved
x
x
b[4]
SCP
b[3]
b[2]
Reserved Reserved
0
R/W
x
b[1]
b[0]
(LSB)
PVIN_
UVLO
Reserved
x
0
R/W
b[2]
b[1]
x
Record the Over-current protection event.
OCP
0 : Over-current protection is not triggered
1 : Over-current protection is triggered
Record the Vout short-circuit protection event.
SCP
0 : Vout short-circuit protection is not triggered
1 : Vout short-circuit protection is triggered
Record the PVIN under voltage event after enabling.
PVIN_UVLO
0 : PVIN UVLO occurs is not triggered
1 : PVIN UVLO occurs is triggered
Register
Address
Register
Address
b[6]
b[5]
b[4]
b[3]
b[0]
(LSB)
Reserve
Reserved Reserved Reserved VOUT_BANK1[1:0]
d
Default
x
x
x
x
x
1
0
Read/Write
R/W
R/W
When VSEL = High. It is used to select the Vout list.
It should be set before enabling the step-down converter.
Meaning
0x1C
b[7]
(MSB)
Reserved
Reserve
d
x
00 : 0.303125V to 0.7V
VOUT_BANK1[1:0]
01 : 0.60625V to 1.4V
10 : 1.2125V to 2.8V
11 : 2.425V to 5.6V
Register
Address
Register
Address
Meaning
0x1D
Default
b[7]
(MSB)
b[6]
b[5]
b[4]
b[3]
b[2]
Reserved Reserved Reserved Reserved Reserved Reserved
x
x
x
x
x
Read/Write
x
b[1]
b[0]
(LSB)
VOUT_BANK0[1:0]
0
1
R/W
R/W
When VSEL = Low. It is used to select the Vout list.
It should be set before enabling the step-down converter.
00 : 0.303125V to 0.7V
VOUT_BANK0[1:0]
01 : 0.60625V to 1.4V
10 : 1.2125V to 2.8V
11 : 2.425V to 5.6V
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Register
Address
Register
Address
b[7]
(MSB)
Meaning
0x1E
b[6]
b[5]
b[4]
b[3]
Vout_High[3:0]
b[2]
b[1]
b[0]
(LSB)
Vout_Low(3:0]
Default
1
1
1
1
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Vout_High[3:0]
To avoid DVS change Vout out of reliable range, set the field to limit the effective upper
bound of Vout voltage level.
When VSEL = Low, if Register 0x11.VoutSEL0[6:0] > {Vout_High[3:0], 3'b111}, effective
Vout would be limited to be the voltage corresponding to the code {Vout_High[3:0],
3'b111}. Else effective Vout would follow Register 0x11.VoutSEL0[6:0] setting. When
VSEL = High, if Register 0x10.VoutSEL1[6:0] > {Vout_High[3:0], 3'b111}, effective Vout
would be limited to be the voltage corresponding to the code {Vout_High[3:0], 3'b111}.
Else effective Vout would follow Register 0x10.VoutSEL1[6:0] setting.
Vout_Low[3:0]
To avoid DVS change Vout out of reliable range, set the field to limit the effective lower
bound of Vout voltage level.
When VSEL = Low, if Register 0x11.VoutSEL0[6:0] < {Vout_Low[3:0], 3'b000}, effective
Vout would be limited to be the voltage corresponding to the code {Vout_Low[3:0],
3'b000}. Else effective Vout would follow Register 0x11.VoutSEL0[6:0] setting.
When VSEL = High, if Register 0x10.VoutSEL1[6:0] < {Vout_Low[3:0], 3'b000}, effective
Vout would be limited to be the voltage corresponding to the code {Vout_Low[3:0],
3'b000}. Else effective Vout would follow Register 0x10.VoutSEL1[6:0] setting.
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RT5701
Thermal Considerations
3.6
Maximum Power Dissipation (W)1
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
TSSOP-14 (Exposed Pad) package, the thermal
resistance, θJA, is 30.1°C/W on a standard JEDEC 51-7
four-layer thermal test board. The maximum power
dissipation at TA = 25°C can be calculated by the following
formula :
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2.8
2.4
2.0
1.6
1.2
0.8
0.4
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 6. Derating Curve of Maximum Power Dissipation
Layout Consideration
For the best performance of the RT5701, the following
PCB layout guidelines must be strictly followed.
Place the input and output capacitors as close as
possible to the input and output pins respectively for
good filtering.
Keep the main power traces as wide and short as
possible.
The switching node area connected to LX and inductor
should be minimized for lower EMI.
Place the feedback components as close as possible
to the VOUT pin and keep these components away from
the noisy devices.
PD(MAX) = (125°C − 25°C) / (30.1°C/W) = 3.32W for
TSSOP-14 (Exposed Pad) package
The maximum power dissipation depends on the operating
ambient temperature for fixed T J(MAX) and thermal
resistance, θJA. The derating curve in Figure 6 allows the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
Four-Layer PCB
3.2
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Connect the Exposed
Pad to a ground plane.
Dedicated sense line.
GND
VSEL
EN
SCL
GNDR
VOUT
CIN2
NC
AVDD
14
2
13
3
4
12
GND
5
6
7
11
10
15
9
8
SDA
GND
LX
LX
NC
PVIN
PVIN
L1
COUT
Keep away
from LX trace
VOUT
CIN1
GND
R3
GND
VBAT
Figure 7. PCB Layout Guide
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RT5701
Outline Dimension
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
1.000
1.200
0.039
0.047
A1
0.000
0.150
0.000
0.006
A2
0.800
1.050
0.031
0.041
b
0.190
0.300
0.007
0.012
D
4.900
5.100
0.193
0.201
e
0.650
0.026
E
6.300
6.500
0.248
0.256
E1
4.300
4.500
0.169
0.177
L
0.450
0.750
0.018
0.030
U
1.900
2.900
0.075
0.114
V
1.600
2.600
0.063
0.102
14-Lead TSSOP (Exposed Pad) Plastic Package
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
www.richtek.com
24
DS5701-00
December 2014
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