RT5735A
5A Step-Down Converter with I2C Interface
General Description
Features
The RT5735A device is a full featured 5.5V, 5A,
synchronous step down constant-on-time (COT)
current mode converter with two integrated MOSFETs.
The RT5735A enables small designs by integrating the
MOSFETs, implementing current mode control to
reduce external component count, reducing inductor
size by enabling up to 2.4MHz switching frequency,
and minimizing the IC footprint with a small
WL-CSP-20B 1.6x2 (BSC) package. The RT5735A
provides accurate regulation for a variety of loads with
an accurate ±1% Voltage Reference (VREF) over
temperature. Efficiency is maximized through the
integrated 34m/18m MOSFETs and 70A typical
quiescent current. Using the enable pin, shutdown
supply current is less than 2A by entering a shutdown
mode.
The output voltage startup ramp is controlled by the
slow start pin. An open-drain power good signal
indicates the output is within 90% to 95% of its nominal
voltage.
Range
Robust Loop Stability with Low-ESR COUT
Over-Temperature Protection
Applications
Distributed Power Systems
Enterprise Servers, Ethernet Switches & Routers,
and Global Storage Equipment
Telecom & Industrial Equipment
Ordering Information
RT5735A
Package Type
WSC : WL-CSP-20B 1.6x2 (BSC)
Note :
Richtek products are :
Marking Information
4AW
2.5V to 5.5V Input Supply Voltage
Current Mode COT Control Loop Design
Fast Transient Response
Internal 34m and 18m Synchronous Rectifier
Highly Accurate VOUT Regulation Over Load/Line
4A : Product Code
W : Date Code
RoHS compliant and compatible with the current
requirements of IPC/JEDEC J-STD-020.
Suitable for use in SnPb or Pb-free soldering processes.
Simplified Application Circuit
RT5735A
VIN
………
C1
C2
PVDD
FB
AVDD
LX
L1
EN
VSEL
SCL
PG/PGND
SDA
VOUT
C3
C4
C5
AGND PGND
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January 2016
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RT5735A
Pin Configurations
(TOP VIEW)
A1
A2
A3
VSEL
EN
SCL
A4
FB
B1
B2
B3
B4
SDA
PGND
C1
C2
C3
C4
AGND
PGND
PGND
PGND
D4
PG/PGND PGND
D1
D2
D3
AVDD
PVDD
LX
LX
E1
E2
E3
E4
PVDD
PVDD
LX
LX
WL-CSP-20B 1.6x2 (BSC)
Functional Pin Description
Pin No.
Pin Name
Pin Function
A1
VSEL
Output Voltage/ Mode Selection. The level determines which of two
programmable, configurations to utilize (operating mode / output voltage).
There is an internal pull down resistor on this pin; could be left open if not used.
A2
EN
Enable Control Input. Active high will enable the part. There is an internal
pull-down resistor on this pin.
A3
SCL
I2C Clock Input.
A4
FB
Output Voltage Pin.
B1
SDA
I2C Data Input.
B3
PG/PGND
Power Good Open-Drain Output. If not used, it has to be connected to ground
plane.
PGND
Power Ground.
AGND
Analog Ground should be electrically connected to GND close to the device.
D1
AVDD
Analog Circuit Input Supply Voltage.
D2, E1, E2
PVDD
Input Supply Voltage, 2.5V to 5.5V.
B2, B4, C2,
C3, C4
C1
D3, D4, E3, E4 LX
Switch Node. The source of the internal high-side power MOSFET, and drain of
the internal low-side (synchronous) rectifier MOSFET.
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RT5735A
Function Block Diagram
EN
PG
AVDD
UVLO
Shutdown
Control
OTP
Ton
Error Amplifier
+
+
VOUT
LX
PVDD
Comparator
+
RC
Driver
Logic Control
LX
-
CCOMP
VREF
Current Limit
Detector
Current
Sense
SDA
PGND
LX
I2C Control
SCL
AZC
LX
AGND
VSEL
Operation
The RT5735A is a synchronous low voltage step-down
converter that can support the input voltage range from
2.5V to 5.5Vand the output current can be up to 5A.
The RT5735A uses a constant on-time, current mode
architecture. In steady-state operation, the high-side
The switching frequency is 2.4MHz allows for efficiency
and size optimization when selecting the output filter
N-MOSFET is turned on when the current feedback
reaches COMP level which is the amplified difference
between the reference voltage and the feedback
voltage. The on time of high-side N-MOSFET is
determined by on-time generator which is a function of
input and output voltage. After on-time expires,
The error amplifier EA adjusts COMP voltage by
comparing the output voltage with the internal I2C set
reference voltage. When the load increases, it causes
a drop in the output voltage relative to the reference,
then the COMP voltage rises to allow higher inductor
current to match the load current.
high-side MOSFET is turned off and low-side MOSFET
is turned on. Until the low-side current sensing signal
reaches the COMP, the high-side MOSFET is turned
on again. In this manner, the converter regulates the
output voltage and keeps the frequency constant.
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DS5735A-00
January 2016
components.
The RT5735A reduces the external component count
by integrating the boot recharge MOSFET.
PWM Frequency and Adaptive On Time Control
The on-time can be roughly estimated by the equation :
Ton = VOUT 1 where FSW is nominal 2.4MHz
VIN
FSW
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RT5735A
Auto-Zero Current Detector
Over-Current Protection (OCP)
The auto-zero current detector circuit senses the LX
waveform to adjust the zero current threshold voltage.
The RT5735A senses the current signal when low-side
MOSFET turns on and uses a valley current limiting
When the current of low-side MOSFET decreases to
the zero current threshold, the low-side MOSFET turns
off to prevent negative inductor current. In this way, the
zero current threshold can adjust for different condition
to get better efficiency.
circuit. As a result, the OCP set point is the OCP DC
limit minus half of the ripple current. The OCP is
cycle-by-cycle limit. If the OCP occurs, the converter
holds off the next on pulse until inductor current drops
below the OCP limit. If the OCP keeps and the load
current is larger than the current provided by the
converter, the output voltage drops. When the output
voltage triggers UVP, the converter enters hiccup
mode.
Protection Features
The RT5735A has many features to protect the device.
Under-Voltage Protection (UVLO)
The UVLO continuously monitors the voltage of AVDD
to make sure the device works properly. When the
AVDD is high enough to reach the high threshold
voltage of UVLO, the step-down converter softly starts
or pre-bias to its regulated output voltage. When the
AVDD decreases to its low threshold (180mV
Soft-Start
hysteresis), the device will shut down.
The RT5735A has over-temperature protection. When
the device triggers the OTP, the device shuts down.
Power Good
An internal current source charges an internal capacitor
to build the soft-start ramp voltage. The typical
soft-start time is 130s.
Over-Temperature Protection (OTP)
When the output voltage is higher than PG rising
threshold, the PG flag is High.
Output Under-Voltage Protection (UVP)
When the output voltage is lower than 400mV after
soft-start end is ok, the UVP is triggered. When UVP
occurs, the device enters hiccup mode.
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RT5735A
Absolute Maximum Ratings
(Note 1)
Supply Input Voltage, VIN -------------------------------------------------------------------------------------0.3V to 6V
Other Pins -------------------------------------------------------------------------------------------------------0.3V to VIN + 0.3V
Power Dissipation, PD @ TA = 25C
WL-CSP-20B 1.6x2 (BSC) ------------------------------------------------------------------------------------1.818W
Package Thermal Resistance
(Note 2)
WL-CSP-20B 1.6x2 (BSC), JA ------------------------------------------------------------------------------55C/W
WL-CSP-20B 1.6x2 (BSC), JC ------------------------------------------------------------------------------7C/W
Lead Temperature (Soldering, 10 sec.) --------------------------------------------------------------------260C
Junction Temperature ------------------------------------------------------------------------------------------150C
Storage Temperature Range ---------------------------------------------------------------------------------65C to 150C
ESD Susceptibility
(Note 3)
HBM (Human Body Model) -----------------------------------------------------------------------------------2kV
Recommended Operating Conditions
(Note 4)
Supply Input Voltage -------------------------------------------------------------------------------------------2.5V to 5.5V
Ambient Temperature Range---------------------------------------------------------------------------------40C to 85C
Junction Temperature Range --------------------------------------------------------------------------------40C to 125C
Electrical Characteristics
(VIN = 3.6V, TA = 25C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Supply Current
Operating Quiescent Current
PWM
IQ_PWM
PWM Mode IQ at IOUT = 0A
(Note 5)
--
10
20
mA
Operating Quiescent Current
PFM
IQ_PFM
PSM Mode IQ at IOUT = 0A
--
70
--
A
Product in Off Mode
IOFF
EN, VSEL Low, VIN = 2.5V to 5.5V
--
1
5
A
2.5
--
5.5
V
1
1
--
1
--
2
2.16
2.4
2.64
DC/DC Converter
Operation Input Voltage
VIN
Output Voltage DC Error
VOUT
Switching Frequency
FSW
RON
PWM Mode
PSM Mode
High-Side
RON_H
VIN = 5V
--
34
--
Low-Side
RON_L
VIN = 5V
--
18
--
Valley Current Limit Level
ILIM,Valley
IOC = 00 Valley Current
(Note 5)
--
4
--
IOC = 01 Valley Current
(Note 5)
--
4.7
--
IOC = 10 Valley Current
(Note 5)
--
5.4
--
5.4
6.4
7.4
IOC = 11 Valley Current
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January 2016
%
MHz
m
A
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RT5735A
Parameter
Symbol
Test Conditions
Typ
Max
Unit
--
0.2
--
%/A
Load Regulation
VLOAD
IOUT from
(Note 5)
Line Regulation
VLINE
2.5V VIN 5.5V
--
0.3
--
%
Transient Load Response
ACLOAD
tr = ts = 0.1s Load Step 0 to 1.2A
(Note 5)
--
±40
--
mV
Time from EN Transition from Low
to High to 90% of Output Voltage
--
70
--
Time from EN Transition from Low
to High to VOUT
--
130
--
Force VOUT = 1.15V, EN = Low
--
16
--
Turn On Time
Tstart
DC/DC Active Output
Discharge
RDISCHG
300mA to IOUTMAX
Min
s
EN. VSEL
Input Voltage
Logic-High
VIH
1.05
--
--
Logic-Low
VIL
--
--
0.4
V
PG
Power Good High Hysteresis
VPGH
Rising Edge as a Percentage of
Nominal Output Voltage
90
94
98
%
Power Good Low Threshold
VPGL
Falling Edge as a Percentage of
Nominal Output Voltage
86
90
94
%
Power Good Reaction Time
for DC/DC
TRT
Falling
--
3.5
--
Rising
3.5
--
14
Power Good Low Output
Voltage
VPGL
IPG = 5mA
--
--
0.2
V
Power Good Leakage Current PGLK
3.6V at PG Pin when Power Good
Valid
--
--
100
nA
Power Good High Output
Voltage
Open-Drain
--
--
5.5
V
V
VPGH
s
I2C
High Level at SCL/SDA Line
VI2CINT
1.7
--
5
Logic-High
SCL, SDA
Input Voltage Logic-Low
VI2CIH
1.7
--
--
VI2CIL
--
--
0.5
SDA Low Output Voltage
VI2COL
ISINK = 3mA
--
--
0.4
V
FSCL
(Note 5)
--
--
3.4
MHz
Under-Voltage Lockout
Threshold
VUVLO
VIN Falling
--
2.15
2.34
V
VIN POR
VPOR
VIN Rising
--
2.3
2.45
V
Thermal Shutdown Protection TSD
(Note 5)
--
150
--
°C
Warning Rising Edge
TWARNING
(Note 5)
--
135
--
°C
Pre-Warning Threshold
TPWTH
For Default Setting
--
105
--
°C
(Note 5)
--
30
--
°C
TWARNING_HYS (Note 5)
--
15
--
°C
2
I C Clock Frequency
V
Total Device
Thermal Shutdown Hysteresis TSDH
Thermal Warning Hysteresis
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(Note 5)
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DS5735A-00
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RT5735A
Parameter
Symbol
Thermal Pre−Warning
Hysteresis
Test Conditions
TPWTH_HYS
Min
Typ
Max
Unit
--
6
--
°C
(Note 5)
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect
device reliability.
Note 2. JA is measured at TA = 25C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. JC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. Guaranteed by design and characterized.
Typical Application Circuit
VIN
………
C1
47μF
D2, E1, E2
C2
4.7μF
RT5735A
PVDD
D1
A2
A1
A3
B1
FB
A4
D3, D4,
E3, E4
AVDD
LX
EN
VSEL
B3
SCL
PG/PGND
SDA
L1
0.47μH
C3
22μF
C4
22μF
C5
22μF
VOUT
AGND PGND
C1
B2, B4, C2, C3,C4
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RT5735A
Typical Operating Characteristics
Efficiency vs. Output Current
Output Voltage vs. Input Voltage
100
1.111
1.109
80
Output Voltage (V)
Efficiency (%)
90
VIN = 3V
VIN = 3.6V
70
VIN = 4.2V
60
1.107
IOUT = 10mA
1.105
IOUT = 0.5A
1.103
IOUT = 3A
1.101
IOUT = 5A
1.099
1.097
1.095
1.093
50
1.091
VOUT = 1.1V, L = 0.47µH, PIFE25201B
40
0.01
0.1
1
VOUT = 1.1V
1.089
10
3
3.5
4
Output Current (A)
4.5
5
5.5
Input Voltage (V)
Output Voltage vs. Temperature
Output Voltage vs. Output Current
1.120
1.111
1.109
1.115
Output Voltage (V)
Output Voltage (V)
1.107
1.110
1.105
1.100
1.095
1.090
1.105
VIN = 2.9V
1.103
VIN = 3.6V
1.101
VIN = 4.2V
1.099
1.097
1.095
1.093
1.085
VIN = 3.6V, IOUT = 10mA, VOUT = 1.1V
1.080
1.091
VOUT = 1.1V
1.089
-50
-25
0
25
50
75
100
125
0
0.5
1
1.5
Temperature (°C)
Frequency vs. Input Voltage
2.5
3
3.5
4
4.5
5
Frequency vs. Temperature
2.64
3.0
2.60
2.9
2.56
2.8
2.52
Frequency (MHz)1
Frequency (MHz)1
2
Output Current (A)
2.48
2.44
2.40
2.36
2.32
2.28
2.7
2.6
2.5
2.4
2.3
2.2
2.24
2.1
2.20
VOUT = 1.1V, IOUT = 1A
2.16
2.5
3
3.5
4
4.5
5
Input Voltage (V)
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VIN = 3.6V, VOUT = 1.1V, IOUT = 1A
2.0
5.5
-50
-25
0
25
50
75
100
125
Temperature (°C)
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RT5735A
Quiescent Current vs. Temperature
100
7.5
90
Quiescent Current (µA)
Inductor Valley Current (A)1
Current Limit vs. Input Voltage
8.0
7.0
6.5
6.0
5.5
5.0
4.5
IOC = 11
IOC = 10
IOC = 01
IOC = 00
4.0
3.5
80
70
60
50
40
30
20
10
VOUT = 1.1V
3.0
IQ, No Switching
0
3
3.5
4
4.5
5
5.5
-50
-25
0
Input Voltage (V)
2.45
1.3
2.40
1.2
Rising
2.30
2.25
2.20
2.15
50
75
100
125
EN Threshold vs. Temperature
1.4
EN Threshold (V)
UVLO Voltage (V)
UVLO Voltage vs. Temperature
2.50
2.35
25
Temperature (°C)
Falling
2.10
1.1
1.0
0.9
0.8
Rising
0.7
Falling
0.6
2.05
VOUT = 1.1V, IOUT = 0A
2.00
-50
-25
0
25
50
75
100
125
0.5
VIN = 3.6V, VOUT = 1.1V, IOUT = 0A
0.4
-50
0
25
50
75
100
Temperature (°C)
Load Transient Response
Load Transient Response
VIN = 3.6V, VOUT = 1.1V,
IOUT = 10mA to 5A, L = 0.47H, COUT = 22F x 3
125
VIN = 3.6V, VOUT = 1.1V,
IOUT = 2.5A to 5A, L = 0.47H, COUT = 22F x 3
VOUT
(50mV/Div)
VOUT
(50mV/Div)
IOUT
(2A/Div)
IOUT
(2A/Div)
Time (50μs/Div)
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Temperature (°C)
January 2016
Time (50μs/Div)
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RT5735A
Output Ripple Voltage
Output Ripple Voltage
VOUT
(10mV/Div)
VOUT
(10mV/Div)
VLX
(2V/Div)
VLX
(2V/Div)
VIN = 3.6V, VOUT = 1.1V, IOUT = 10mA, L = 0.47H
VIN = 3.6V, VOUT = 1.1V, IOUT = 5A, L = 0.47H
Time (10μs/Div)
Time (500ns/Div)
Power On from EN
Power Off from EN
VEN
VEN
(2V/Div)
(2V/Div)
(4V/Div)
VLX
VLX
(4V/Div)
VOUT
(1V/Div)
VOUT
(1V/Div)
IOUT
(5A/Div)
IOUT
(5A/Div)
VIN = 3.6V, VOUT = 1.1V, IOUT = 5A
Time (50μs/Div)
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VIN = 3.6V, VOUT = 1.1V, IOUT = 5A
Time (50μs/Div)
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RT5735A
Application Information
The basic RT5735A application circuit is shown in
Typical Application Circuit. External component
selection is determined by the maximum load current
and begins with the selection of the inductor value and
operating frequency followed by CIN and COUT.
Inductor Selection
The inductor value and operating frequency determine
the ripple current according to a specific input and
output voltage. The ripple current, IL, increases with
higher VIN and decreases with higher inductance, as
shown in equation below :
V
V
IL OUT 1 OUT
f
L
V
IN
where f is the operating frequency and L is the
inductance. Having a lower ripple current reduces not
only the ESR losses in the output capacitors, but also
the output voltage ripple. Higher operating frequency
combined with smaller ripple current is necessary to
achieve high efficiency. Thus, a large inductor is
required to attain this goal. The largest ripple current
occurs at the highest VIN. A reasonable starting point for
selecting the ripple current is IL = 0.3 × IMAX to
0.4×IMAX. To guarantee that the ripple current stays
below a specified maximum, the inductor value should
be chosen according to the following equation :
VOUT
VOUT
L
1
f IL(MAX) VIN(MAX)
The inductor's current rating (defined by a temperature
rise from 25C ambient to 40°C) should be greater than
the maximum load current and its saturation current
should be greater than the short-circuit peak current
limit.
Input and Output Capacitor Selection
An input capacitor, CIN, is needed to filter out the
trapezoidal current at the source of the high-side
MOSFET. To prevent large ripple current, a low ESR
input capacitor sized for the maximum RMS current
should be used. The RMS current is given by :
IRMS IOUT(MAX)
VOUT
VIN
VIN
1
VOUT
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This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT(MAX) / 2. This simple worst-case condition is
commonly used for design. Choose a capacitor rated at
a higher temperature than required. Several capacitors
may also be paralleled to meet the size or height
requirements of the design. Ceramic capacitors have
high ripple current, high voltage rating and low ESR,
which makes them ideal for switching regulator
applications. However, they can also have a high
voltage coefficient and audible piezoelectric effects. The
high Q of ceramic capacitors with trace inductance can
lead to significant ringing. When a ceramic capacitor is
used at the input and the power is supplied by a wall
adapter through long wires, a load step at the output
can induce ringing at the input, VIN. At best, this ringing
can couple to the output and be mistaken as loop
instability. At worst, a sudden inrush of current through
the long wires can potentially cause a voltage spike at
VIN large enough to damage the part. Thus, care must
be taken to select a suitable input capacitor.
The selection of COUT is determined by the required
ESR to minimize output voltage ripple. Moreover, the
amount of bulk capacitance is also a key for COUT
selection to ensure that the control loop is stable. Loop
stability can be checked by viewing the load transient
response. The output voltage ripple, VOUT, is
determined by :
1
VOUT IL ESR
8fOSC COUT
where f OSC is the switching frequency and IL is the
inductor ripple current. The output voltage ripple will be
the highest at the maximum input voltage since ΔIL
increases with input voltage. Multiple capacitors placed
in parallel may be needed to meet the ESR and RMS
current handling requirement. Ceramic capacitors have
excellent low ESR characteristics, but can have a high
voltage coefficient and audible piezoelectric effects. The
high Q of ceramic capacitors with trace inductance can
also lead to significant ringing. Nevertheless, high value,
low cost ceramic capacitors are now becoming
available in smaller case sizes. Their high ripple current,
high voltage rating and low ESR make them ideal for
switching regulator applications.
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RT5735A
I2C Interface Function
2
RT5735A can be used by I C interface to select VOUT
voltage level, over current limit level, thermal warning
temperature level, PWM control mode, and so on. The
register of each function can be found from the following
register map and it also explains how to use these
function.
VOUT Selection : RT5735A has external VSEL pin to
select PROGVSEL1(0X10) or PROGVSEL0(0X11)
which can control VOUT from 0.6V to 1393.75mV with
7bits resolution. Pull VSEL to high is for PROGVSEL1
and pull VSEL to low is for PROGVSEL0. If VSELGT bit
in the COMMAND register is set to 0, VOUT will only be
controlled by PROGVSEL1.
Discharge Function : In the PGOOD register DISCHG
bit is set to 1 can let VOUT discharge by internal resistor
when converter shuts down. If setting to 0 VOUT will
decrease depending on the loading.
Power Good Function : In the PGOOD register
PGDCDC bit can control if external PG pin is active.
After PG function is active if PGDVS pin is 0, PG will not
change state during VOUT changing. Once PGDVS pin
is 1 PG will be low when VOUT is much lower than VREF
during VOUT changing.
Force PWM Mode : In the COMMAND register
PWMSEL0 and PWMSEL1 can decide converter is
always at PWM mode or enters power saving mode at
light load condition. During output voltage is changed
from high to low at light load, setting DVSMODE bit to 1
will make transition operate at PWM mode and output
voltage will decrease quickly. If setting to 0, the output
voltage will decrease depending on the loading.
Over Current Level : RT5735A has four levels of over
current limit to be selected. Using IOC bits in the
LIMCONF register can change different inductor valley
current limit level.
Thermal Shutdown Protection : The default REARM
bit in the LIMCONF register is 1. RT5735A will shut
down switching operation when the junction
temperature exceeds 150 ° C. Once the junction
temperature cools down by approximately 30°C the IC
will resume normal operation with a complete soft-start.
When REARM bit is set to 0, once the device triggers
the OTP, the system will be latched and the output
voltage will no longer be regulated during OTP latched
state. Re-start input voltage or EN pin can unlatch the
protection state. Using I2C to shutdown the system and
then re-enable it will also unlatch UVP function.
Slew Rate Setting : RT5735A can control slew rate as
VOUT changing between two voltage levels for both up
and down. In the time register DVS_UP bits can control
up-speed when in the LIMCONF register DVS_DOWN
can control down-speed. DVS_DOWN is valid only
when converter is at PWM mode or DVSMODE bit is 1.
Copyright © 2016 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS5735A-00
January 2016
RT5735A
The RT5735A default I2C slave address = 7'b0011100. I2C interface support fast mode (bit rate up to 400kb/s). The
write or read bit stream (N≥1) is shown below :
Read N bytes from RT5735A
Slave Address
Register Address
S
0
Slave Address
A
MSB
A Sr
1
MSB
A
Data for Address = m
Data 2
LSB
MSB
Data N
LSB
A
A
Register Address
S
0
MSB
A
Data 1
LSB
A
Assume Address = m
R/W
P
Data for Address = m + N - 1
Data for Address = m + 1
Write N bytes to RT5735A
Slave Address
LSB
A
Assume Address = m
R/W
Data 1
MSB
Data 2
LSB
A
A
Data for Address = m
MSB
Data for Address = m + 1
Data N
LSB
A P
Data for Address = m + N - 1
Driven by Master,
Driven by Slave (RT5735A), P Stop,
S Start,
Sr Repeat Start
SDA
tLOW
tF
tSU,DAT
tR
tF
tSP
tHD,STA
tR
tBUF
SCL
tHD,STA
tHD,DAT
S
tSU,STA
tHIGH
tSU,STO
P
Sr
S
Figure 1. I2C Read and Write Stream and Timing Diagram
RT5735A can also support High-speed mode(bit rate
up to 3.4Mb/s) with access code 08H. Figure 2 and
START condition (S)
Figure 3 show detail transfer format. Hs-mode can only
commence after the following conditions (all of which
not-acknowledge bit ( A )
8-bit master code (00001xxx)
are in F/S-mode) :
F/S-Mode
Hs-Mode (current-source for SCLH enabled
F/S-Mode
A/A
S
Master Code
A
Sr
Slave ADD.
A
R/W
Data
N bytes + ack.
P
Hs-Mode
Continues
Sr Slave ADD.
Figure 2. Data Transfer Format in Hs-mode
Copyright © 2016 Richtek Technology Corporation. All rights reserved.
DS5735A-00
January 2016
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13
RT5735A
8-bit Master code 00001xxx
t1
A
tH
S
SDAH
1
SCLH
2 to 5
6
7
8
9
F/S-Mode
7-bit SLA
R/W
A
8
9
N x (8-bit data + A/A
Sr
Sr P
SDAH
SCLH
1
2 to 5
6
7
1
2 to 5
6
7
8
9
If P then F/S mode
Hs-Mode
If Sr (dotted lines) then Hs-mode
tH
tFS
Figure 3. A Complete Hs-mode Transfer
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is a registered trademark of Richtek Technology Corporation.
DS5735A-00
January 2016
RT5735A
Address
Register
Name
Address
Bit7
Bit6
Bit5
Meaning
PRODUCT
_ID
0x03
_ID
0x04
_ID
0x05
PROGVSEL1 0x10
PROGVSEL0 0x11
0x12
0
0
0
1
0
0
0
0
R
R
R
R
R
R
R
REVISION_ID
Default
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
FEATURE_ID
Default
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
VENDER_ID
Default
1
0
0
0
1
0
0
0
Read/Write
R
R
R
R
R
R
R
R
Meaning
ENVSEL1
Default
0
1
0
1
0
0
0
0
Read/Write
RW
RW
RW
RW
RW
RW
RW
RW
Meaning
ENVSEL0
Default
0
0
0
1
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PGDVS
PGDCDC
Vout_VSEL1[6:0]
Vout_VSEL0[6:0]
RESV
0x13
COMMAND 0x14
0x16
0
0
0
0
0
0
0
0
R
R
R
R/W
R
R
R/W
R/W
RESV
DVS_UP[2:0]
RESV
Default
0
0
0
1
1
0
0
1
Read/Write
R
R
R
R/W
R/W
R/W
R
R
Meaning
PWMSEL0
PWMSEL1
DVSMODE
Default
0
0
0
0
0
0
0
1
Read/Write
R/W
R/W
R/W
R
R
R
R
R/W
IOC
RESV
TPWTH
RESV
VSELGT
DVS_DOWN
REARM
Default
0
1
1
0
0
0
1
1
Read/Write
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
Copyright © 2016 Richtek Technology Corporation. All rights reserved.
DS5735A-00
RESV
Default
Meaning
LIMCONF
DISCHG
Read/Write
Meaning
TIME
Bit0
R
Meaning
PGOOD
Bit1
Default
Meaning
VENDER ID 0x06
Bit2
Read/Write
Meaning
FEATURE
Bit3
PRODUCT_ID
Meaning
REVISION
Bit4
January 2016
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15
RT5735A
Register
Name
Register
Address
b[7]
(MSB)
b[6]
b[5]
Meaning
PRODUCT
0x03
_ID
0
1
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
b[5]
b[4]
b[3]
b[2]
b[1]
b[0]
(LSB)
Register
Address
PRODUCT_ID
b[7]
(MSB)
b[6]
REVISION_ID
Default
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
b[5]
b[4]
b[3]
b[2]
b[1]
b[0]
(LSB)
Register
Address
REVISION_ID
b[7]
(MSB)
b[6]
Meaning
FEATURE_
0x05
ID
FEATURE_ID
Default
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
b[5]
b[4]
b[3]
b[2]
b[1]
b[0]
(LSB)
FEATURE_ID
Register
Address
FEATURE_ID
b[7]
(MSB)
b[6]
Meaning
VENDER
0x06
ID
RESV
Default
1
0
0
0
1
0
0
0
Read/Write
R
R
R
R
R
R
R
R
b[6]
b[5]
b[4]
b[3]
b[2]
b[1]
b[0]
(LSB)
VENDER ID
Register
Address
VENDER ID
b[7]
(MSB)
Meaning
ENVSEL1
Default
0
1
0
1
0
0
0
0
Read/Write
RW
RW
RW
RW
RW
RW
RW
RW
PROGVSE
0x10
L1
ENVSEL1
Vout_VSEL1[6:0]
Vout_VSEL1[6:0]
EN Pin Gating for VSEL internal signal = High
0 : Disabled
1 : Enabled
VID Table satisfy :
SEL[6:0] = 1111111 : VOUT = 1393.75mV
…
SEL[6:0] = 1010000: VOUT = 1.1V (default)
…
SEL[6:0] = 0000000 :0.6V
6.25mV step for DCDC, VOUT = 600mV + 6.25mV x SEL
Copyright © 2016 Richtek Technology Corporation. All rights reserved.
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16
b[0]
(LSB)
0
REVISION_ID
Register
Name
b[1]
PRODUCT_ID
Meaning
Register
Name
b[2]
0
REVISION
0x04
_ID
Register
Name
b[3]
Default
PRODUCT_ID
Register
Name
b[4]
is a registered trademark of Richtek Technology Corporation.
DS5735A-00
January 2016
RT5735A
Register
Name
Register
Address
b[7]
(MSB)
b[6]
b[5]
b[4]
Meaning ENVSEL0
PROGVSE
0x11
L0
Vout_VSEL0[6:0]
0
1
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
b[1]
b[0]
(LSB)
EN Pin Gating for VSEL internal signal= Low
0 : Disabled
1 : Enabled
VID Table satisfy :
SEL[6:0] = 1111111 : VOUT = 1393.75mV
…
SEL[6:0] = 0010000 : VOUT = 0.7V (default)
…
SEL[6:0] = 0000000 : 0.6V
6.25mV step for DCDC, VOUT = 600mV + 6.25mV x SEL
b[7]
(MSB)
Meaning
PGOOD 0x12
b[6]
b[5]
RESV
b[4]
b[3]
DISCHG
b[2]
RESV
PGDVS PGDCDC
Default
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R/W
R
R
R/W
R/W
b[4]
b[3]
b[2]
b[1]
b[0]
(LSB)
RESV
Reserved bits
Active discharge bit enabling
0 : Discharge path disabled
1 : Discharge path enabled
DISCHG
RESV
Reserved bits
Power good active on DVS
0 : Disabled
1 : Enabled
PGDVS
Power good enabling
0 : Disabled
1 : Enabled
PGDCDC
Register
Address
b[7]
(MSB)
Meaning
0x13
b[6]
b[5]
Reserved
DVS_UP[2:0]
Reserved
Default
0
0
0
1
1
0
0
1
Read/Write
R
R
R
R/W
R/W
R/W
R
R
RESV
DVS_UP[2:0]
RESV
Reserved bits
DVS slew rate for up
000 : 64mV/S
001 : 16mV/S
010 : 32mV/S
011 : 8mV/S
100 : 4mV/S
101 : 4mV/S
110 : 32mV/S
111 : 8mV/S
Reserved bits
Copyright © 2016 Richtek Technology Corporation. All rights reserved.
DS5735A-00
b[0]
(LSB)
0
Register
Address
TIME
b[1]
0
Vout_VSEL0[6:0]
Register
Name
b[2]
Default
ENVSEL0
Register
Name
b[3]
January 2016
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17
RT5735A
Register
Name
Register
Address
b[7]
(MSB)
b[6]
b[5]
b[4]
b[3]
Meaning PWMSEL0 PWMSEL1 DVSMODE
COMMAN
0x14
D
b[0]
(LSB)
VSELGT
Default
0
0
0
0
0
0
0
1
Read/Write
R/W
R/W
R/W
R
R
R
R
R/W
b[1]
b[0]
(LSB)
Operation mode for VSEL internal signal = Low
0 : Auto
1 : Forced PWM
PWMSEL1
Operation mode for VSEL internal signal = High
0 : Auto
1 : Forced PWM
DVSMODE
DVS transition mode selection
0 : Auto
1 : Forced PWM
RESV
Reserved bits
VSEL Pin gating
0 : Disabled
1 : Enabled
VSELGT
Register
Address
b[7]
(MSB)
Meaning
LIMCONF 0x16
b[6]
IOC
b[5]
b[4]
TPWTH
b[3]
RESV
b[2]
DVS_DOWN
REARM
Default
0
1
1
0
0
0
1
1
Read/Write
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
IOC[1:0]
TPWTH[1:0]
RESV
DVS_DOWN[1:0]
REARM
Inductor valley current settings
00 = 4A (typ.)
01 = 4.7A (typ.)
10 = 5.4A (typ.)
11 = 6.4A (typ.)
Thermal pre-warning threshold settings
00 = 83C
01 = 94C
10 = 105C
11 = 116C
Reserved bits
DVS slew rate for down
00 = 32mV/s
01 = 4mV/s
10 = 8mV/s
11 = 16mV/s
Recovery of device after TSD
0 : No Recovery after TSD
1 : Recovery after TSD
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18
b[1]
RESV
PWMSEL0
Register
Name
b[2]
is a registered trademark of Richtek Technology Corporation.
DS5735A-00
January 2016
RT5735A
Thermal Considerations
Layout Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
For best performance of the RT5735A, the following
layout guidelines must be strictly followed.
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature.
The maximum power dissipation can be calculated by
the following formula :
Input capacitor must be placed as close to the IC as
possible.
SW should be connected to inductor by wide and
short trace. Keep sensitive components away from
PD(MAX) = (TJ(MAX) TA) / JA
this trace.
where TJ(MAX) is the maximum junction temperature, TA
is the ambient temperature, and JA is the junction to
ambient thermal resistance.
Keep every trace connected to pin as wide as
possible for improving thermal dissipation.
For recommended operating condition specifications,
the maximum junction temperature is 125C. The
junction to ambient thermal resistance, JA, is layout
dependent. For WL-CSP-20B 1.6x2 (BSC) package, the
thermal resistance, JA, is 55C/W on a standard
JEDEC 51-7 four-layer thermal test board. The
maximum power dissipation at TA = 25C can be
calculated by the following formula :
PD(MAX) = (125C 25C) / (55C/W) = 1.8W for
WL-CSP-20B 1.6x2 (BSC) package
The maximum power dissipation depends on the
operating ambient temperature for fixed TJ(MAX) and
thermal resistance, JA. The derating curve in Figure 4
allows the designer to see the effect of rising ambient
temperature on the maximum power dissipation.
Maximum Power Dissipation (W)1
2.5
Four-Layer PCB
2.0
1.5
1.0
0.5
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 4. Derating Curve of Maximum Power
Dissipation
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January 2016
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19
RT5735A
Top layer
2nd layer
AGND and PGND connect
together at negative of Cin
to reduce noise.
Vias can help to reduce power trace and improve
thermal dissipation. PGND pins connect top layer
and 2nd layer directly for thermal dissipation.
FB
A4
SDA
B1
PGND
B2
PG/P
GND
B3
PGND
B4
AGND
C1
PGND
C2
PGND
C3
PGND
C4
AVDD
D1
PVDD
D2
LX
D3
LX
D4
PVDD
E1
PVDD
E2
LX
E3
LX
E4
GND
1608 Cout
22µF
SCL
A3
1608 Cout
22µF
EN
A2
1608 Cout
22µF
1608 Cin
4.7µF
VSEL
A1
Vout connects to FB
pin from 2nd layer.
WL-CSP-20B 1.6X2 (BSC)
2520 L
0.47µH
Vout connects to FB
pin from 2nd layer
VIN
VOUT
Input capacitor must be placed as close
to the IC as possible. Suggest layout
trace wider for thermal dissipation .
SW should be connected to inductor by wide and short
trace. Keep sensitive components away from this trace.
Suggest layout trace wider for thermal dissipation .
Figure 5. PCB Layout Guide
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is a registered trademark of Richtek Technology Corporation.
DS5735A-00
January 2016
RT5735A
Outline Dimension
Symbol
Dimensions In Millimeters
Dimensions In Inches
Min.
Max.
Min.
Max.
A
0.500
0.600
0.020
0.024
A1
0.170
0.230
0.007
0.009
b
0.240
0.300
0.009
0.012
D
1.950
2.050
0.077
0.081
D1
E
1.600
1.550
0.063
1.650
0.061
0.065
E1
1.200
0.047
e
0.400
0.016
20B WL-CSP 1.6x2 Package (BSC)
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume
responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable.
However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
Copyright © 2016 Richtek Technology Corporation. All rights reserved.
DS5735A-00
January 2016
is a registered trademark of Richtek Technology Corporation.
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