RT6543BGQW

® RT6543A/B High Efficiency Single Synchronous Buck PWM Controller for INTEL VCCIN AUX ICL and TGL General Description Features The RT6543A/B PWM controller provides high efficiency, excellent transient response, and high DC output accuracy for stepping down high voltage batteries to generate low voltage CPU core, I/O, and chipset RAM.      The RT6543A/B supports on chip voltage programming function between 0V and 1.8V by controlling VID1/VID0 inputs.   Compared with conventional current-mode PWMs, the RT6543A/B achieves high efficiency without any current sensing resistors. Furthermore, the RT6543A/B has ability to drive synchronous rectifier MOSFETs and enters diode emulation mode at light load condition that also save lots of power consumption. Besides, the RT6543A/B equips with UVLO, OVP, UVP, OTP and current limit protection. All above functions are integrated in a WQFN-20L-3x3 package.       A High Efficiency Step-Down DC-DC Controller Built-in 1% Reference Voltage 2-Bit Programmable Output Voltage with Integrated Adjustable Switching Frequency Input Voltage Range : 3V to 24V Internal Soft-Start to Reduce Inrush Current Capability of Driving Large Synchronous Rectifier MOSFETs Power Good Indicator Cycle-by-Cycle Current Limit Over-/Under-Voltage Protection Thermal Shutdown RT6543A : Slew Down Mode as VID Change RT6543B : Decay Down Mode as VID Change Pin Configuration VSYS EN VID0 VID1 VCC (TOP VIEW) Applications    CS_DIS ISENSEP ISENSEN PGOOD COMP 1 15 2 14 3 AGND 4 21 5 13 12 11 6 7 8 PVCC PGND LGATE PH UGATE 9 10 FB RGND VOUT FSWSEL BOOT  20 19 18 17 16 Notebook Computers CPU/GPU Core Supply Chipset/RAM Supply Generic DC-DC Power Regulator WQFN-20L 3x3 Simplified Application Circuit RT6543A/B VSYS PVCC VCC VEN VID0 VID1 VSYS PVCC VCC PGOOD FSWSEL EN CS_DIS VID0 VID1 PGND AGND Copyright © 2022 Richtek Technology Corporation. All rights reserved. DS6543A/B-04 March 2022 BOOT LGATE BUCK VOUT PH UGATE ISENSEP ISENSEN VOUT FB COMP RGND is a registered trademark of Richtek Technology Corporation. www.richtek.com 1 RT6543A/B Ordering Information Marking Information RT6543A/B RT6543AGQW Package Type QW : WQFN-20L 3x3 (W-Type) Lead Plating System G : Green (Halogen Free and Pb Free) Mode when VID changes to lower set point A : Slew down B : Decay down ML=YM DNN YMDNN : Date Code RT6543BGQW P7= : Product Code Note : Richtek products are :  ML= : Product Code RoHS compliant and compatible with the current require- P7=YM DNN YMDNN : Date Code ments of IPC/JEDEC J-STD-020.  Suitable for use in SnPb or Pb-free soldering processes. Functional Pin Description Pin No. Pin Name Pin Function 1 CS_DIS Current limit setting. Connect a resistor from CS pin to AGND for overcurrent protection. CS pin sources a CS current which is 6A (typ) at TA = 25oC to define maximum allowable output current. CS terminal voltage VCS is limited from 0.5V to 2.8V over all operation temperature. 2 ISENSEP Positive input pin for current sense of buck.(for load line setting, in zero load line condition is short this pin with ISENSEN) 3 ISENSEN Negative input pin for current sense of buck.(for load line setting, in zero load line condition is short this pin with ISENSEP) 4 PGOOD 5 6 7 8 COMP FB RGND VOUT Power good indicator output for VCCIN_AUX. This open-drain is pulled low as UVP, OVP, OTP, EN low and output voltage is not regulated (such as before soft-start). An external pull-up resistor to VCC or other external rail is required, in which the pull-up resistor is recommended from 10k to 100k. Internal error amplifier output. For loop compensator application. Internal error amplifier input. For loop compensator application. Return ground for VCCIN_AUX from CPU side. VCCIN_AUX feedback input. This pin is unit feedback for AUX regulation FSWSEL VCCIN_AUX setting pin. Use this pin to adjust AUX rail frequency setting for different LC combination. (High state: Direct pull high to VCC, Hi-Z state: Floating, Low state: Direct connect to GND). Default switching frequency is floating, 600kHz. Anytime, make sure FSWSEL  VCC < 0.5V. 10 BOOT Supply bootstrap capacitor output pin. The bootstrap capacitor is charged by this pin while the low-side MOSFET is turned on. Therefore, the bootstrap capacitor can provide the energy to turn on the high-side MOSFET. Connect this pin through the bootstrap capacitor to the PH pin. 11 UGATE Upper gate driver with sink and source output. Connect to the gate of the high-side MOSFET through a short and low inductance path. 12 PH Switch node of AUX. Connect to the power inductor. For the high-side gate driver return path, connect a capacitor from PH to BOOT. Beside, this pin is noisy, keep the sensitive trace or signal away from PH. 9 Copyright © 2022 Richtek Technology Corporation. All rights reserved. www.richtek.com 2 is a registered trademark of Richtek Technology Corporation. DS6543A/B-04 March 2022 RT6543A/B Pin No. Pin Name Pin Function 13 LGATE Low-side gate driver output pin. Connect this pin to the gate of low-side MOSFET. Notice, DO NOT connect the resistor RG_EXT between LGATE and gate terminal of low-side MOSFET, otherwise it might cause undesired shoot-through since the LGATE voltage is monitored for shoot-through protection. 14 PGND Power GND. AGND and PGND are connected with a short trace and at only one point to reduce circulating currents. PVCC Bias voltage for internal gate driver. The required bias voltage for PVCC is 5V typ. For avoiding noise disturbance, the supplied bias voltage must be stable, Beside, a RC filter (R = 2.2/0603 and C = 1F/0603) from bias voltage to PVCC pin is necessary which should be placed as close as physically possible to PVCC pin. 16 VCC Bias voltage for control logic. The required bias voltage for VCC is 5V typ. For avoiding noise disturbance, the supplied bias voltage must be stable, Beside, a RC filter (R = 2.2/0603 and C = 1F/0603) from bias voltage to VCC pin is necessary which should be placed as close as physically possible to VCC pin. 17 VID1 VCCIN_AUX VID control signal. Adjust AUX output voltage (0V, 1.1V, 1.65V and 1.8V) 18 VID0 VCCIN_AUX VID control signal. Adjust AUX output voltage (0V, 1.1V, 1.65V and 1.8V) 19 EN Enable control input. As voltage is lower than 0.3V, RT6543A/B is in shutdown mode and all power rails are disabled. As RT6543A/B is higher than 1V, RT6543A/B is woken up. 20 VSYS System voltage sense. Connect this pin to input voltage for UVLO monitor and controller’s on-time setting. For avoiding any noise to disturb on-time setting, a RC filter (R = 2.2/0603 and C = 0.1F/0603) is required from input voltage to VSYS. 21 (Exposed pad) GND Exposed pad for package. Electrically isolated. Directly solder to the large PGND plane and use thermal vias to connect PGND of other layers for thermal resistor reduction 15 Copyright © 2022 Richtek Technology Corporation. All rights reserved. DS6543A/B-04 March 2022 is a registered trademark of Richtek Technology Corporation. www.richtek.com 3 RT6543A/B Functional Block Diagram VID0 VID1 To driver Logic To Power on Reset Reference Output Gen. Enable Logic EN RGND VCC VOUT OV 2.2V UV 60% VREF PGOOD VREF 90% VREF Soft-Start & Slew Rate Control ISENSEP ISENSEN FB Droop + - Power On Reset &Central Logic + - Control & Protection Logic PGOOD PVCC + - VREF_ DROOP + - EA TON Gen. + PWM CMP VIN Detection AGND PWM Driver Logic Zero Current Detction COMP VSYS FSWSEL BOOT UGATE PH HIZ To Power on Reset Current Limit Frequency Lock and Selection LGATE PGND + + 6µA CS_DIS X(-1/12) Operation The RT6543A/B is a constant on-time synchronous stepdown controller. In normal operation, the high-side NMOSFET is turned on when the output voltage is lower than VREF, and is turned off after the internal one-shot timer expires. While the high-side N-MOSFET is turned off, the low-side N-MOSFET is turned on to conduct the inductor current until next cycle begins. Current Limit Soft-Start (SS) Over-Voltage Protection (OVP) & Under-Voltage Protection (UVP) For internal soft-start function, an internal current source charges an internal capacitor to build the soft-start ramp voltage. The output voltage will track the internal ramp voltage during soft-start interval. PGOOD The power good output is an open-drain architecture. When the soft-start is finished, the PGOOD open-drain output will be high impedance. Copyright © 2022 Richtek Technology Corporation. All rights reserved. www.richtek.com 4 The current limit circuit employs a unique “valley” current sensing algorithm. If the magnitude of the current sense signal at PHASE is above the current limit threshold, the PWM is not allowed to initiate a new cycle. The current limit threshold can be set with an external voltage setting resistor on the CS_DIS pin. The output voltage is continuously monitored for overvoltage and under-voltage protection. When the output voltage exceeds 2.2V (Typ.), UGATE goes low and LGATE is forced high. When the feedback voltage is less than 60% of output voltage, under-voltage protection is triggered and then both UGATE and LGATE gate drivers are forced low. The controller is latched until VCC is re-supplied and exceeds the POR rising threshold voltage or EN is reset. is a registered trademark of Richtek Technology Corporation. DS6543A/B-04 March 2022 RT6543A/B Absolute Maximum Ratings                (Note 1) VSYS to PGND ---------------------------------------------------------------------------------------------------------VCC to PGND ----------------------------------------------------------------------------------------------------------RGND to PGND --------------------------------------------------------------------------------------------------------BOOT to PH ------------------------------------------------------------------------------------------------------------DC --------------------------------------------------------------------------------------------------------------------------