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RT7243
6A, 18V, Synchronous Step-Down Converter
General Description
Features
The RT7243 is a high efficiency, monolithic synchronous
step-down DC/DC converter that can deliver up to 6A output
current from a 4.5V to 18V input supply. The RT7243
current-mode architecture with external compensation
allows the transient response to be optimized over a wide
range of loads and output capacitors. Cycle-by-cycle
current limit provides protection against shorted outputs
and soft-start eliminates input current surge during startup. Fault condition protections include output under-voltage
protection, output over-voltage protection, and overtemperature protection. The low current shutdown mode
provides output disconnection, enabling easy power
management in battery-powered systems.
Ω/19mΩ
Ω
Low RDS(ON) Power MOSFET Switches 26mΩ
Input Voltage Range : 4.5V to 18V
Adjustable Switching Frequency : 200kHz to 1.6MHz
Current-Mode Control
Synchronous to External Clock : 200kHz to 1.6MHz
Accurate Voltage Reference 0.8V ± 1.25%
Monotonic Start-Up into Pre-biased Outputs
Adjustable Soft-Start
Power Good Indicator
Under-Voltage and Over-Voltage Protection
Input Under-Voltage Lockout
RoHS Compliant and Halogen Free
Applications
Marking Information
02=YM
DNN
02= : Product Code
YMDNN : Date Code
High Performance Point of Load Regulation
Notebook Computers
High Density and Distributed Power Systems
Simplified Application Circuit
VIN
VIN
RT7243
BOOT
CIN
CBOOT
PVIN
Enable
L
LX
R1
EN
PGOOD
PGOOD
ROSC
RT/SYNC
FB
SS/TR
Copyright © 2019 Richtek Technology Corporation. All rights reserved.
June 2019
COUT
RCOMP1
COMP
CCOMP2
CSS
DS7243-06
VOUT
CCOMP1
R2
GND
is a registered trademark of Richtek Technology Corporation.
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1
RT7243
Ordering Information
Pin Configurations
Lead Plating System
G : Green (Halogen Free and Pb Free)
RoHS compliant and compatible with the current require-
13
3
12
GND
4
11
5
10
15
6
ments of IPC/JEDEC J-STD-020.
14
Suitable for use in SnPb or Pb-free soldering processes.
7
8
COMP
Richtek products are :
1
2
FB
Note :
GND
GND
PVIN
PVIN
VIN
PGOOD
Package Type
QW : WQFN-14AL 3.5x3.5 (W-Type)
RT/SYNC
(TOP VIEW)
RT7243
9
BOOT
LX
LX
EN
SS/TR
WQFN-14AL 3.5x3.5
Functional Pin Description
Pin No.
1
Pin Name
RT/SYNC
2, 3,
GND
15 (Exposed Pad)
4, 5
Pin Function
Oscillator Resistor and External Frequency Synchronization Input. Connecting a
resistor from this pin to GND sets the switching frequency or connecting an
external clock to this pin changes the switching frequency.
System Ground. Provide the ground return path for the control circuitry and
low-side power MOSFET. The exposed pad must be soldered to a large PCB
and connected to GND for minimum power dissipation.
PVIN
Power Input. Supplies the power switches of the device.
6
VIN
Supply Voltage Input. Supplies the control circuitry and internal reference of the
device.
7
FB
Feedback Voltage Input. This pin is used to set the desired output voltage via an
external resistive divider. The feedback reference voltage is 0.8V typically.
8
COMP
Compensation Node. The current comparator threshold increases with this
control voltage. Connect external compensation elements to this pin to stabilize
the control loop.
9
SS/TR
Soft-Start and Tracking Control Input. Connect a capacitor from SS to GND to
set the soft-start period. The soft-start period can be used to track and sequence
when the external voltage on this pin overrides the internal reference.
10
EN
Enable Control Input. Floating this pin or connecting this pin to logic high can
enable the device and connecting this pin to GND can disable the device.
11, 12
LX
Switch Node. LX is the switching node that supplies power to the output and
connect the output LC filter from LX to the output load.
13
BOOT
Bootstrap Supply for High-Side Gate Driver. Connect a 100nF or greater
capacitor from LX to BOOT to power the high-side switch.
14
PGOOD
Power Good Indicator Output. This pin is an open-drain logic output that is pulled
to ground when the output voltage is lower or higher than its specified threshold
under the conditions of OVP, OTP, dropout, EN shutdown, or during slow start.
Copyright © 2019 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS7243-06
June 2019
RT7243
Function Block Diagram
PGOOD EN
VIN
UV
Comparator
Ihys
IP
91% VREF
Thermal
Detector
UVLO
PGOOD
Logic
109% VREF
Regulator
Shutdown
Logic
VEN = 1.21V
OV
Comparator
Slope
Compensation
High-Side
Current Sense
ISS
SS/TR
FB
VREF
PVIN
+
+
-
Power Stage
Control
Logic,
Driver, and
Boot UVLO
Current
Comparator
Voltage
Reference
Oscillator with
RT/SYNC
Function
COMP
Shutdown
Low-Side
Current Sense
BOOT
LX
GND
RT/SYNC
Operation
UV Comparator
Error Amplifier
If the feedback voltage (VFB) is lower than threshold voltage
(91% of VREF), the UV Comparator's output goes high
and the logic control circuit is allowed to turn on the
MOSFET to pull PGOOD pin to low.
The device uses a transconductance error amplifier. The
error amplifier compares the FB pin voltage with the SS/
TR pin voltage and the internal reference voltage which is
0.8V. The transconductance of the error amplifier is
1300μA/V during normal operation. The compensation
network should be connected between the COMP pin and
ground.
OV Comparator
If the feedback voltage (VFB) is higher than threshold voltage
(109% of VREF), the OV Comparator's output goes high
and the logic control circuit is allowed to turn on the
MOSFET to pull PGOOD pin to low.
Voltage Reference
The converter produces a precise ±1% voltage reference
over-temperature by scaling the output of a temperature
stable bandgap circuit.
Copyright © 2019 Richtek Technology Corporation. All rights reserved.
DS7243-06
June 2019
Oscillator with RT/SYNC function
The switching frequency is adjustable by an external
resistor connected between the RT/SYNC pin and GND.
The available frequency range is from 200kHz to 1.6MHz.
An internal synchronized circuit has been implemented
to switch from RT mode to SYNC mode. To implement
the synchronization function, connect a square wave clock
signal to the RT/SYNC pin with a duty cycle between
10% to 90%. The switching cycle is synchronized to the
falling edge of the external clock at RT/SYNC pin.
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RT7243
Absolute Maximum Ratings
(Note 1)
Supply Input Voltage, VIN, PVIN -------------------------------------------------------------------------Switch Node Voltage, LX -----------------------------------------------------------------------------------LX (t ≤ 10ns) --------------------------------------------------------------------------------------------------BOOT Pin Voltage -------------------------------------------------------------------------------------------Other Pins -----------------------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C
WQFN-14AL 3.5x3.5 ---------------------------------------------------------------------------------------Package Thermal Resistance (Note 2)
WQFN-14AL 3.5x3.5, θJA ----------------------------------------------------------------------------------WQFN-14AL 3.5x3.5, θJC ---------------------------------------------------------------------------------Junction Temperature ---------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -----------------------------------------------------------------Storage Temperature Range ------------------------------------------------------------------------------ESD Susceptibility (Note 3)
HBM (Human Body Model) ---------------------------------------------------------------------------------
Recommended Operating Conditions
−0.3V to 20V
−1V to 20.3V
−5V to (VIN + 6.3V)
−0.3V to (VIN + 6.3V)
−0.3V to 6V
2.083W
48°C/W
3.8°C/W
150°C
260°C
−65°C to 150°C
2kV
(Note 4)
Power Input Voltage, PVIN --------------------------------------------------------------------------------Supply Input Voltage, VIN ---------------------------------------------------------------------------------Junction Temperature Range ------------------------------------------------------------------------------Ambient Temperature Range -------------------------------------------------------------------------------
1.6V to 18V
4.5V to 18V
−40°C to 125°C
−40°C to 85°C
Electrical Characteristics
(VIN = PVIN = 12V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Supply Voltage
PVIN Power Input
Operating Voltage
PVIN
1.6
--
18
VIN Supply Input
Operating Voltage
VIN
4.5
--
18
Under-Voltage Lockout
Threshold
VUVLO
--
4
4.5
Under-Voltage Lockout
Threshold Hysteresis
VUVLO
--
150
--
VIN Rising
VIN Shutdown Current
VEN = 0V
--
3
9
VIN Quiescent Current
VFB = 0.83V, Not Switching
--
600
1000
VIH
VEN Rising
--
1.21
--
VIL
VEN Falling
--
1.17
--
Pull-Up Current
VEN = 1.1V
--
1
--
Hysteresis Current
VEN = 1.3V
--
3
--
V
mV
A
Enable Voltage
EN Threshold Voltage
Copyright © 2019 Richtek Technology Corporation. All rights reserved.
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V
A
is a registered trademark of Richtek Technology Corporation.
DS7243-06
June 2019
RT7243
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
0A ILOAD 6A
0.79
0.8
0.81
V
ROSC = 27k
1440
1600
1760
ROSC = 110k
400
480
560
ROSC = 270k
160
200
240
Include Sync mode and RT
mode set point
200
--
1600
--
20
--
High-Level
--
--
2
Low-Level
0.8
--
--
Measure at 500kHz with ROSC
resistor in series
--
66
--
Reference Voltage
Reference Voltage
VREF
Timing Resistor and External Clock
Switching Frequency
fOSC
Switching Frequency Range
Minimum Sync Pulse Width
SYNC Threshold Voltage
SYNC Falling Edge to LX
Rising Edge Delay
kHz
ns
V
ns
Internal MOSFET
High-Side On-Resistance
RDS(ON)_H
VBOOT VLX = 5.5V
--
26
--
Low-Side On-Resistance
RDS(ON)_L
VIN = 12V
--
19
--
Minimum On-Time
Measured at 90% to 90% of VLX,
ILX = 2A
--
--
135
Minimum Off-Time
VBOOT VLX 3V
--
0
--
--
--
3
V
--
2
--
A
--
20
60
mV
High-Side Switch Current
Limit
8
11
--
Low-Side Switch Sourcing
Current Limit
7
10
--
Low-Side Switch Sinking
Current Limit
--
2.3
--
--
1300
--
A/V
--
3100
--
V/V
--
110
--
A
--
16
--
A/V
VFB Rising (Good)
--
94
--
VFB Rising (Fault)
--
109
--
m
LX and BOOT
BOOTLX UVLO
VBL-UVLO
ns
Soft-Start and Tracking
Internal Charge Current
SS to Feedback Offset
VSS = 0.4V
Current Limit
A
Error Amplifier
Error Amplifier
Trans-conductance
Error Amplifier DC Gain
Error Amplifier Sink/Source
Current
gm
2A < ICOMP < 2A,
VCOMP = 1V
VFB = 0.8V
VCOMP = 1V, 100mV input
overdrive
COMP to Iswitch gm
Power Good
Power Good Rising
Threshold
Copyright © 2019 Richtek Technology Corporation. All rights reserved.
DS7243-06
June 2019
%VREF
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RT7243
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Power Good Falling
Threshold
V FB Falling (Fault)
--
91
--
V FB Falling (Good)
--
106
-
Power Good Sink Current
Capability
PGOOD signal fault, IPGOOD sinks
2mA
--
--
0.3
V
Power Good Leakage
Current
PGOOD signal good, V PGOOD = 5.5V
--
30
100
nA
Minimum VIN for Indicating
PGOOD
V PGOOD 0.5V, IPGOOD sinks 100A
--
0.6
1
--
--
2.6
160
175
--
--
10
--
%VREF
V
Minimum SS/TR Voltage for
Indicating PGOOD
Over-Temperature Protection
Thermal Shutdown
T SD
Thermal Shutdown
Hysteresis
TSD
°C
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Copyright © 2019 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS7243-06
June 2019
RT7243
Typical Application Circuit
RT7243
VIN
4.5V to 18V
6
BOOT
VIN
13
CIN
4, 5
10
Enable
PVIN
ROSC
100k
CSS
10nF
1
L
VOUT
R1
EN
FB
14 PGOOD
PGOOD
LX
CBOOT
0.1µF
11, 12
COMP
7
R2
CCOMP1
CCOMP2
RT/SYNC
9 SS/TR
COUT
RCOMP1
8
GND
2, 3,
15 (Exposed Pad)
Table 1. Suggested Component Values
VOUT (V)
R1 (k)
R2 (k)
RCOMP1
(k)
CCOMP1
(nF)
CCOMP2
(pF)
COUT (F)
L (H)
5.0
126
24
4.3
8.2
180
22 x 2
4.7
3.3
75
24
2.4
8.2
180
22 x 2
3.7
2.5
51
24
1.8
8.2
180
22 x 2
3.7
1.8
30
24
1.5
8.2
180
22 x 2
2.2
1.5
21
24
1.0
8.2
180
22 x 2
2.2
1.2
12
24
0.82
8.2
180
22 x 2
2.2
1.0
6
24
0.68
8.2
180
22 x 2
1.5
Copyright © 2019 Richtek Technology Corporation. All rights reserved.
DS7243-06
June 2019
is a registered trademark of Richtek Technology Corporation.
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RT7243
Typical Operating Characteristics
Efficiency vs. Output Current
Efficiency vs. Output Current
100
100
90
90
VIN = 9V
VIN = 12V
VIN = 17V
70
80
Efficiency (%)
Efficiency (%)
80
60
50
40
30
20
VOUT = 5V
VOUT = 3.3V
VOUT = 1.2V
70
60
50
40
30
20
10
10
VOUT = 3.3V
0
VIN = 12V
0
0
1
2
3
4
5
6
0
1
2
Output Current (A)
Output Voltage vs. Output Current
4
5
3.37
3.32
3.35
3.31
3.30
3.29
3.28
3.27
3.33
3.31
3.29
IOUT = 0A
IOUT = 3A
IOUT = 6A
3.27
3.25
VIN = 12V, VOUT = 3.3V
VOUT = 3.3V
3.26
3.23
0
1
2
3
4
5
6
4
6
8
Output Current (A)
10
12
14
16
18
Input Voltage (V)
Reference Voltage vs. Temperature
Switching Frequency vs. Temperature
0.95
700
Switching Frequency (kHz)1
Reference Voltage (V)
6
Output Voltage vs. Input Voltage
3.33
Output Voltage (V)
Output Voltage (V)
3
Output Current (A)
0.90
0.85
0.80
0.75
0.70
650
600
550
500
450
400
ROSC = 100kΩ
0.65
350
-50
-25
0
25
50
75
100
Temperature (°C)
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125
-50
-25
0
25
50
75
100
125
Temperature (°C)
is a registered trademark of Richtek Technology Corporation.
DS7243-06
June 2019
RT7243
Shutdown Current vs. Temperature
18
4.8
15
Shutdown Current (µA)1
Shutdown Current (µA)1
Shutdown Current vs. Input Voltage
5.1
4.5
4.2
3.9
3.6
3.3
12
9
6
3
VEN = 0V
VEN = 0V
3.0
0
4
6
8
10
12
14
16
-50
18
-25
0
Input Voltage (V)
50
75
1000
1000
Quiescent Current (µA)
1100
900
800
700
600
500
900
800
700
600
500
VFB = 0.83V
VFB = 0.83V
400
400
4
6
8
10
12
14
16
18
-50
-25
0
Input Voltage (V)
25
50
75
100
125
Temperature (°C)
Current Limit vs. Input Voltage
Current Limit vs. Temperature
20
20
17
17
Current Limit (A)
Current Limit (A)
125
Quiescent Current vs. Temperature
1100
14
11
8
5
14
11
8
5
2
2
4
6
8
10
12
14
16
Input Voltage (V)
Copyright © 2019 Richtek Technology Corporation. All rights reserved.
DS7243-06
100
Temperature (°C)
Quiescent Current vs. Input Voltage
Quiescent Current (µA)
25
June 2019
18
-50
-25
0
25
50
75
100
125
Temperature (°C)
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RT7243
Input Voltage vs. Temperature
EN Voltage vs. Temperature
1.35
4.5
1.30
Rising
EN Voltage (V)
Input Voltage (V)
4.4
4.3
4.2
Falling
4.1
Rising
1.25
1.20
Falling
1.15
1.10
4.0
VEN = 3.3V
VIN = 3.3V
1.05
3.9
-50
-25
0
25
50
75
100
25
50
75
100
Load Transient Response
Load Transient Response
125
VOUT
(1V/Div)
VIN = 12V, VOUT = 3.3V, IOUT = 0 to 6A
IOUT
(2A/Div)
VIN = 12V, VOUT = 3.3V, IOUT = 1A to 6A
Time (100μs/Div)
Time (100μs/Div)
Load Transient Response
Load Transient Response
VOUT
(500mV/Div)
VIN = 12V, VOUT = 3.3V, IOUT = 0 to 3A
Time (100μs/Div)
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0
Temperature (°C)
VOUT
(500mV/Div)
IOUT
(1A/Div)
-25
Temperature (°C)
VOUT
(1V/Div)
IOUT
(2A/Div)
-50
125
IOUT
(2A/Div)
VIN = 12V, VOUT = 3.3V, IOUT = 3 to 6A
Time (100μs/Div)
is a registered trademark of Richtek Technology Corporation.
DS7243-06
June 2019
RT7243
Voltage Ripple
Voltage Ripple
VIN
(20mV/Div)
VIN
(500mV/Div)
VOUT
(10mV/Div)
VOUT
(10mV/Div)
VLX
(20V/Div)
VLX
(20V/Div)
VIN = 12V, VOUT = 3.3V, IOUT = 0A
VIN = 12V, VOUT = 3.3V, IOUT = 6A
Time (1μs/Div)
Time (1μs/Div)
Power On from VIN
Power Off from VIN
VIN
(20V/Div)
VIN
(20V/Div)
VPGOOD
(5V/Div)
VPGOOD
(5V/Div)
VOUT
(2V/Div)
VOUT
(2V/Div)
IOUT
(5A/Div)
IOUT
(5A/Div)
VIN = 12V, VOUT = 3.3V, IOUT = 6A
Time (2.5ms/Div)
Time (10ms/Div)
Power On from EN
Power Off from EN
VEN
(5V/Div)
VEN
(5V/Div)
VPGOOD
(5V/Div)
VPGOOD
(5V/Div)
VOUT
(2V/Div)
VOUT
(2V/Div)
IOUT
(5A/Div)
VIN = 12V, VOUT = 3.3V, IOUT = 6A
Time (2.5ms/Div)
Copyright © 2019 Richtek Technology Corporation. All rights reserved.
DS7243-06
June 2019
VIN = 12V, VOUT = 3.3V, IOUT = 6A
IOUT
(5A/Div)
VIN = 12V, VOUT = 3.3V, IOUT = 6A
Time (2.5ms/Div)
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RT7243
Application Information
This IC is a single phase Buck PWM converter with two
integrated N-MOSFETs. It provides good performance
during load and line transients by implementing a single
feedback loop, current-mode control, and external
compensation. The integrated synchronous power
switches can increase efficiency and it is suitable for lower
duty cycle applications. The switching frequency can be
externally set from 200kHz to 1.6MHz which allows for
high efficiency and optimal size selection of output filter
components. In additional, there is a synchronization
mode control in this device which can be synchronized to
the external clock frequency, and easily switched from
internal switching mode to synchronization mode.
The device contains a power good protection and an
external soft-start function that is able to monitor the
system output voltage for normal regulation and provides
a programmable power up sequence for avoiding inrush
currents efficiently. Furthermore, the device incorporates
a lot of protections such as OVP, OCP, OTP and etc.
Main Control Loop
The device implements an adjustable fixed frequency with
peak current-mode control which offers an excellent
performance over various line and loading. During normal
operation, the internal high-side power switch is turned
on by the internal oscillator initiating. Current in the
inductor increases until the high-side switch current reaches
the current reference converted by the output voltage VCOMP
of the error amplifier. The error amplifier adjusts its output
voltage by comparing the feedback signal from a resistive
voltage divider on the FB pin with an internal 0.8V
reference. When the load current increases, it causes a
reduction in the feedback voltage relative to the reference.
The error amplifier increases its current reference until
the average inductor current matches the new load current.
When the high-side power MOSFET turns off, the lowside synchronous power switch (N-MOSFET) turns on
until the beginning of the next clock cycle.
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VIN and PVIN Pins
The VIN and PVIN pins can be used together or separately
for a variety of applications. In this device, the VIN pin is
an input for supplying internal reference and control
circuitry and the PVIN pin is an input for providing main
power to device system and internal high-side power
MOSFET. When the VIN and PVIN pins are tied together,
both pins can operate from 4.5V to 18V. When the VIN
and PVIN pins are used separately, VIN pin must be ranged
from 4.5V to 18V, and the PVIN pin can be applied down
to as low as 1.6V to 18V.
The device incorporates an internal Under-Voltage Lockout
(UVLO) circuitry on the VIN pin. If the VIN pin voltage
exceeds the UVLO rising threshold voltage 4V, the
converter resets and prepares the PWM for operation. If
the VIN pin voltage falls below the falling threshold voltage
3.85V during normal operation, the device is disabled.
Such wide internal UVLO hysteresis of 150mV can
efficiently prevent noise caused reset. There is also an
external UVLO circuitry which can be achieved by
configuring a resistive voltage divider on EN pin for both
input VIN and PVIN pins and it is able to provide either
input pins an adjustable UVLO function to ensure a proper
power up behavior. More discussions are located in the
section of Enable Operation.
Output Voltage Setting
The resistive voltage divider allows the FB pin to sense
the output voltage as shown in Figure 1.
VOUT
R1
FB
RT7243
R2
GND
Figure 1. Setting the Output Voltage
is a registered trademark of Richtek Technology Corporation.
DS7243-06
June 2019
RT7243
For high efficiency, the divider resistance must adopt larger
values, but too large values may induce noises and voltage
errors by the coupled FB pin input current. It is
recommended to use the values between 10kΩ and
100kΩ. The output voltage is set by an external resistive
voltage divider according to the following Equation (1) :
VOUT = VREF 1 R1
(1)
R2
where VREF is the feedback reference voltage (0.8V typ.).
Soft-Start
The device contains an external soft-start clamp that
gradually raises the output voltage. The soft-start timing
is programmed by the external capacitor between SS/TR
pin and GND. The device provides an internal 2μA charge
current for the external capacitor. If a 10nF capacitor is
used to set the soft-start, the period can be 4ms. The
calculations for external charge capacitor CSS and softstart time TSS are shown in Equation (2) :
TSS =
CSS VREF
ISS
Once the input voltage falls below UVLO threshold, the
EN pin is pulled low, or the OTP is triggered, the device
stops switching and the SS/TR pin starts to discharge. It
is held such shutdown condition until the event is cleared
and the SS/TR pin has already discharged to ground
ensuring proper soft-start behavior.
During the pre-biased start-up sequence, the output of
device is not discharged by low-side power switch
because the device is designed to prevent low-side
MOSFET sinking. It is allowed to sink when the SS/TR
pin exceeds 2.1V.
Slope Compensation
Slope compensation provides stability in constant
frequency architectures by preventing sub-harmonic
oscillations at duty cycles greater than 50%. It is
accomplished internally by adding a compensating ramp
to the inductor current signal. Normally, the peak inductor
current is remained constant under the whole duty cycle
range when slope compensation is added. For the device,
DS7243-06
June 2019
Enable Operation
The EN pin is an device enable input. Pulling the EN pin
to logic low that is typically less than the set threshold
voltage 1.17V, the device shuts down and enters to low
quiescent current state about 2μA. The regulator starts
switching again once the EN pin voltage exceeds the
threshold voltage 1.21V. In additional, the EN pin is
implemented with an internal pull-up current source which
allows to enable the device when the EN pin is floating.
For general external timing control, the EN pin can be
externally pulled high by adding a capacitor and a resistor
from the VIN pin as Figure 2.
VIN
(2)
where CSS is the external soft-start capacitor, ISS is the
soft-start charge current (2μA), VREF is the feedback
reference voltage (0.8V).
Copyright © 2019 Richtek Technology Corporation. All rights reserved.
separated inductor current signal is used to monitor overcurrent condition, so the maximum output current stays
relatively constant regardless of duty cycle. More
discussions about over-current protection are described
in a later section.
VIN
REN
RT7243
EN
CEN
GND
Figure 2. Enable Timing Control
An external MOSFET can be added to implement digital
control from the EN pin to ground, as shown in Figure 3.
In this case, there is no need to connect a pull-up resistor
between the VIN and EN pins since the EN pin is pulled
up by the internal current source. The device can simply
achieve the digital control only through an external
MOSFET on EN pin.
VIN
External
Digital Control
VIN
RT7243
EN
GND
Figure 3. Digital Enable Control
The EN pin can also be applied to adjust its Under-Voltage
Lockout (UVLO) threshold with two external resistors
divider from the both input VIN and PVIN pins used together
or separately, and the application structures can refer to
Figure 4, Figure 5, and Figure 6.
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RT7243
Separated
Supply
PVIN
REN1
RT7243
EN
REN2
GND
Figure 4. Resistor Divider for PVIN UVLO Setting
Separated
Supply
VIN
REN1
RT7243
EN
REN2
GND
Figure 5. Resistor Divider for VIN UVLO Setting,
VIN ≥ 4.5V
Combined
Supply
PVIN
VIN
REN1
RT7243
EN
Adjustable Operating Frequency-RT mode
Selection of the operating frequency is a tradeoff between
efficiency and component size. Higher operating frequency
allows the use of smaller inductor and capacitor values
but it may press the minimum controllable on-time to affect
devices stability. Lower operating frequency improves
efficiency by reducing internal gate charge and switching
losses but requires larger inductance and capacitance to
maintain low output ripple voltage.
The operating frequency of the device is determined by
an external resistor ROSC, that is connected between the
RT/SYNC pin and ground. The value of the resistor sets
the ramp current which is used to charge and discharge
an internal timing capacitor within the oscillator. The
practical switching frequency ranges from 200kHz to
1.6MHz. Determine the ROSC resistor value by examining
the curve in Figure 7.
1600
REN2
Figure 6. Resistor Divider for PVIN and VIN UVLO
Setting
Under above application structures, the adjustable UVLO
function of EN pin allows to achieve a secondary UVLO
on PVIN pin, a higher UVLO on VIN pin or even a common
UVLO on both VIN and PVIN pins. For example, if the EN
pin is configured as Figure 5 and the output voltage is set
to a higher value 10V. The device may shut down after
soft-start sequence is over, and the reason for the result
is that the VOUT is still lower than its set target during the
VIN rising period even though VIN has already risen to its
internal UVLO threshold 4V. To prevent this situation, an
adjustable UVLO threshold from EN pin is useful to avoid
such high output transfer condition. The exact UVLO
thresholds can be calculated by Equation (3). The setting
VOUT is 10V and VIN is from 0V to 18V. When VIN is higher
than 12V, the device is triggered to enable the converter.
Assume REN1 = 56kΩ. Then,
R
V
REN2 = EN1 IH
(3)
VIN_S VIH
where VIH is the typical threshold of enable rising (1.21V)
and VIN_S is the target turn on input voltage (12V in this
example). According to the equation, the suggested
resistor REN2 is 6.28kΩ.
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14
Switching Frequency (kHz)1
GND
1400
1200
1000
800
600
400
200
0
50
100
150
200
250
300
ROSC (k Ω )
Figure 7. Switching Frequency vs. ROSC Resistor
Synchronization-SYNC Mode
The device is allowed to synchronize with an external
square wave clock ranging from 200kHz to 1.6MHz applied
to the RT/SYNC pin. The range of sync duty cycle must
be from 20% to 80%, and the amplitude of sync signal
must be higher than 2V and lower than 0.8V. During the
SYNC mode operation, the switching cycle of LX pin is
synchronized to the falling edge of the external sync
signal.
is a registered trademark of Richtek Technology Corporation.
DS7243-06
June 2019
RT7243
Before the external sync signal is provided to the RT/
SYNC pin, the device operates at the original switching
frequency set by resistor ROSC. When the sync signal is
provided, the SYNC mode overrides the RT mode to force
the device synchronizing to external frequency. This IC
can easily switch between RT mode and SYNC mode,
and the application structure can be configured as Figure
8.
BOOT
RT7243
1µF
SW
Figure 9. External Bootstrap Diode
Inductor Selection
External
Sync Signal
RT/SYNC
ROSC
RT7243
GND
Figure 8. External Sync Signal Control
Power Good Output
The power good output is an open-drain output and needs
to connect a voltage source below 5.5V with a pull-up
resistor for avoiding the PGOOD floating. When the output
voltage is 9% above or 9% below its set voltage, PGOOD
is pulled low. It is held low until the output voltage returns
within the allowed tolerances ±6% once more. During softstart, PGOOD is actively held low when VIN is greater
than 1V and is only allowed to be high when soft-start
period is over that means the SS/TR pin exceeds 2.1V
typically and the output voltage reaches 94% of its set
voltage. Besides, the PGOOD pin is also pulled low when
the input UVLO or OVP are triggered, EN pin is pulled
below 1.21V or the OTP is occurred.
External Bootstrap Diode
Connect a 100nF low ESR ceramic capacitor between
the BOOT and SW pins. This capacitor provides the gate
driver voltage for the high-side MOSFET.
It is recommended to add an external bootstrap diode
between an external 5V and the BOOT pin for efficiency
improvement when input voltage is lower than 5.5V or duty
ratio is higher than 65% .The bootstrap diode can be a
low cost one such as IN4148 or BAT54. The external 5V
can be a 5V fixed input from system or a 5V output of the
RT7243. Note that the external boot voltage must be lower
than 5.5V.
Copyright © 2019 Richtek Technology Corporation. All rights reserved.
DS7243-06
5V
June 2019
For a given input and output voltage, the inductor value
and operating frequency determine the ripple current. The
ripple current ΔIL increases with higher VIN and decreases
with higher inductance.
V
V
IL = OUT 1 OUT
(4)
VIN
f L
Having a lower ripple current reduces not only the ESR
losses in the output capacitors but also the output voltage
ripple. Highest efficiency operation is achieved by reducing
ripple current at low frequency, but it requires a large
inductor to attain this goal.
For the ripple current selection, the value of ΔIL = 0.24
(IMAX) is a reasonable starting point. The largest ripple
current occurs at the highest VIN. To guarantee that the
ripple current stays below a specified maximum, the
inductor value should be chosen according to the following
equation :
VOUT
VOUT
L =
(5)
1
f IL(MAX) VIN(MAX)
In this device, 3.7μH is recommended for initial design.
The current rating of the inductor (caused a 40°C
temperature rising from 25°C ambient) must be greater
than the maximum load current and ensure that the peak
current does not saturate the inductor during short-circuit
condition. Referring the Table 1 for the inductor selection
reference.
Table 1. Suggested Inductors for Typical
Application Circuit
Component
Supplier
Series
Dimensions (mm)
TDK
TDK
TAIYO YUDEN
WE
WE
VLF10045
SLF12565
NR8040
744325
744355
10 x 9.7 x 4.5
12.5 x 12.5 x 6.5
8x8x4
10.2 x 10.2 x 4.7
12.8 x 12.8 x 6.2
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RT7243
Input and Output Capacitors Selection
The input capacitance CIN is needed to filter the trapezoidal
current at the Source of the high-side MOSFET. To prevent
large ripple current, a low ESR input capacitor sized for
the maximum RMS current should be used. The RMS
current is given by Equation (6) :
V
IRMS = IOUT(MAX) OUT
VIN
VIN
1
VOUT
(6)
The formula above has a maximum at VIN = 2VOUT, where
IRMS = IOUT / 2. This simple worst condition is commonly
used for design because even significant deviations do
not offer much relief.
Choose a capacitor rated at a higher temperature than
required. Several capacitors may also be paralleled to
meet size or height requirements in the design. For the
input capacitor, Two 10μF and one 4.7μF low ESR ceramic
capacitors are recommended for bypassing the PVIN pin
and VIN pin respectively and an additional 0.1μF is
recommended to place as close as possible to the IC
input side for high frequency filtering. All the recommended
input and output capacitors can refer to Table 2 for more
detail.
Table 2. Suggested Capacitors for CIN and COUT
Location
Component Supplier
Part No.
Capacitance (F)
Case Size
CIN
MURATA
GRM32ER71C226M
22
1210
CIN
TDK
C3225X5R1C226M
22
1210
COUT
MURATA
GRM31CR60J476M
47
1206
COUT
TDK
C3225X5R0J476M
47
1210
COUT
MURATA
GRM32ER71C226M
22
1210
COUT
TDK
C3225X5R1C226M
22
1210
The selection of COUT is determined by the required ESR
to minimize voltage ripple. Moreover, the amount of bulk
capacitance is also a key for COUT selection to ensure
that the control loop is stable. Loop stability can be
checked by viewing the load transient response. The
output ripple ΔVOUT is determined by Equation (7) :
1
VOUT IL ESR
8fCOUT
(7)
Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However, care must
be taken when these capacitors are used at input and
output. When a ceramic capacitor is used at the input
and the power is supplied by a wall adapter through long
wires, a load step at the output can induce ringing at the
input VIN. At best, this ringing can couple to the output
and be mistaken as loop instability. At worst, a sudden
inrush of current through the long wires can potentially
cause a voltage spike at VIN large enough to damage the
part.
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16
Output Under-Voltage Protection
For the device, a hiccup mode of Under-Voltage Protection
(UVP) is incorporated. When the power supply output is
shorted to ground and the voltage of FB pin drops below
half of the internal reference voltage, the hiccup mode
protection is triggered to force the device to stop switching
for a period of time. During the shutdown period, the SS/
TR pin is discharged and it is allowed to recover switching
via soft-start sequence when the SS/TR pin has discharged
to ground. Such periodically re-start condition remains
until the UVP condition is removed and then the device
backs into normal operation. The hiccup mode of UVP
can reduce input average current to avoid the thermal issue
in short-circuit conditions efficiently.
Besides, while the FB pin drops, switching frequency is
proportional to the feedback voltage, this is a level
frequency reduced function which is implemented in the
device. For the same short-circuit example, when the
output voltage drops during over-current condition, the
switching frequency is reduced in direct proportion to the
is a registered trademark of Richtek Technology Corporation.
DS7243-06
June 2019
RT7243
output voltage, so the low-side MOSFET is turned off long
enough to reduce the inductor current to prevent a current
runaway issue. With function of level frequency reducing,
the switching frequency can reduce from 100%, 50%, then
25% as the voltage decreases from 0.8V to 0V on FB pin.
The principle of level frequency reducing is also allowed
to cover the soft-start sequence to increase the switching
frequency as feedback voltage increases from 0V to 0.8V.
Output Over-Voltage Protection
The device provides an output Over-Voltage Protection
(OVP) once the output voltage exceeds 109% of VOUT,
the OVP function turns off the high-side power MOSFET
to stop current flowing to the output which can only be
released when the output voltage drops below 106% of
VOUT. There is a 5μs delay also built into the over-voltage
protection circuit to prevent false transition. Using this
OVP feature can easily minimize the output overshoot.
High-Side MOSFET Over-Current Protection
The Over-Current Protection (OCP) of high-side MOSFET
is implemented in this device, it adopts monitoring inductor
current during the on-state to control the COMP pin voltage
for turning off the high-side MOSFET. Each cycle the
separated inductor current signal is compared through
sensing the external inductor current to the COMP pin
voltage from an error amplifier output. If the separated
inductor current peak value exceeds the set current limit
threshold, the high-side power switch is turned off.
Low-Side MOSFET Over-Current Protection
The device not only implements the high-side over-current
protection but also provides the over sourcing current
protection and over sinking current protection for low-side
MOSFET. With these three current protections, the IC
can easily control inductor current at both side power
switches and avoid current runaway for short-circuit
condition.
For the sourcing current protection, there is a specific
comparator in internal circuitry to compare the low-side
MOSFET sourcing current to the internal set current limit
at the end of every clock cycle. When the low-side
sourcing current is higher than the set sourcing limit, the
high-side power switch is not turned on and low-side power
Copyright © 2019 Richtek Technology Corporation. All rights reserved.
DS7243-06
June 2019
switch is kept on until the following clock cycle for releasing
the above sourcing current to the load. It is allowed to
turn on the high-side MOSFET again when the low-side
current is lower than the set sourcing current limit at the
beginning of a new cycle.
For the sinking current protection, it is implemented by
detecting the voltage across the low-side power switch. If
the low-side reverse current exceeds the set sinking limit,
both power switches are off immediately, and it is held to
stop switching until the beginning of next cycle. By
incorporating this additional protection, the device is able
to prevent an excessive sinking current from the load during
the condition of pre-biased output and the SS/TR pin is
asserted high that is 2.1V or above.
Over-Temperature Protection
An Over-Temperature Protection (OTP) is contained in the
device. The protection is triggered to force the device
shutdown for protecting itself when the junction
temperature exceeds 175°C typically. Once the junction
temperature drops below the hysteresis 10°C typically,
the device is re-enable and automatically reinstates the
power up sequence.
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
WQFN-14AL 3.5x3.5 package, the thermal resistance, θJA,
is 48°C/W on a standard JEDEC 51-7 four-layer thermal
test board. The maximum power dissipation at TA = 25°C
can be calculated by the following formula :
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RT7243
PD(MAX) = (125°C − 25°C) / (48°C/W) = 2.083W for
WQFN-14AL 3.5x3.5 package
Layout Considerations
Follow the PCB layout guidelines for optimal performance
of the device.
The maximum power dissipation depends on the operating
ambient temperature for fixed T J(MAX) and thermal
resistance, θJA. The derating curve in Figure 10 allows
the designer to see the effect of rising ambient temperature
on the maximum power dissipation.
Maximum Power Dissipation (W)1
2.5
Four-Layer PCB
Keep the traces of the main current paths as short and
wide as possible.
Put the input capacitor as close as possible to VIN and
PVIN pins.
LX node is with high frequency voltage swing and should
be kept at small area. Keep analog components away
from the LX node to prevent stray capacitive noise pickup.
Connect feedback network behind the output capacitors.
Keep the loop area small. Place the feedback
components near the device.
Connect all analog grounds to a common node and then
connect the common node to the power ground behind
the output capacitors.
An example of PCB layout guide is shown in Figure 11
for reference.
2.0
1.5
1.0
0.5
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 10. Derating Curve of Maximum Power
Dissipation
Place the input and output capacitors
as close to the IC as possible.
PGOOD
1
14
2
13
3
12
GND
4
11
5
10
15
6
CVIN
CBOOT
L
COUT
VOUT
LX should be connected
to inductor by wide and
short trace, and keep
sensitive components
away from this trace.
8
FB
7
9
BOOT
LX
LX
EN
SS/TR
R2
COMP
CPVIN
GND
GND
PVIN
PVIN
VIN
RT/SYNC
ROSC
CSS
RCOMP
Place the feedback
components as close
to the IC as possible.
R1 CCOMP
Figure 11. PCB Layout Guide
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is a registered trademark of Richtek Technology Corporation.
DS7243-06
June 2019
RT7243
Outline Dimension
1
1
2
2
DETAIL A
Pin #1 ID and Tie Bar Mark Options
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Symbol
Dimensions In Millimeters
Dimensions In Inches
Min.
Max.
Min.
Max.
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.200
0.300
0.008
0.012
D
3.400
3.600
0.134
0.142
D2
2.000
2.100
0.079
0.083
D3
0.200
0.008
E
3.400
3.600
0.134
0.142
E2
2.000
2.100
0.079
0.083
E3
0.325
0.013
e
0.500
0.020
e1
1.500
0.059
K
0.350
0.014
L
0.350
0.450
0.014
0.018
W-Type 14AL QFN 3.5x3.5 Package
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Customers should obtain the latest relevant information and data sheets before placing orders and should verify
that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek
product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use;
nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent
or patent rights of Richtek or its subsidiaries.
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June 2019
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