RT7259GQW

® RT7259 10A, 24V, 600kHz Step-Down Converter with Synchronous Gate Driver General Description Features The RT7259 is a synchronous step-down DC/DC converter with an integrated high side internal power MOSFET and a gate driver for a low side external power MOSFET. It can deliver up to 10A output current from a 4.5V to 24V input supply. The RT7259's current mode architecture allows the transient response to be optimized over a wider input voltage and load range. Cycle-by-cycle current limit provides protection against shorted outputs and soft-start eliminates input current surge during start-up. The RT7259 is synchronizable to an external clock with frequency ranging from 300kHz to 1.5MHz. z The RT7259 is available in WDFN-14L 4x3 package. z z z z z z z z z z z z z Applications z z z z z Point of Load Regulator in Distributed Power System Digital Set top Boxes Personal Digital Recorders Broadband Communications Flat Panel TVs and Monitors z z 4.5V to 24V Input Voltage Range 10A Output Current 45mΩ Ω Internal High Side N-MOSFET Current Mode Control 600kHz Switching Frequency Adjustable Output from 0.808V to 15V Up to 95% Efficiency Internal Compensation Stable with Ceramic Capacitors Synchronous External Clock : 300kHz to 1.5MHz Cycle-by-Cycle Current Limit Input Under Voltage Lockout Output Under Voltage Protection Power Good Indicator Thermal Shutdown Protection RoHS Compliant and Halogen Free Simplified Application Circuit VIN VIN RT7259 BOOT CIN CBOOT L SW VCC BG PGOOD R2 EN/SYNC Copyright © 2013 Richtek Technology Corporation. All rights reserved. November 2013 COUT FB Chip Enable DS7259-01 Q1 R1 CVCC Power Good VOUT GND is a registered trademark of Richtek Technology Corporation. www.richtek.com 1 RT7259 Ordering Information Marking Information 14= : Product Code RT7259 Package Type QW : WDFN-14L 4x3 (W-Type) 14=YM DNN YMDNN : Date Code Lead Plating System G : Green (Halogen Free and Pb Free) Note : Pin Configurations Richtek products are : ` RoHS compliant and compatible with the current require- ` Suitable for use in SnPb or Pb-free soldering processes. ments of IPC/JEDEC J-STD-020. (TOP VIEW) FB PGOOD EN/SYNC VIN VIN VIN NC 1 14 2 13 3 4 5 6 7 12 GND 15 11 10 9 8 GND BG VCC BOOT SW SW SW WDFN-14L 4x3 Functional Pin Description Pin No. Pin Name Pin Function 1 FB Feedback Input. This pin is connected to the converter output. It is used to set the output of the converter to regulate to the desired value via an external resistive divider. The feedback reference voltage is 0.808V typically. 2 PGOOD Power Good Indicator with Open Drain. A 100kΩ pull-high resistor is needed. The output of this pin is pulled to low when the FB is lower than 0.75V; otherwise it is high impedance. 3 EN/SYNC 4, 5, 6 VIN 7 NC 8, 9, 10 SW 11 BOOT 12 VCC 13 BG 14, GND 15 (Exposed Pad) Enable or External Frequency Synchronization Input. A logic-high (2V < EN < 5.5V) enables the converter; a logic-low forces the IC into shutdown mode reducing the supply current to less than 3μA. For external frequency synchronization operation, the available frequency range is from 300kHz to 1.5MHz. Power Input. The available input voltage range is from 4.5V to 24V. A 22μF or larger input capacitor is needed to reduce voltage spikes at the input. No Internal Connection. Switching Node. Output of the internal high side MOSFET. Connect this pin to external low side N-MOSFET, inductor and bootstrap capacitor. Bootstrap for High side Gate Driver. Connect a 1μF ceramic capacitor between the BOOT pin and SW pin. BG Driver Bias Supply. Decouple with a 1μF X5R/X7R ceramic capacitor between the VCC pin and GND. Gate Driver Output. Connect this pin to the gate of the external low side N-MOSFET. Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum thermal dissipation. Copyright © 2013 Richtek Technology Corporation. All rights reserved. www.richtek.com 2 is a registered trademark of Richtek Technology Corporation. DS7259-01 November 2013 RT7259 Function Block Diagram VIN VCC VCC Internal Regulator OSC Enable Comparator + 1.7V EN/SYNC - - 5k Slope Current Sense Compensator Amplifier + Foldback Control 3V RSENSE VCC OTP BOOT UV Comparator VCC 0.4V + - 0.808V VSS 54pF FB 45m Switch Controller SW Current Signal + +EA - COMP + - Current Comparator BG Driver BG 300k 1pF PGOOD Comparator 0.75V + - PGOOD GND Operation The RT7259 is a synchronous high voltage Buck Converter that can support the input voltage range from 4.5V to 24V and the output current can be up to 10A. The RT7259 uses a constant frequency, current mode architecture. In normal operation, the high side N-MOSFET is turned on when the Switch Controller is set by the oscillator (OSC) and is turned off when the current comparator resets the Switch Controller. While the N-MOSFET is turned off, the external low side N-MOSFET is turned on by BG Driver with 5V driving voltage from Internal Regulator (VCC) until next cycle begins. High side MOSFET peak current is measured by internal RSENSE. The Current Signal is where Slope Compensator works together with sensing voltage of RSENSE. The error amplifier EA adjusts COMP voltage by comparing the feedback signal (VFB) from the output voltage with the internal 0.808V reference. When the load current increases, it causes a drop in the feedback voltage relative to the reference, the COMP voltage then rises to allow higher inductor current to match the load current. UV Comparator : If the feedback voltage (VFB) is lower than threshold voltage 0.4V, the UV Comparator's output will go high and the Switch Controller will turn off the high Copyright © 2013 Richtek Technology Corporation. All rights reserved. DS7259-01 November 2013 side MOSFET. The output under voltage protection is designed to operate in Hiccup mode. Oscillator (OSC) : The internal oscillator runs at nominal frequency 600kHz and can be synchronized by an external clock in the range between 300kHz and 1.5MHz from EN/ SYNC pin. PGOOD Comparator : When the feedback voltage (VFB) is higher than threshold voltage 0.75V, the PGOOD open drain output will be high impedance. Enable Comparator : Internal 5kΩ resistor and Zener diode are used to clamp the input signal to 3V. A 1.7V reference voltage is for EN logic-high threshold voltage. The EN pin can be connected to VIN through a 100kΩ resistor for automatic startup. Foldback Control : When VFB is lower than 0.7V, the oscillation frequency will be proportional to the feedback voltage. Soft-Start (SS) : An internal current source charges an internal capacitor to build the soft-start ramp voltage (VSS). The VFB voltage will track the internal ramp voltage during soft-start interval. The typical soft-start time is 2ms. is a registered trademark of Richtek Technology Corporation. www.richtek.com 3 RT7259 Absolute Maximum Ratings z z z z z z z z z z (Note 1) Supply Input Voltage, VIN -----------------------------------------------------------------------------------------Switching Voltage, SW -------------------------------------------------------------------------------------------SW (AC) < 20ns ----------------------------------------------------------------------------------------------------BOOT to SW --------------------------------------------------------------------------------------------------------All Other Voltage ---------------------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C WDFN-14L 4x3 ------------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2) WDFN-14L 4x3, θJA ------------------------------------------------------------------------------------------------WDFN-14L 4x3, θJC ------------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------Junction Temperature ----------------------------------------------------------------------------------------------Storage Temperature Range -------------------------------------------------------------------------------------ESD Susceptibility (Note 3) HBM (Human Body Mode) ---------------------------------------------------------------------------------------MM (Machine Mode) ------------------------------------------------------------------------------------------------ Recommended Operating Conditions z z z –0.3V to 26V –0.3V to (VIN + 0.3V) −5V to 30V –0.3V to 6V −0.3V to 6V 1.667W 60°C/W 7.5°C/W 260°C 150°C –65°C to 150°C 2kV 200V (Note 4) Supply Input Voltage, VIN ------------------------------------------------------------------------------------------ 4.5V to 24V Junction Temperature Range -------------------------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range -------------------------------------------------------------------------------------- −40°C to 85°C Electrical Characteristics (VIN = 12V, TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit Shutdown Supply Current VEN = 0V -- 1 -- μA Supply Current VEN = 3V, VFB = 1V -- 0.9 -- mA 0.82 V Reference Voltage VREF 4.5V ≤ VIN ≤ 24V Feedback Current I FB VFB = 0.8V High Side Switch On Resistance RDS(ON) BOOT − SW = 4.8V High Side Switch Current Limit 0.796 0.808 -- 10 -- nA -- 45 -- mΩ -- 16 -- A -- 600 -- kHz Oscillation Frequency f OSC1 Short Circuit Oscillation Frequency f OSC2 VFB = 0V -- 190 -- kHz Maximum Duty Cycle DMAX VFB = 0.6V -- 90 -- % Minimum On-Time t ON VFB = 1V -- 100 -- ns 4 4.2 4.4 V -- 400 -- mV Input Under Voltage Lockout Threshold VUVLO Input Under Voltage Lockout Threshold ΔVUVLO Hysteresis EN Threshold Voltage Logic-High VIH 2 -- 5.5 Logic-Low VIL -- -- 0.4 V Sync Frequency Range f Sync 0.3 -- 1.5 MHz EN Turn-Off Delay t OFF -- 10 -- μs Copyright © 2013 Richtek Technology Corporation. All rights reserved. www.richtek.com 4 is a registered trademark of Richtek Technology Corporation. DS7259-01 November 2013 RT7259 Parameter Symbol EN Pull Low Current Test Conditions VEN = 2V Min Typ Max Unit -- 1 -- μA Thermal Shutdown T SD -- 150 -- °C Thermal Shutdown Hysteresis ΔTSD -- 20 -- °C Power Good Threshold Rising -- 0.75 -- V Power Good Threshold Hysteresis -- 40 -- mV -- -- 0.125 V Power Good Pin Level PGOOD Sink 10mA BG Driver Bias Supply Voltage VCC 4.5 5 -- V Gate Driver Sink Impedance RSink -- 0.9 -- Ω Gate Driver Source Impedance RSource -- 3.3 -- Ω Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Copyright © 2013 Richtek Technology Corporation. All rights reserved. DS7259-01 November 2013 is a registered trademark of Richtek Technology Corporation. www.richtek.com 5 RT7259 Typical Application Circuit RT7259 4, 5, 6 VIN 4.5V to 24V VIN BOOT 11 CIN 22µF CBOOT 1µF SW 12 VCC BG 8, 9, 10 13 R1 62k R3 100k FB 2 Chip Enable VOUT 3.3V Q1 CVCC 1µF Power Good L 2.2µH COUT 22µF x 4 1 R2 20k PGOOD 3 EN/SYNC GND 14, 15 (Exposed Pad) Table 1. Recommended Component Selection VOUT (V) R1 (kΩ) R2 (kΩ) L (μH) COUT (μF) 1.2 62 127 1.5 22μF x 4 1.8 70 57 1.5 22μF x 4 2.5 69 33 2.2 22μF x 4 3.3 62 20 2.2 22μF x 4 5 93 18 2.8 22μF x 4 8 120 13.5 3.6 22μF x 4 Copyright © 2013 Richtek Technology Corporation. All rights reserved. www.richtek.com 6 is a registered trademark of Richtek Technology Corporation. DS7259-01 November 2013 RT7259 Typical Operating Characteristics Output Voltage vs. Input Voltage Efficiency vs. Load Current 100 3.33 90 3.32 VIN = 10V VIN = 12V VIN = 24V 70 60 Output Voltage (V) Efficiency (%) 80 50 40 30 20 3.31 3.30 3.29 3.28 10 VIN = 4.5V to 24V, VOUT = 3.3V, IOUT = 0A VOUT = 3.3V 3.27 0 0 2 4 6 8 10 4 6 8 10 16 18 20 22 24 Output Voltage vs. Load Current 3.40 3.35 3.38 3.34 3.36 3.33 Output Voltage (V) Output Voltage (V) Output Voltage vs. Temperature 3.34 3.32 3.30 3.28 3.26 3.24 3.32 3.31 3.30 3.29 VIN = 10V VIN = 12V VIN = 24V 3.28 3.27 3.22 3.26 VIN = 12V, VOUT = 3.3V, IOUT = 0A 3.20 VOUT = 3.3V 3.25 -50 -25 0 25 50 75 100 125 0 1 2 3 5 6 7 8 9 10 Switching Frequency vs. Temperature Switching Frequency vs. Input Voltage 650 640 640 Switching Frequency (kHz)1 650 630 620 610 600 590 580 570 560 4 Load Current (A) Temperature (°C) Switching Frequency (kHz)1 14 Input Voltage (V) Load Current (A) 630 620 610 600 590 580 570 560 VOUT = 3.3V, IOUT = 0A VIN = 12V, VOUT = 3.3V, IOUT = 0A 550 550 4 6 8 10 12 14 16 18 20 22 Input Voltage (V) Copyright © 2013 Richtek Technology Corporation. All rights reserved. DS7259-01 12 November 2013 24 -50 -25 0 25 50 75 100 125 Temperature (°C) is a registered trademark of Richtek Technology Corporation. www.richtek.com 7 RT7259 Current Limit vs. Temperature Load Transient Response 18 Output Current (A) 17 VOUT (100mV/Div) 16 15 14 13 12 IOUT (5A/Div) 11 VIN = 12V, VOUT = 3.3V VIN = 12V, VOUT = 3.3V, IOUT = 0A to 10A 10 -50 -25 0 25 50 75 100 Time (500μs/Div) 125 Temperature (°C) Load Transient Response Output Ripple Voltage VOUT (5mV/Div) VOUT (100mV/Div) VSW (10V/Div) IOUT (5A/Div) VIN = 12V, VOUT = 3.3V, IOUT = 5A to 10A IL (5A/Div) VIN = 12V, VOUT = 3.3V, IOUT = 5A Time (500μs/Div) Time (1μs/Div) Output Ripple Voltage Power On from VIN VOUT (5mV/Div) VIN (5V/Div) VSW (10V/Div) VOUT (2V/Div) IL (5A/Div) IL (10A/Div) VIN = 12V, VOUT = 3.3V, IOUT = 10A Time (1μs/Div) Copyright © 2013 Richtek Technology Corporation. All rights reserved. www.richtek.com 8 VIN = 12V, VOUT = 3.3V, IOUT = 10A Time (5ms/Div) is a registered trademark of Richtek Technology Corporation. DS7259-01 November 2013 RT7259 Power On from EN Power Off from VIN VIN = 12V, VOUT = 3.3V, IOUT = 10A VIN = 12V, VOUT = 3.3V, IOUT = 10A VEN (5V/Div) VIN (5V/Div) VOUT (2V/Div) VOUT (2V/Div) IL (10A/Div) IL (10A/Div) Time (5ms/Div) Time (2.5ms/Div) Power Off from EN External SYNC VIN = 12V, VOUT = 3.3V, IOUT = 10A VIN = 12V, VOUT = 3.3V, IOUT = 10A, Clock = 500kHz VEN (5V/Div) Clock (5V/Div) VOUT (2V/Div) VLX (10V/Div) IL (10A/Div) IL (5A/Div) VOUT (2V/Div) Time (2.5ms/Div) Copyright © 2013 Richtek Technology Corporation. All rights reserved. DS7259-01 November 2013 Time (1μs/Div) is a registered trademark of Richtek Technology Corporation. www.richtek.com 9 RT7259 Application Information Output Voltage Setting The resistive divider allows the FB pin to sense the output voltage as shown in Figure 1. can also be externally pulled high by adding a REN resistor and CEN capacitor from the VIN pin (see Figure 3). EN VIN VOUT REN EN RT7259 CEN R1 GND FB RT7259 R2 Figure 3. Enable Timing Control GND Figure 1. Output Voltage Setting The output voltage is set by an external resistive voltage divider according to the following equation : VOUT = VREF ⎛⎜ 1+ R1 ⎞⎟ ⎝ R2 ⎠ Where VREF is the feedback voltage (0.808V typ.). An external MOSFET can be added to implement digital control on the EN pin, as shown in Figure 4. In this case, a 100kΩ pull-up resistor, REN, is connected between VIN pin and the EN pin. MOSFET Q2 will be under logic control to pull down the EN pin. VIN 5V Figure 4. Digital Enable Control Circuit The chip starts to operate when VIN rises to 4.2V (UVLO threshold). During the VIN rising period, if an 8V output voltage is set, VIN is lower than the VOUT target value and it may cause the chip to shut down. To prevent this situation, a resistive voltage divider can be placed between the input voltage and ground and connected to the EN pin to adjust enable threshold, as shown in Figure 5. For example, the setting VOUT is 8V and VIN is from 0V to 12V, when VIN is higher than 10V, the chip is triggered to enable the converter. Assume REN1 = 50kΩ. Then, REN2 = BOOT 1µF SW Figure 2. External Bootstrap Diode (REN1 x VEN_T ) (VIN_S − VEN_T ) where VEN_T is the enable comparator's logic-high reference threshold voltage (1.7V) and VIN_S is the target turn on input voltage (10V in this example). According to the equation, the suggested resistor R EN2 is 10.2kΩ. Chip Enable Operation The EN pin is the chip enable input. Pulling the EN pin low (2V). If the EN pin is pulled to low-level for 10μs above, the IC will shut down. The RT7259 can be synchronized with an external clock ranging from 300kHz to 1.5MHz applied to the EN/SYNC pin. The external clock duty cycle must be from 10% to 90%. 3.5ms (Start-up period) 10µs Under Voltage Protection For the RT7259, it provides Hiccup Mode Under Voltage Protection (UVP). When the VFB voltage drops below 0.4V, the UVP function will be triggered to shut down switching operation. If the UV condition remains for a period, the RT7259 will retry every 2ms. When the UV condition is removed, the converter will resume operation. The UVP is disabled during soft-start period. Hiccup Mode EN/SYNC VFB CLK Foldback External CLK VOUT (1V/Div) 600kHz Figure 6. Startup Sequence Using External Sync Clock IL (10A/Div) VIN = 12V, IOUT = Short Figure 6 shows the synchronization operation in startup period. When the EN/SYNC is triggered by an external clock, the RT7259 enters soft-start phase and the output voltage starts to rise. When VFB is lower than 0.7V, the oscillation frequency will be proportional to the feedback voltage. With higher VFB, the switching frequency is relatively higher. After startup period about 3.5ms, the IC operates with the same frequency as the external clock. Time (2.5ms/Div) Figure 7. Hiccup Mode Under Voltage Protection Duty Cycle Limitation The RT7259 has a maximum duty cycle 90%. The minimum input voltage is determined by the maximum duty cycle and its minimum operating voltage 4.5V. The voltage drops of high side MOSFET and low side MOSFET also must be considered for the minimum input voltage. The minimum duty cycle can be calculated by the following equation : Duty Cycle(min) = fSW x tON(min) Copyright © 2013 Richtek Technology Corporation. All rights reserved. DS7259-01 November 2013 is a registered trademark of Richtek Technology Corporation. www.richtek.com 11 RT7259 where fsw is the switching frequency, tON (min) is the minimum switch on time (100ns). This equation shows that the minimum duty cycle increases when the switching frequency is increased. Therefore, slower switching frequency is necessary to achieve high VIN/VOUT ratio application. For the ripple current selection, the value of ΔIL = 0.24(IMAX) will be a reasonable starting point. The largest ripple current occurs at the highest VIN. To guarantee that the ripple current stays below the specified maximum, the inductor value should be chosen according to the following equation : External N-MOSFET Selection ⎡ VOUT ⎤ ⎡ VOUT ⎤ L =⎢ ⎥ × ⎢1 − VIN(MAX) ⎥ f I × Δ L(MAX) ⎣ ⎦ ⎣ ⎦ The RT7259 is designed to operate using an external low side N-MOSFET. Important parameters for the power MOSFETs are the breakdown voltage (BVDSS), threshold voltage (VGS_TH), on-resistance (RDS(ON)), total gate charge (Qg) and maximum current (ID(MAX)). The gate driver voltage is from internal regulator (5V, VCC). Therefore logic level N-MOSFET must be used in the RT7259 application. The total gate charge (Qg) must be less than 50nC, lower Qg characteristics results in lower power losses. Drain-source on-resistance (RDS(ON)) should be as small as possible, less than 30mΩ is desirable. Lower RDS(ON) results in higher efficiency. Table 2. External N-MOSFET Selection Part No. Manufacture Si7114 Vishay A04474 ALPHA & OMEGA FDS6670AS Fairchild IRF7821 International Rectifier Inductor Selection The inductor value and operating frequency determine the ripple current according to a specific input and output voltage. The ripple current ΔIL increases with higher VIN and decreases with higher inductance. V V ΔIL = ⎡⎢ OUT ⎤⎥ × ⎡⎢1− OUT ⎤⎥ VIN ⎦ ⎣ f ×L ⎦ ⎣ Having a lower ripple current reduces not only the ESR losses in the output capacitors but also the output voltage ripple. High frequency with small ripple current can reduce voltage. For the highest efficiency operation, however, it requires a large inductor to achieve this goal. Copyright © 2013 Richtek Technology Corporation. All rights reserved. www.richtek.com 12 The inductor's current rating (cause a 40°C temperature rising from 25°C ambient) should be greater than the maximum load current and its saturation current should be greater than the short circuit peak current limit. Please see Table 3 for the inductor selection reference. Table 3. Suggested Inductors for Typical Application Circuit Component Supplier Series Zenithtek ZPWM WE TAIYOYUDEN 74477 NR8040 Dimensions (mm) 10 x 10 x 4 6 x6x3 10 x 10 x 4 8 x 10 x 4 CIN and COUT Selection The input capacitance, C IN, is needed to filter the trapezoidal current at the source of the high side MOSFET. To prevent large ripple current, a low ESR input capacitor sized for the maximum RMS current should be used. The approximate RMS current equation is given : V IRMS = IOUT(MAX) OUT VIN VIN −1 VOUT This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT / 2. This simple worst case condition is commonly used for design because even significant deviations do not offer much relief. Choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. is a registered trademark of Richtek Technology Corporation. DS7259-01 November 2013 RT7259 Table 4. Suggested Capacitors for CIN and COUT Location Component Supplier Part No. Capacitance (μF) Case Size CIN MURATA GRM31CR61E106K 10 1206 CIN TDK C3225X5R1E106K 10 1206 CIN TAIYO YUDEN TMK316BJ106ML 10 1206 COUT MURATA GRM31CR60J476M 47 1206 COUT TDK C3225X5R0J476M 47 1210 COUT MURATA GRM32ER71C226M 22 1210 COUT TDK C3225X5R1C22M 22 1210 For the input capacitor, two 10μF low ESR ceramic capacitors are recommended. For the recommended capacitor, please refer to Table 4 for more details. The selection of COUT is determined by the required ESR to minimize voltage ripple. Moreover, the amount of bulk capacitance is also a key for COUT selection to ensure that the control loop is stable. Loop stability can be checked by viewing the load transient response as described in a later section. The output ripple, ΔVOUT , is determined by : 1 ⎤ ΔVOUT ≤ ΔIL ⎡⎢ESR + 8fCOUT ⎥⎦ ⎣ The output ripple will be the highest at the maximum input voltage since ΔIL increases with input voltage. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirement. Higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, VIN. This ringing can couple to the output and be mistaken. A sudden inrush of current through the long wires can potentially cause a voltage spike at VIN large enough to damage the part. Copyright © 2013 Richtek Technology Corporation. All rights reserved. DS7259-01 November 2013 Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step load change. When a step load occurs, VOUT immediately shifts by an amount equal to ΔILOAD x ESR also begins to charge or discharge COUT generating a feedback error signal for the regulator to return VOUT to its steady-state value. During this recovery time, VOUT can be monitored for overshoot or ringing that would indicate a stability problem. Thermal Considerations For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : PD(MAX) = (TJ(MAX) − TA) / θJA where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJA is the junction to ambient thermal resistance. For recommended operating condition specifications of the RT7259, the maximum junction temperature is 125°C. The junction to ambient thermal resistance, θJA, is layout dependent. For WDFN-14L 4x3 package, the thermal resistance, θJA, is 60°C/W on a standard JEDEC 51-7 four-layer thermal test board. is a registered trademark of Richtek Technology Corporation. www.richtek.com 13 RT7259 The maximum power dissipation at TA = 25°C can be calculated by the following formulas : Layout Consideration Follow the PCB layout guidelines for optimal performance of the RT7259. PD(MAX) = (125°C − 25°C) / (60°C/W) = 1.667W for WDFN-14L 4x3 package The maximum power dissipation depends on the operating ambient temperature for fixed T J(MAX) and thermal resistance, θJA. For the RT7259 package, the derating curves in Figure 8 allow the designer to see the effect of rising ambient temperature on the maximum power dissipation. Maximum Power Dissipation (W)1 1.80 ` Keep the traces of the main current paths as short and wide as possible. ` Put the input capacitor as close as possible to the device pins (VIN and GND). ` SW node is with high frequency voltage swing and should be kept at small area. Keep analog components away from the SW node to prevent stray capacitive noise pick-up. ` Connect feedback network behind the output capacitors. Keep the loop area small. Place the feedback components near the RT7259. ` Connect all analog grounds to a common node and then connect the common node to the power ground behind the output capacitors. ` An example of PCB layout guide is shown in Figure 9 for reference. Four-Layer PCB 1.60 1.40 1.20 1.00 0.80 0.60 0.40 0.20 0.00 0 25 50 75 100 125 Ambient Temperature (°C) Figure 8. Derating Curves for RT7259 Package The feedback components must be connected as close to the device as possible. GND R2 VOUT VCC R1 FB 1 14 PGOOD GND EN/SYNC 2 13 3 12 VIN VIN VIN NC 4 R3 The EN/SYNC must be kept away from noise. The trace should be short and shielded with a ground trace. VIN CIN GND 5 11 10 6 9 15 7 8 GND BG VCC BOOT SW SW SW Q1 Input capacitor must be placed as close to the IC as possible. CVCC capacitor must be placed as close to the IC as possible. CVCC CBOOT L BG VOUT SW should be connected to inductor by wide and short trace. Keep sensitive components away from this trace. COUT GND Figure 9. PCB Layout Guide Copyright © 2013 Richtek Technology Corporation. All rights reserved. www.richtek.com 14 is a registered trademark of Richtek Technology Corporation. DS7259-01 November 2013 RT7259 Outline Dimension 2 1 2 1 DETAIL A Pin #1 ID and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 3.900 4.100 0.154 0.161 D2 3.250 3.350 0.128 0.132 E 2.900 3.100 0.114 0.122 E2 1.650 1.750 0.065 0.069 e L 0.500 0.350 0.020 0.450 0.014 0.018 W-Type 14L DFN 4x3 Package Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. DS7259-01 November 2013 www.richtek.com 15