®
RT7302
Primary-Side-Regulation Dimmable LED Driver Controller
with Active PFC
General Description
Features
The RT7302 is a constant current LED driver with active
power factor correction. It supports high power factor
across a wide range of line voltages, and it drives the
converter in the Quasi-Resonant (QR) mode to achieve
higher efficiency. By using Primary Side Regulation (PSR),
the RT7302 controls the output current accurately without
a shunt regulator and an opto-coupler at the secondary
side, reducing the external component count, the cost,
and the volume of the driver board.
The RT7302 is designed to be compatible with PWM
Dimming. The output current can be modulated by the
duty ratio of the external PWM dimming signal.
An in-house design High Voltage (HV) start-up device is
integrated in the RT7302 to minimize the power loss and
shorten the start-up time.
The RT7302 embeds comprehensive protection functions
for robust designs, including LED open-circuit protection,
LED short-circuit protection, output diode short-circuit
protection, VDD Under-Voltage Lockout (UVLO), VDD
Over-Voltage Protection (VDD OVP), Over-Temperature
Protection (OTP), and cycle-by-cycle current limitation.
Tight LED Current Regulation
No Opto-Coupler and TL431 Required
Power Factor Correction (PFC)
Compatible with PWM Dimming
Built-in HV Start-up Device
Quasi-Resonant
Maximum/Minimum Switching Frequency
Clamping
Input Voltage Feed-Forward Compensation
Maximum/Minimum On-Time Limitation
Wide VDD Voltage Range (up to 25V)
Multiple Protection Features
LED Open-Circuit Protection
LED Short-Circuit Protection
Output Diode Short-Circuit Protection
VDD Under-Voltage Lockout
VDD Over-Voltage Protection
Over-Temperature Protection
Cycle-by-Cycle Current Limit
RoHS Compliant and Halogen Free
Applications
AC/DC LED Lighting driver
Simplified Application Circuit
Flyback Converter
Line
Buck-Boost Converter
TX1
BD
CSIN
RM1
Line
Q1
GD
RM2
CS
RPC
RM1
RHV
VDD
CVDD
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COUT
VOUT+
Q1
GD
CS
RPC
RCS
COMP
DAUX
GND
VDD
ZCD
RZCD1
DOUT
RT7302
HV
MULT
CCOMP
RZCD2
DS7302-02 April 2014
CSIN
Neutral
RCS
DAUX
ZCD
VOUT-
RM2
COMP
GND
BD
TX1
VOUT-
RT7302
HV
MULT
CCOMP
VOUT+
COUT
RHV
Neutral
DOUT
CVDD
RZCD1
RZCD2
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RT7302
Ordering Information
Marking Information
RT7302
RT7302GS : Product Number
Package Type
S : SOP-8
RT7302
GSYMDNN
YMDNN : Date Code
Lead Plating System
G : Green (Halogen Free and Pb Free)
Note :
Pin Configurations
Richtek products are :
(TOP VIEW)
RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.
Suitable for use in SnPb or Pb-free soldering processes.
HV
VDD
8
GND
2
7
GD
COMP
3
6
CS
MULT
4
5
ZCD
SOP-8
Functional Pin Description
Pin No.
Pin Name
Pin Function
1
HV
High Voltage Input for Startup.
2
GND
Ground of the Controller.
3
COMP
Compensation Node. Output of the internal trans-conductance amplifier.
4
MULT
Input for Line Voltage Signal. This pin is used to sense the line voltage by resistor divider
to achieve dimming function.
5
ZCD
Zero Current Detection Input. This pin is used to sense the voltage at auxiliary winding of
the transformer.
6
CS
Current Sense Input. Connect this pin to the current sense resistor.
7
GD
Gate Driver Output for External Power MOSFET.
8
VDD
Supply Voltage (VDD) Input. The controller will be enabled when V DD exceeds VTH_ON
and disabled when VDD is lower than VTH_OFF.
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RT7302
Function Block Diagram
HV
Valley
Detector
ZCD
HV Start-Up
Control
Clamping
Circuit
VMULT
Feed-Forward
Compensation
Ramp
Generator
L : Open
H : Closed
Constant Current Control
VMULT
PWM
Control
Logic
VDD Over
Voltage
Protection
VCLAMP 13V
GD
Gate
Driver
RGD
Output Diode
Short Circuit
Protection
Dimming
Comparator
VMULT_EN / VMULT_DS
150mV / 100mV
VDD OVP
VDD
PWM
+
VCS_CL
1V
Current Limit
Comparator
Output Over
Voltage
Protection
Leading
Edge
Blanking
+
Constant On-Time
Comparator
ICS
CS
Starter
Circuit
Under
Voltage
Lockout
(16V/9V)
Over
Temperature
Protection
+
-
OTP
Output OVP
MULT
COMP
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GND
RT7302
Operation
Critical-Conduction Mode (CRM) with Constant
On-Time Control
Figure 1 shows a typical flyback converter with input voltage
(VIN). When main switch Q1 is turned on with a fixed ontime (tON), the peak current (IL_PK) of the magnetic inductor
(Lm) can be calculated by the following equation :
V
IL_PK = IN tON
Lm
TX1
DOUT
+
IL
VIN
+
COUT
Lm
VOUT
IOUT
ROUT
Q1
Primary-Side Constant-Current Regulation
The RT7302 needs no shunt regulator and opto-coupler
at the secondary side to achieve the output current
regulation. Figure 3 shows several key waveforms of a
conventional flyback converter in Quasi-Resonant (QR)
mode, in which VAUX is the voltage on the auxiliary winding
of the transformer.
VDS
VIN
0
GD
(VGS)
VAUX
0
VIN x NA / NP
Figure 1. Typical Flyback Converter
If the input voltage is the output voltage of the full-bridge
rectifier with sinusoidal input voltage (VIN_PK x sin(θ)), the
inductor peak current (IL_PK) can be expressed as the
following equation :
IL_PK =
VIN_PK sin(θ) tON
Lm
Clamped by
controller
IQ1
IDOUT
Figure 3. Key Waveforms of a Flyback Converter
When the converter operates in CRM with constant ontime control, the envelope of the peak inductor current
will follow the input voltage waveform with in-phase. Thus,
high power factor can be achieved, as shown in Figure 2.
VIN
Input Voltage
Iin_avg
Average Input Current
IL_PK
Peak Inductor Current
IDOUT
Output Diode Current
IQ1_DS MOSFET Current
(VOUT + Vf) x NA / NS
Voltage Clamping Circuit
The RT7302 provides a voltage clamping circuit at ZCD
pin since the voltage on the auxiliary winding is negative
when the main switch is turned on. The lowest voltage on
ZCD pin is clamped near zero to prevent the IC from being
damaged by the negative voltage. Meanwhile, the sourcing
ZCD current (IZCD_SH), flowing through the upper resistor
(RZCD1), is sampled and held to be a line-voltage-related
signal for propagation delay compensation. The RT7302
embeds the programmable propagation delay
compensation through CS pin. A sourcing current ICS
(equal to IZCD_SH x KPC) applies a voltage offset (ICS x
RPC) which is proportional to line voltage on CS to
compensate the propagation delay effect. Thus, the output
current can be equal at high and low line voltage.
VQ1_GS MOSFET Gate Voltage
Figure 2. Inductor Current of CRM with Constant
On-Time Control
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RT7302
Valley
Signal
～
～
For improving converter's efficiency, the RT7302 detects
valleys of the Drain-to-Source voltage (VDS) of main switch
and turns on it near the selected valley. For the valley
detections, a pulse of the “valley signal” is generated
after a 500ns (typ.) delay time which starts at which the
voltage (VZCD) on ZCD pin goes down and reaches the
voltage threshold (VZCDT, 0.4V typ.). During the rising of
the VZCD, the VZCD must reach the voltage threshold
(VZCDA, 0.5V typ.). Otherwise, no pulse of the “valley
signal” is generated. Moreover, if the timing when the
falling VZCD reaches VZCDT is not later than a mask time
(tMASK, 2μs typ.) then the valley signal will be masked and
regards as no valley, as shown in Figure 4.
PWM
～
～
Quasi-Resonant Operation
tSTART
Valley
Signal
PWM
tS(MIN)
Valley
Signal
……
PWM
～
～
PWM
tS(MIN)
VZCD
～
～
VZCDA
VZCDT
Valley
Signal
Valley
Signal
……
PWM
5µs
tS(MIN)
500ns
tMASK
Figure 5. PWM Triggered Method
Figure 4. Valley Signal Generating Method
HV Start-up Device
Figure 5 illustrates how valley signal triggers PWM. If no
valley signal is detected for a long time, the next PWM is
triggered by a starter circuit at the end of the interval (tSTART,
130μs typ.) which starts at the rising edge of the previous
PWM signal. A blanking time (tS(MIN), 8.5μs typ.), which
starts at the rising edge of the previous PWM signal, limits
minimum switching period. When the tS(MIN) interval is
on-going, all of valley signals are not allowed to trigger
the next PWM signal. After the end of the tS(MIN) interval,
the coming valley will trigger the next PWM signal. If one
or more valley signals are detected during the tS(MIN)
interval and no valley is detected after the end of the tS(MIN)
interval, the next PWM signal will be triggered
automatically at the end of the tS(MIN) + 5μs (typ.).
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS7302-02 April 2014
An in-house design 500V start-up device is integrated in
the RT7302 to minimize the power loss and shorten the
start-up time. The HV start-up device will be turned on
during start-up period and be turned off during normal
operation. It guarantees fast start-up time and no power
loss in this path during normal operation. A 10kΩ resistor
is recommended to be connected in series with HV pin.
Feed-Forward Compensation
The MULT pin is a high impedance input pin used to detect
the line input voltage. A proper voltage divider and a
capacitor should be applied to sense the rectified input
voltage at the output of bridge diode rectifier. Since the
MULT voltage is proportional to the rectified input voltage,
it is used to generate a feed-forward signal, the peak of
the MULT voltage, to compensate the slope of the ramp,
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RT7302
which is the non-inverting input of the constant on-time
comparator. This function reduces the operating COMP
voltage range over full line input voltage range and extends
the range of the allowed magnetize inductance.
(VCS_SD 1.5 typ.) of the output diode short-circuit protection,
the RT7302 will shut down the PWM output (GD pin) in
few cycles to prevent the converter from damage. It will
be auto-restarted when the failure condition is recovered.
PWM Dimming Function
VDD Under-Voltage Lockout (UVLO) and
Over-Voltage Protection(VDD OVP)
PWM dimmable function is embedded in the RT7302.
When the MULT voltage (VMULT) < VMULT_DIS, the COMP
pin will become high impedance and the regulation loop
operates according to the voltage (VCOMP). The loop will
keep operation with the previous condition. When VMULT
> VMULT_EN, the internal amplifier resumes controlling the
VCOMP for the regulation loop to provide the constant output
current. Thus, the average output current is linearly
proportional to the duty ratio of the PWM dimming signal
The RT7302 will be enabled when VDD voltage (VDD)
exceeds rising UVLO threshold (VTH_ON, 16V typ.) and
disabled when VDD is lower than falling UVLO threshold
(VTH_OFF, 9V typ.).
When VDD exceeds its over-voltage threshold (VOVP, 27V
typ.), the PWM output of the RT7302 is shut down. It will
be auto-restarted when the VDD is recovered to a normal
level.
Protections
Over-Temperature Protection (OTP)
LED Open-Circuit Protection
The RT7302 provides an internal OTP function to protect
the controller itself from suffering thermal stress and
permanent damage. It's not suggested to use the function
as precise control of over temperature. Once the junction
temperature is higher than the OTP threshold (TSD, 150°C
typ.), the controller will shut down until the temperature
cools down by 30°C (typ.). Meanwhile, if VDD reaches falling
UVLO threshold voltage (VTH_OFF), the controller will
hiccup till the over-temperature condition is removed.
In an event of output open circuit, the converter will be
shut down to prevent being damaged, and it will be autorestarted when the output is recovered. Once the LED is
open, the output voltage and VZCD will rise. When the
sample-and-hold ZCD voltage (VZCD_SH) exceeds its OV
threshold (V ZCD_OVP, 3.1V typ.), output OVP will be
activated and the PWM output (GD pin) will be forced low
to turn off the main switch.
If the output is still open-circuit when the converter restarts,
the converter will be shut down again.
LED Short-Circuit Protection
LED short-circuit protection can be achieved by VDD UVLO
and cycle-by-cycle current limitation. Once LED shortcircuit failure occurs, VDD drops related to the output
voltage. When the VDD is lower than falling UVLO threshold
(VTH_OFF, 9V typ.), the converter will be shut down and it
will be auto-restarted when the output is recovered.
Output Diode Short-Circuit Protection
When the output diode is damaged as short-circuit, the
transformer will be led to magnetic saturation and the main
switch will suffer from a high current stress. To avoid the
above situation, an output diode short-circuit protection
is built-in. When CS voltage VCS exceeds the threshold
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DS7302-02 April 2014
RT7302
Absolute Maximum Ratings
(Note 1)
HV to GND ----------------------------------------------------------------------------------------------------------VDD to GND --------------------------------------------------------------------------------------------------------GD to GND ----------------------------------------------------------------------------------------------------------MULT, CS, ZCD, COMP to GND -------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C
SOP-8 ----------------------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2)
SOP-8, θJA ----------------------------------------------------------------------------------------------------------Junction Temperature ---------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -----------------------------------------------------------------------Storage Temperature Range ------------------------------------------------------------------------------------ESD Susceptibility (Note 3)
HBM (Human Body Model) (Except HV pin) ----------------------------------------------------------------MM (Machine Model) ----------------------------------------------------------------------------------------------
Recommended Operating Conditions
−0.3V to 500V
−0.3V to 30V
−0.3V to 20V
−0.3V to 6V
0.48W
206.9°C/W
150°C
260°C
−65°C to 150°C
2kV
200V
(Note 4)
Supply Input Voltage, VDD ---------------------------------------------------------------------------------------- 12V to 25V
COMP Voltage, VCOMP -------------------------------------------------------------------------------------------- 0.7V to 4.3V (Note 5)
Junction Temperature Range ------------------------------------------------------------------------------------- −40°C to 125°C
Electrical Characteristics
(VDD = 15V, TA = 25°C, unless otherwise specification)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
0.8
--
--
mA
--
--
2
A
25.5
27
28.5
V
--
10
--
s
Rising UVLO Threshold Voltage VTH_ON
15
16
17
V
Falling UVLO Threshold Voltage VTH_OFF
8
9
10
V
IZCD = 0, GD Open
--
--
3.5
mA
VDD = VTH_ON 1V
--
--
30
A
IZCD = 0 to 2.5mA
--
0
0.3
V
2.8
3.1
3.4
V
HV Start-up Section
HV Start-up Average Current
I HV_ST
Off State Leakage Current
VDD < VTH_ON, VHV = 100V
VDD = VTH_ON + 1V, VHV = 500V
VDD Supply Current and Protections Section
VDD OVP Threshold Voltage
VOVP
VDD OVP De-bounce Time
Operating Supply Current
(Note 6)
I DD_OP
Start-up Current
ZCD Section
Lower Clamp Voltage
ZCD OVP Threshold Voltage
VZCD_OVP
At the Knee Point
(Note 6)
Enable Threshold Voltage
VMULT_EN
VMULT Rising
--
150
--
mV
Disable Threshold Voltage
VMULT_DIS
VMULT Falling
--
100
--
mV
(Note 6)
--
7
--
s
Dimming Control Section
De-bounce Time
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RT7302
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
0.245
0.25
0.255
V
4.5
--
--
V
--
62.5
--
A
2.2
2.7
3.2
s
Constant Current Control Section
Regulated factor for
Constant-Current Control
KCC
Maximum COMP Voltage
Maximum COMP Sourcing
Current
I COMP < 30A
ICOMP(MAX) VCOMP < 3.5V
Timing Control Section
I ZCD = 150A
Minimum On-Time
tON(MIN)
Maximum On-Time
tON(MAX)
29
47
65
s
Minimum Switching Period
tS(MIN)
7
8.5
10
s
Duration of Starter
tSTART
At No Valley Detected
75
130
300
s
Blanking Time
tLEB
LEB + Propagation Delay
240
400
570
ns
Output Diode Short-Circuit
Protection Voltage Threshold
at CS
VCS_SD
Shutdown when V CS > VCS_SD in 7
cycles.
--
1.5
--
V
CS Voltage Threshold for
Peak Current Limitation
VCS_CL
0.93
1.03
1.13
V
Propagation Delay
Compensation Factor
KPC
Sourcing I CS = I ZCD x KPC ,
I ZCD = 150A
--
0.02
--
A/A
GD Voltage Rising Time
tR
CL = 1nF
--
60
80
ns
GD Voltage Falling Time
tF
CL = 1nF
--
40
70
ns
GD Output Clamping Voltage
VCLAMP
CL = 1nF
--
13
--
V
Internal GD Pull Low Resistor
RGD
--
40
--
k
Current Sense Section
(Note 6)
Gate Driver Section
Over-Temperature Protection Section
Over-Temperature Threshold
TSD
(Note 6)
--
150
--
C
Over-Temperature Threshold
Hysteresis
TSD_HYS
(Note 6)
--
30
--
C
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a low effective thermal conductivity two-layer test board per JEDEC 51-3.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. Please refer to “Feed-Forward Compensation Design” in “Application Information”.
Note 6. Guaranteed by Design.
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RT7302
Typical Application Circuit
Flyback Application Circuit
Line
F1
RSN3 CSN2
TX1
BD
DOUT
+
CSN1
COUT
VOUT
…
RSN1
CSIN
RSN2 DSN
RM1
Neutral
RHV
RT7302
1
HV
4
GD
RG
Q1
RGP
MULT
CMULT
RM2
CS
RPC
6
CCS
3
CCOMP
7
RCS
COMP
2
-
GND
VDD
8
ZCD
5
RAUX DAUX
CVDD
RZCD1
CZCD
RZCD2
Buck-Boost Application Circuit
Line
F1
BD
-
RM1
Neutral
4
CMULT
RT7302
HV
GD
2
VOUT
RG
Q1
RGP
CS
CCOMP
7
MULT
RM2
3
COUT
+
RHV
1
DOUT
…
TX1
CSIN
RPC
6
CCS
COMP
GND
ZCD
5
VDD
8
RCS
RAUX DAUX
CVDD
RZCD1
CZCD
RZCD2
Table 1. Suggested Component Values
CVDD
(F)
CCOMP
(F)
CMULT
(nF)
CZCD
(pF)
CCS
(pF)
RHV
(k)
RM1
(M)
RM2
(k)
RGP
(k)
RG ()
RAUX
()
22
1
1
22
4.7
(optional)
10
7.5
51
10
47
10
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RT7302
Typical Operating Characteristics
IHV_ST vs. Temperature
VOVP vs. Temperature
2.00
28.0
27.6
1.60
VOVP (V)
I HV_ST (mA)
1.80
1.40
26.8
1.20
26.4
1.00
0.80
26.0
-50
-25
0
25
50
75
100
125
-50
-25
0
50
75
Temperature (°C)
VTH_ON vs. Temperature
VTH_OFF vs. Temperature
18.0
11.0
17.5
10.5
17.0
10.0
16.5
16.0
15.5
100
125
100
125
100
125
9.5
9.0
8.5
15.0
8.0
14.5
7.5
14.0
7.0
-50
-25
0
25
50
75
100
125
-50
-25
0
Temperature (°C)
25
50
75
Temperature (°C)
IDD_OP vs. Temperature
KCC vs. Temperature
3.00
0.270
2.75
0.265
2.50
0.260
2.25
0.255
KCC (V)
I DD_OP (mA)
25
Temperature (°C)
VTH_OFF (V)
VTH_ON (V)
27.2
2.00
1.75
0.250
0.245
1.50
0.240
1.25
0.235
1.00
0.230
-50
-25
0
25
50
75
100
Temperature (°C)
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10
125
-50
-25
0
25
50
75
Temperature (°C)
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RT7302
ICOMP(MAX) vs. Temperature
tON(MIN) vs. Temperature
100
3.0
90
tON(MIN) (μs)
I COMP(MAX) (μA)
2.8
80
70
60
2.4
50
2.2
40
30
2.0
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
Temperature (°C)
Temperature (°C)
tSTART vs. Temperature
VCS_SD vs. Temperature
150
1.8
140
1.7
130
1.6
VCS_SD (V)
tSTART (μs)
2.6
120
110
100
125
100
125
100
125
1.5
1.4
1.3
100
1.2
90
-50
-25
0
25
50
75
100
-50
125
-25
0
25
50
75
Temperature (°C)
Temperature (°C)
VCS_CL vs. Temperature
KPC vs. Temperature
1.20
0.022
1.15
0.021
0.020
1.05
KPC (A/A)
VCS_CL (V)
1.10
1.00
0.95
0.019
0.018
0.90
0.017
0.85
0.80
0.016
-50
-25
0
25
50
75
100
Temperature (°C)
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125
-50
-25
0
25
50
75
Temperature (°C)
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RT7302
Application Information
Output Current Setting
IZCD_SH can be expressed as :
Considering the conversion efficiency, the programmed
DC level of the average output current (IOUT (t)) can be
IZCD_SH =
derived as :
Thus, RZCD1 can be determined by :
IOUT_CC
CTRTX1
K
N
= 1 P CC CTRTX1
2 NS RCS
ISEC_PK NS
=
IPRI_PK NP
in which CTR TX1 is the current transfer ratio of the
transformer TX1, ISEC_PK is the peak current of secondary
side, and IPRI_PK is the peak current of the primary side.
CTRTX1 can be estimated to be 0.9.
According to the above parameters, current sense resistor
RCS can be determined as the following equation :
RCS
K CC
N
= 1 P
CTRTX1
2 NS IOUT_CC
Propagation Delay Compensation Design
The VCS deviation (ΔVCS) caused by propagation delay
effect can be derived as :
VCS =
VIN TD RCS
Lm
in which t D is the delay period which includes the
propagation delay of the RT7302 and the turn-off transition
of the main MOSFET. The sourcing current from CS pin
of the RT7302 (ICS) can be expressed as :
N
ICS = KPC VIN A 1
NP R ZCD1
where NA is the turns number of auxiliary winding.
RPC can be designed by :
RPC =
VCS
t RCS R ZCD1 NP
= D
ICS
Lm KPC
NA
Minimum On-Time Setting
The RT7302 limits a minimum on-time (tON(MIN)) for each
switching cycle. The tON(MIN) is a function of the sampleand-hold ZCD current (IZCD_SH) as following :
R ZCD1=
VIN NA
R ZCD1 NP
t ON(MIN) VIN NA
(typ.)
375p
NP
In addition, the current flowing out of ZCD pin must be
lower than 2.5mA (typ.). Thus, the R ZCD1 is also
determined by :
RZCD1 >
2 VAC(MAX) NA
2.5m
NP
where the VAC(MAX) is maximum input AC voltage.
Output Over-Voltage Protection Setting
Output OVP is achieved by sensing the knee voltage on
the auxiliary winging. It is recommended that output OV
level (VOUT_OVP) is set at 120% of nominal output voltage
(VOUT). Thus, RZCD1 and RZCD2 can be determined by the
equation as :
VOUT
R ZCD2
NA
120% = 3.1V (typ.)
NS R ZCD1 R ZCD2
Feed-Forward Compensation Design
The COMP voltage, VCOMP, can be derived from the following
equations.
2
tON tOFF
1 V
Gmramp tON
MULT_pk
2
ts
= Cramp VCOMP
VMULT_pk is the peak voltage on the MULT pin. Gmramp is
the trans-conductance of the ramp generator, and its typical
value is 2.5μA/V. Cramp is the capacitance of the ramp
generator, and its typical value is 6.5pF. It is recommended
to design VCOMP(MIN) = 1.2V. If the COMP voltage is over
its recommended operating range (0.7V to 4.3V), output
current regulation may be affected. Thus, the voltage divider
resistors RM1 and RM2 can be determined according to the
above parameters.
tON(MIN) IZCD_SH 375p sec A (typ.)
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is a registered trademark of Richtek Technology Corporation.
DS7302-02 April 2014
RT7302
CCOMP
CMULT
1F to 4.7F
10pF to 10nF (Dimming)
1nF to 100nF (Non-dimming)
CZCD
10pF to 22pF
CCS
NC to 22pF
RHV
10k to 22k
RM1
6.8M to 8.2M
RM2
47k to 56k
RGP
10k to 22k
RG
10 to 47
RAUX
10 to 100
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
0.8
Maximum Power Dissipation (W)1
Table 2. Suggested Component Values Range
Range of Typical Value
Component
(Tolerance < ±30%)
CVDD
10F to 33F
The maximum power dissipation depends on the operating
ambient temperature for fixed T J(MAX) and thermal
resistance, θJA. The derating curve in Figure 6 allows the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS7302-02 April 2014
0.4
0.3
0.2
0.1
25
50
75
100
125
Ambient Temperature (°C)
Figure 6. Derating Curve of Maximum Power Dissipation
Layout Considerations
A proper PCB layout can abate unknown noise interference
and EMI issue in the switching power supply. Please refer
to the guidelines when designing a PCB layout for
switching power supply.
The current path(1) from input capacitor, transformer,
MOSFET, R CS return to input capacitor is a high
frequency current loop. The path(2) from GD pin,
MOSFET, RCS return to input capacitor is also a high
frequency current loop. They must be as short as
possible to decrease noise coupling and kept a space
to other low voltage traces, such as IC control circuit
paths, especially. Besides, the path(3) between
MOSFET ground(b) and IC ground(d) is recommended
to be as short as possible, too.
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
PD(MAX) = (125°C − 25°C) / (206.9°C/W) = 0.48W for
SOP-8 package
0.5
0
PD(MAX) = (TJ(MAX) − TA) / θJA
calculated by the following formula :
0.6
0.0
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
SOP-8 package, the thermal resistance, θJA, is 206.9°C/
W on a standard JEDEC 51-3 two-layer thermal test board.
The maximum power dissipation at TA = 25°C can be
Two-Layer PCB
0.7
The path(4) from RCD snubber circuit to MOSFET is a
high switching loop. Keep it as small as possible.
The path(5) from input capacitor to HV pin is a high
voltage loop. Keep a space from path(5) to other low
voltage traces.
It is good for reducing noise, output ripple and EMI issue
to separate ground traces of input capacitor(a),
MOSFET(b), auxiliary winding(c) and IC control circuit(d).
Finally, connect them together on input capacitor
ground(a). The areas of these ground traces should be
kept large.
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RT7302
Placing bypass capacitor for abating noise on IC is highly
recommended. The capacitors CMULT, CCOMP, CZCD and
CCS should be placed as close to the controller as
possible.
To minimize parasitic trace inductance and EMI,
minimize the area of the loop connecting the secondary
winding, the output diode, and the output filter capacitor.
In addition, apply sufficient copper area at the anode
and cathode terminal of the diode for heat-sinking. It is
recommended to apply a larger area at the quiet cathode
terminal. A large anode area will induce high-frequency
radiated EMI.
…
Line
(4)
Neutral
(5)
(a)
CMULT
RT7302
HV
Input capacitor
Ground (a)
GD
MULT
Trace
CS
CCS (2)
COMP
GND
CCOMP
ZCD VDD
(b)
(d)
(1)
Trace
IC
Ground (d)
Trace
Auxiliary
MOSFET
Ground (c) Ground (b)
(3)
CZCD
(c)
Figure 7. PCB Layout Guide
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is a registered trademark of Richtek Technology Corporation.
DS7302-02 April 2014
RT7302
Outline Dimension
H
A
M
J
B
F
C
I
D
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
4.801
5.004
0.189
0.197
B
3.810
3.988
0.150
0.157
C
1.346
1.753
0.053
0.069
D
0.330
0.508
0.013
0.020
F
1.194
1.346
0.047
0.053
H
0.170
0.254
0.007
0.010
I
0.050
0.254
0.002
0.010
J
5.791
6.200
0.228
0.244
M
0.400
1.270
0.016
0.050
8-Lead SOP Plastic Package
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
DS7302-02 April 2014
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