RT7304A
Primary-Side Regulation LED Driver Controller with Active-PFC
General Description
Features
The RT7304A is a constant current LED driver with
active power factor correction. It supports high power
factor across a wide range of line voltages, and it drives
the converter in the Quasi-Resonant (QR) mode to
achieve higher efficiency. By using Primary Side
Regulation (PSR), the RT7304A controls the output
current accurately without a shunt regulator and an
opto-coupler at the secondary side, reducing the
external component count, the cost, and the volume of
the driver board.
The RT7304A embeds comprehensive protection
functions for robust designs, including LED open-circuit
protection, LED short-circuit protection, output diode
short-circuit protection, VDD Under-Voltage Lockout
(UVLO), VDD Over-Voltage Protection (VDD OVP),
Over-Temperature Protection (OTP), and cycle-by-cycle
current limitation.
Tight LED Current Regulation
No Opto-Coupler and TL431 Required
Power Factor Correction (PFC)
Quasi-Resonant
Maximum/Minimum Switching Frequency
Clamping
Maximum/Minimum on-Time Limitation
Wide VDD Range (up to 34V)
THD Optimization
Input-Voltage Feed-Forward Compensation
Multiple Protection Features
LED Open-Circuit Protection
LED Short-Circuit Protection
Output Diode Short-Circuit Protection
VDD Under-Voltage Lockout
VDD Over-Voltage Protection
Over-Temperature Protection
Cycle-by-Cycle Current Limitation
Applications
AC/DC LED Lighting Driver
Simplified Application Circuit
Buck-Boost Converter
TX1
BD
VOUT-
Line
CIN
COUT
RST
DOUT
Neutral
CVDD
VDD
RT7304A GD
COMP
CS
CCOMP
ZCD
VOUT+
Q1
RPC
RCS
GND
DAUX
RZCD1
RZCD2
Copyright © 2016 Richtek Technology Corporation. All rights reserved.
DS7304A-00
July 2016
is a registered trademark of Richtek Technology Corporation.
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1
RT7304A
Ordering Information
Pin Configurations
(TOP VIEW)
RT7304A
Package Type
E : SOT-23-6
COMP ZCD CS
6
Lead Plating System
G : Green (Halogen Free and Pb Free)
4
2
3
GND VDD GD
Note :
Richtek products are :
5
SOT-23-6
RoHS compliant and compatible with the current
requirements of IPC/JEDEC J-STD-020.
Suitable for use in SnPb or Pb-free soldering processes.
Marking Information
4T=DNN
4T= : Product Code
DNN : Date Code
Functional Pin Description
Pin No.
Pin Name
Pin Function
1
GND
Ground of the Controller.
2
VDD
Supply Voltage (VDD) Input. The controller will be enabled when VDD exceeds
VTH_ON and disabled when VDD is lower than VTH_OFF.
3
GD
Gate Driver Output for External Power MOSFET.
4
CS
5
ZCD
Current Sense Input. Connect this pin to the current sense resistor.
Zero Current Detection Input. This pin is used to sense the voltage at auxiliary
winding of the transformer.
6
COMP
Compensation Node. Output of the internal trans-conductance amplifier.
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RT7304A
Function Block Diagram
Valley Signal
Valley
Detector
ZCD
Clamping
Circuit
THD
Optimizer
Feed-Forward
Compensator
Ramp
Generator
Starter
Circuit
+
PWM
Control
Logic
PWM
Output
Over-Voltage
Protection
CS
CS
VCS_CL
1.2V
Leading
Edge
Blanking
Gate Driver
+
VDD
VDD
Over-Voltage
Protection
VDD OVP
Constant on-Time
Comparator
Constant
Current
Control
ICS
Under-Voltage
Lockout
(16V/9V)
UVLO
GD
Current-Limit
Comparator
Output Diode
Short-Circuit
Protection
GND
OverTemperature
Protection
OTP
Output OVP
COMP
Operation
Critical-Conduction Mode (CRM) with Constant
IL_PK
VIN_PK sin(θ) tON
Lm
On-Time Control
Figure 1 shows a typical flyback converter with input
voltage (VIN). When main switch Q1 is turned on with a
fixed on-time (tON), the peak current (IL_PK) of the
magnetic inductor (Lm) can be calculated by the following
equation :
When the converter operates in CRM with constant
on-time control, the envelope of the peak inductor current
will follow the input voltage waveform with in-phase. Thus,
high power factor can be achieved, as shown in Figure 2.
V
IL_PK IN tON
Lm
TX1
NP:NS DOUT
IL
+
COUT
Lm
VIN
VOUT
-
IOUT
ROUT
Q1
Figure 1. Typical Flyback Converter
If the input voltage is the output voltage of the
full-bridge rectifier with sinusoidal input voltage
(VIN_PKsin()), the inductor peak current (IL_PK) can be
expressed as the following equation :
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DS7304A-00
July 2016
VIN
Input Voltage
IL_PK
Peak Inductor Current
IQ1_DS
MOSFET Current
Iin_avg
Average Input Current
IDo
Output Diode Current
VQ1_GS
MOSFET Gate Voltage
Figure 2. Inductor Current of CRM with Constant
On-Time Control
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RT7304A
RT7304A needs no shunt regulator and opto-coupler at
the secondary side to achieve the output current
regulation. Figure 3 shows several key waveforms of a
(tSTART, 130s typ.) which starts at the rising edge of
the previous PWM signal. A blanking time (tS(MIN),
8.5μs typ.), which starts at the rising edge of the
conventional flyback converter in Quasi-Resonant (QR)
mode, in which VAUX is the voltage on the auxiliary
winding of the transformer.
previous PWM signal, limits minimum switching period.
When the tS(MIN) interval is on-going, all of valley
signals are not allowed to trigger the next PWM signal.
After the end of the tS(MIN) interval, the coming valley
will trigger the next PWM signal. If one or more valley
signals are detected during the tS(MIN) interval and no
valley is detected after the end of the tS(MIN) interval,
the next PWM signal will be triggered automatically at
end of the tS(MIN) + 5s (typ.).
VDS
VIN
0
GD
(VGS)
(VOUT + Vf) x Naux / NS
VIN x Naux / NP
Clamped by Controller
～
～
Valley
Signal
0
PWM
～
～
VAUX
tSTART
IQ1
Valley
Signal
IDOUT
PWM
Figure 3. Key Waveforms of a Flyback Converter
Voltage Clamping Circuit
The RT7304A provides a voltage clamping circuit at
ZCD pin since the voltage on the auxiliary winding is
negative when the main switch is turned on. The lowest
voltage on ZCD pin is clamped near zero to prevent the
IC from being damaged by the negative voltage.
Meanwhile, the sourcing ZCD current (IZCD_SH),
flowing through the upper resistor (RZCD1), is sampled
and held to be a line-voltage-related signal for
propagation delay compensation. The RT7304A
embeds the programmable propagation delay
compensation through CS pin. A sourcing current ICS
(equal to IZCD_SH x KPC) applies a voltage offset (ICS x
RPC) which is proportional to line voltage on CS to
compensate the propagation delay effect. Thus, the
output current can be equal at high and low line
voltage.
Quasi-Resonant Operation
Figure 4 illustrates how valley signal triggers PWM. If
no valley signal detected for a long time, the next PWM
is triggered by a starter circuit at end of the interval
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4
tS(MIN)
Valley
Signal
PWM
tS(MIN)
Valley
Signal
PWM
tS(MIN)
5μs
Figure 4. PWM Triggered Method
Protections
LED Open-Circuit Protection
In an event of output open circuit, the converter will be
shut down to prevent being damaged, and it will be
auto-restarted when the output is recovered. Once the
LED is open-circuit, the output voltage keeps rising,
causing the voltage on ZCD pin VZCD rising accordingly.
When the sample-and-hold ZCD voltage (VZCD_SH)
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DS7304A-00
July 2016
RT7304A
exceeds its OV threshold (VZCD_OVP, 3.2V typ.), output
OVP will be activated and the PWM output (GD pin) will
be forced low to turn off the main switch. If the output is
still open-circuit when the converter restarts, the
converter will be shut down again.
Output Diode Short-Circuit Protection
When the output diode is damaged as short-circuit, the
transformer will be led to magnetic saturation and the
main switch will suffer from a high current stress. To
avoid the above situation, an output diode short-circuit
protection is built-in. When CS voltage VCS exceeds
the threshold (VCS_SD 1.7 typ.) of the output diode
short-circuit protection, RT7304A will shut down the
PWM output (GD pin) in few cycles to prevent the
converter from damage. It will be auto-restarted when
the failure condition is recovered.
VDD Under-Voltage Lockout (UVLO) and
Over-Voltage Protection (VDD OVP)
RT7304A will be enabled when VDD voltage (VDD)
exceeds rising UVLO threshold (VTH_ON, 17V typ.) and
disabled when VDD is lower than falling UVLO
threshold (VTH_OFF, 8.5V typ.).
When VDD exceeds its over-voltage threshold (VOVP,
37.4V typ.), the PWM output of RT7304A is shut down.
It will be auto-restarted when the VDD is recovered to a
normal level.
Over-Temperature Protection (OTP)
The RT7304A provides an internal OTP function to
protect the controller itself from suffering thermal stress
and permanent damage. It's not suggested to use the
function as precise control of over temperature. Once the
junction temperature is higher than the OTP threshold
(TSD, 150C typ.), the controller will shut down until the
temperature cools down by 30C (typ.). Meanwhile, if VDD
reaches falling UVLO threshold voltage (VTH_OFF), the
controller will hiccup till the over temperature condition is
removed.
Copyright © 2016 Richtek Technology Corporation. All rights reserved.
DS7304A-00
July 2016
is a registered trademark of Richtek Technology Corporation.
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RT7304A
Absolute Maximum Ratings
(Note 1)
Supply Voltage, VDD ------------------------------------------------------------------------------------------------- 0.3V to 40V
Gate Driver Output, GD --------------------------------------------------------------------------------------------- 0.3V to 20V
Other Pins -------------------------------------------------------------------------------------------------------------- 0.3V to 6V
Power Dissipation, PD @ TA = 25C
SOT-23-6---------------------------------------------------------------------------------------------------------------- 0.42W
Package Thermal Resistance
(Note 2)
SOT-23-6, JA ---------------------------------------------------------------------------------------------------------- 235.6C/W
Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------------- 260C
Junction Temperature ------------------------------------------------------------------------------------------------ 150C
Storage Temperature Range --------------------------------------------------------------------------------------- 65C to 150C
ESD Susceptibility
(Note 3)
HBM (Human Body Model) ----------------------------------------------------------------------------------------- 2kV
MM (Machine Model) ------------------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions
(Note 4)
Supply Input Voltage, VDD ----------------------------------------------------------------------------------------- 11V to 34V
COMP Voltage, VCOMP --------------------------------------------------------------------------------------------- 0.7V to 4.3V
Junction Temperature Range -------------------------------------------------------------------------------------- 40C to 125C
Electrical Characteristics
(VDD = 15V, TA = 25C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
35.4
37.4
39.4
V
16
17
18
V
7.5
8.5
9.5
V
VDD Section
VDD OVP Threshold Voltage
VOVP
Rising UVLO Threshold Voltage
VTH_ON
VDD Rising
Falling UVLO Threshold Voltage VTH_OFF
Operating Current
IDD_OP
VDD = 15V, IZCD = 0, GD open
--
2
3
mA
Start-up Current
IVDD_ST
VDD = VTH_ON 1V
--
15
30
A
Lower Clamp Voltage
VZCDL
IZCD = 0 to 2.5mA
50
0
60
mV
ZCD OVP Threshold Voltage
VZCD_OVP
3.04
3.2
3.36
V
246.25
250
253.75
mV
ZCD Section
Constant Current Control Section
Maximum Regulated factor for
constant-current control
KCC(MAX)
Maximum Comp Voltage
VCOMP(MAX)
5
5.5
--
V
Minimum Comp Voltage
VCOMP(MIN)
--
0.5
--
V
Maximum Sourcing Current
ICOMP(MAX)
--
100
--
A
240
400
570
ns
VDIM = 3V
During start-up period
Current Sense Section
Leading Edge Blanking Time
tLEB
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RT7304A
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Peak Current Shutdown Voltage
VCS_SD
Threshold
1.53
1.7
1.87
V
Peak Current Limitation at
Normal Operation
VCS_CL
1.08
1.2
1.32
V
Propagation Delay
Compensation Factor
KPC
ICS = KPC x IZCD, IZCD =
150A
--
0.042
--
A/A
Rising Time
tR
VDD = 15V, CL = 1nF
--
140
250
ns
Falling Time
tF
VDD = 15V, CL = 1nF
--
40
70
ns
Gate Output Clamping Voltage
VCLAMP
VDD = 15V, CL = 1nF
10.8
12
13.2
V
Minimum on-Time
tON(MIN)
IZCD = 150A
0.9
1.25
1.6
s
Minimum Switching Period
Duration of Starter at Normal
Operation
tS(MIN)
7
8.5
10
s
tSTART
75
130
300
s
Maximum on-Time
tON(MAX)
29
47
65
s
Gate Driver Section
Timing Control Section
Over-Temperature Protection (OTP) Section
OTP Temperature Threshold
TOTP
(Note 5)
--
150
--
C
OTP Temperature Hysteresis
TOTP-HYS
(Note 5)
--
30
--
C
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect
device reliability.
Note 2. JA is measured under natural convection (still air) at TA = 25C with the component mounted on a low
effective-thermal-conductivity two-layer test board on a JEDEC thermal measurement standard.
Note 3. Devices are ESD sensitive. Handling precaution recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. Guarantee by design.
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RT7304A
Typical Application Circuit
Flyback Converter
RSN2 CSN2
TX1
BD
F1
DOUT
+
Line
COUT
CIN
～
～ VOUT
RSN1
CSN1
RST
Neutral
-
DSN
2
RT7304A GD 3
VDD
RG
4
RPC
Q1
CVDD
6
CS
COMP
CCOMP
RCS
5 ZCD
GND
CZCD
RAUX
1
DAUX
RZCD1
RZCD2
Buck-Boost Converter
F1
TX1
BD
-
Line
CIN
DOUT
RST
COUT
～ VOUT
～
+
Neutral
RT7304A GD
2
3 RG
VDD
CVDD
6
Q1
COMP
CS
4
CCOMP
RPC
RCS
5 ZCD
CZCD
RAUX
GND
1
DAUX
RZCD1
RZCD2
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RT7304A
Typical Operating Characteristics
VTH_OFF vs. Junction Temperature
VOVP vs. Junction Temperature
36.7
8.60
36.6
8.56
VTH_OFF (V)
VOVP (V)
36.5
36.4
36.3
8.52
8.48
36.2
8.44
36.1
8.40
36.0
-50
-25
0
25
50
75
100
-50
125
-25
0
25
50
75
100
125
Junction Temperature (°C)
Junction Temperature (°C)
VZCDL vs. Junction Temperature
IDD_OP vs. Junction Temperature
25
2.00
1.95
20
VZCDL (mV)
I DD_OP (mA)
1.90
1.85
1.80
15
10
1.75
5
1.70
0
1.65
-50
-25
0
25
50
75
100
-50
125
-25
0
25
50
75
100
125
Junction Temperature (°C)
Junction Temperature (°C)
KCC vs. Junction Temperature
VCOMP(MAX) vs. Junction Temperature
260
5.26
5.24
VCOMP(MAX) (V)
KCC (mV)
258
256
5.22
5.20
5.18
5.16
254
5.14
252
5.12
-50
-25
0
25
50
75
100
Junction Temperature (°C)
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125
-50
-25
0
25
50
75
100
125
Junction Temperature (°C)
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RT7304A
ICOMP(MAX) vs. Junction Temperature
tLEB vs. Junction Temperature
500
140
120
tLEB (ns)
I COMP(MAX) (A)
480
100
80
60
460
440
40
420
20
0
400
-50
-25
0
25
50
75
100
125
-50
-25
Junction Temperature (°C)
0
25
50
75
100
125
Junction Temperature (°C)
VCS_SD vs. Junction Temperature
VCS_CL vs. Junction Temperature
1.850
1.30
1.28
VCS_CL (V)
VCS_SD (V)
1.825
1.800
1.26
1.24
1.22
1.775
1.20
1.18
1.750
-50
-25
0
25
50
75
100
-50
125
-25
25
50
75
100
125
tON(MIN) vs. Junction Temperature
KPC vs. Junction Temperature
0.045
1.30
0.044
1.25
tON(MIN) (μs)
KPC (A/A)
0
Junction Temperature (°C)
Junction Temperature (°C)
0.043
0.042
1.20
1.15
1.10
0.041
1.05
0.040
-50
-25
0
25
50
75
100
Junction Temperature (°C)
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10
125
-50
-25
0
25
50
75
100
125
Junction Temperature (°C)
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RT7304A
tON(MAX) vs. Junction Temperature
60
140
50
130
40
tON(MAX) (μs)
tSTART (μs)
tSTART vs. Junction Temperature
150
120
110
30
20
10
100
0
90
-50
-25
0
25
50
75
100
Junction Temperature (°C)
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125
-50
-25
0
25
50
75
100
125
Junction Temperature (°C)
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RT7304A
Application Information
Output Current Setting
Feed-Forward Compensation Design
Considering the conversion efficiency, the programmed
DC level of the average output current (IOUT(t)) can be
derived as :
The COMP voltage, VCOMP, is a function of the resistor
RZCD1 as following :
IOUT_CC 1 NP KCC CTRTX1
2 NS RCS
RZCD1
CTRTX1
ISEC_PK NS
IPRI_PK NP
in which CTRTX1 is the current transfer ratio of the
transformer TX1, ISEC_PK is the peak current of the
secondary side, and IPRI_PK is the peak current of the
primary side. CTRTX1 can be estimated to be 0.9.
According to the above parameters, current sense
resistor RCS can be determined as the following
equation :
tON Gm
ramp tON
t
N
S
= VIN_pk A KIV
NP
2 Cramp VCOMP VD
in which KIV, Gmramp, and Cramp are fixed parameters in
the RT7304A, and the typical value are : KIV = 2.5V/mA,
Gmramp = 8A/V, Cramp = 6.5pF.
VD is the offset of the constant on-time comparator, and
its typical value is 0.63V. It is recommended to design
VCOMP = 2 to 3V. If the COMP voltage is over its
recommended operating range (0.7 to 4.3V), output
current regulation may be affected. Thus, the resistors
RZCD1 can be determined according to the above
RCS 1 NP KCC CTRTX1
2 NS IOUT_CC
parameters.
Propagation Delay Compensation Design
The RT7304A limits a minimum on-time (tON(MIN)) for
each switching cycle. The tON(MIN) can be derived from
the following equations.
The VCS deviation (VCS) caused by propagation delay
effect can be derived as:
V t R
VCS IN D CS ,
Lm
in which tD is the delay period which includes the
propagation delay of RT7304A and the turn-off
transition of the main MOSFET. The sourcing current
from CS pin of RT7304A (ICS) can be expressed as :
N
ICS KPC VIN A 1
NP RZCD1
where NA is the turns number of the auxiliary winding.
RPC can be designed by :
RPC
VCS tD RCS RZCD1 NP
ICS
Lm KPC
NA
Minimum On-Time Setting
tON(MIN) IZCD_SH 187.5p sec A (typ.)
Thus, RZCD1 can be determined by:
RZCD1
tON(MIN) VIN NA
(typ.)
187.5p
NP
In addition, the current flowing out of ZCD pin must be
lower than 2.5mA (typ.). Thus, the RZCD1 is also
determined by :
RZCD1
2 VAC(MAX) NA
2.5m
NP
where the VAC(MAX) is maximum input AC voltage.
Output Over-Voltage Protection Setting
Output OVP is achieved by sensing the voltage on the
auxiliary winging. It is recommended that output OV
level (VOUT_OVP) is set at 120% of nominal output
voltage (VOUT). Thus, RZCD1 and RZCD2 can be
determined by the equation as :
RZCD2
N
VOUT A
120% 3.2V(typ.)
NS RZCD1 RZCD2
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is a registered trademark of Richtek Technology Corporation.
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RT7304A
Thermal Considerations
Layout Considerations
For continuous operation, do not exceed absolute
A proper PCB layout can abate unknown noise
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature.
The maximum power dissipation can be calculated by
the following formula :
interference and EMI issue in the switching power
supply. Please refer to the guidelines when designing a
PCB layout for switching power supply :
PD(MAX) = (TJ(MAX) − TA ) / θJA
The current path(1) from input capacitor, transformer,
MOSFET, RCS return to input capacitor is a high
frequency current loop. The path(2) from GD pin,
MOSFET, RCS return to the ground of the IC is also
a high frequency current loop. They must be as short
as possible to decrease noise coupling and kept a
space to other low voltage traces, such as IC control
circuit paths, especially. Besides, the path(3)
between MOSFET ground(b) and IC ground(d) is
recommended to be as short as possible, too.
Where TJ(MAX) is the maximum junction temperature,
TA is the ambient temperature, and θJA is the junction
to ambient thermal resistance.
For recommended operating condition specifications,
the maximum junction temperature is 125°C. The
junction to ambient thermal resistance, θJA, is layout
dependent. For SOT-23-6 packages, the thermal
resistance, θJA, is 235.6°C/W on a standard JEDEC
51-3 two-layer thermal test board.The maximum power
The path(4) from RCD snubber circuit to MOSFET is
a high switching loop. Keep it as small as possible.
It is good for reducing noise, output ripple and EMI
dissipation at TA= 25°C can be calculated by the
following formula:
issue to separate ground traces of input capacitor(a),
MOSFET(b), auxiliary winding(c) and IC control
circuit(d). Finally, connect them together on input
capacitor ground(a). The areas of these ground
traces should be kept large.
PD(MAX) = (125°C − 25°C) / (235.6°C/W) = 0.42W for
SOT-23-6 package.
The maximum power dissipation depends on the
operating ambient temperature for fixed TJ(MAX) and
thermal resistance, θJA. The derating curve in Figure 5
allows the designer to see the effect of rising ambient
temperature on the maximum power dissipation.
Maximum Power Dissipation (W)1
0.6
To minimize parasitic trace inductance and EMI,
minimize the area of the loop connecting the
secondary winding, the output diode, and the output
filter capacitor. In addition, apply sufficient copper
area at the anode and cathode terminal of the diode
for heat-sinking. It is recommended to apply a larger
area at the quiet cathode terminal. A large anode
Two-Layer PCB
0.5
area will induce high-frequency radiated EMI.
0.4
0.3
0.2
0.1
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 5. Derating Curve of Maximum Power
Dissipation
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RT7304A
Line
～
～
CIN
RST
Neutral
(4)
(a)
RT7304A
VDD
GD
CVDD
CS
COMP
CCOMP
(2)
(1)
GND
(d)
ZCD
(3)
Input Capacitor
Ground (a)
(b)
CZCD
Trace
Trace
IC
Ground (d)
Trace
Auxiliary
Ground (c)
MOSFET
Ground (b)
(c)
Figure 6. PCB Layout Guide
Copyright © 2016 Richtek Technology Corporation. All rights reserved.
www.richtek.com
14
is a registered trademark of Richtek Technology Corporation.
DS7304A-00
July 2016
RT7304A
Outline Dimension
Symbol
Dimensions In Millimeters
Dimensions In Inches
Min
Max
Min
Max
A
0.889
1.295
0.031
0.051
A1
0.000
0.152
0.000
0.006
B
1.397
1.803
0.055
0.071
b
0.250
0.560
0.010
0.022
C
2.591
2.997
0.102
0.118
D
2.692
3.099
0.106
0.122
e
0.838
1.041
0.033
0.041
H
0.080
0.254
0.003
0.010
L
0.300
0.610
0.012
0.024
SOT-23-6 Surface Mount Package
Copyright © 2016 Richtek Technology Corporation. All rights reserved.
DS7304A-00
July 2016
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
15
RT7304A
Footprint Information
Package
Footprint Dimension (mm)
Number of
TSOT-26/TSOT-26(FC)/SOT-26
Tolerance
Pin
P1
A
B
C
D
M
6
0.95
3.60
1.60
1.00
0.70
2.60
±0.10
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume
responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and
reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
Copyright © 2016 Richtek Technology Corporation. All rights reserved.
www.richtek.com
16
is a registered trademark of Richtek Technology Corporation.
DS7304A-00
July 2016
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