RT7306DGS

RT7306D Primary-Side Regulation Dimmable LED Driver Controller with Active-PFC General Description Features The RT7306D is a constant current LED driver with active power factor correction. It supports high power factor across a wide range of line voltages, and it drives the converter in the Quasi-Resonant (QR) mode to achieve higher efficiency. By using Primary Side Regulation (PSR), the RT7306D controls the output current accurately without a shunt regulator and an opto-coupler at the secondary side, reducing the  external component count, the cost, and the volume of the driver board.  RT7306D is compatible with analog dimming. The output current can be modulated by the DIM pin. An in-house design high voltage (HV) start-up device is integrated in the RT7306D to minimize the power loss and shorten the start-up time.           Tight LED Current Regulation No Opto-Coupler and TL431 Required Power Factor Correction (PFC) Compatible with Analog Dimming Built-In HV Start-Up Device Quasi-Resonant Maximum/Minimum Switching Frequency Clamping Maximum/Minimum On-Time Limitation Wide VDD Range (up to 34V) THD Optimization Input-Voltage Feed-Forward Compensation Multiple Protection Features  LED Open-Circuit Protection LED Short-Circuit Protection Output Diode Short-Circuit Protection VDD Under-Voltage Lockout VDD Over-Voltage Protection Over-Temperature Protection  Cycle-by-Cycle Current Limitation    The RT7306D embeds comprehensive protection functions for robust designs, including LED open-circuit protection, LED short-circuit protection, output diode   short-circuit protection, VDD Under-Voltage Lockout (UVLO), VDD Over-Voltage Protection (VDD OVP), Over-Temperature Protection (OTP), and cycle-by-cycle current limitation. Applications  AC-DC LED Lighting Driver Simplified Application Circuit Buck-Boost Application Circuit Flyback Application Circuit TX1 BD Line RHV CIN VDD Neutral CVDD RT7306D Analog Dimming Signal RHV Neutral CVDD Q1 GD COUT CCOMP RPC RCS GND Analog Dimming Signal DOUT HV VDD RT7306D GD COMP CS DIM ZCD VOUT- Line CIN VOUT- COMP CCOMP VOUT+ COUT HV TX1 BD DOUT CS DIM ZCD VOUT+ Q1 RPC RCS GND DAUX DAUX RZCD1 RZCD1 RZCD2 RZCD2 Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS7306D-01 September 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 1 RT7306D Ordering Information Marking Information RT7306D Package Type S : SOP-8 Lead Plating System G : Green (Halogen Free and Pb Free) Note : RT7306DGS : Product Number YMDNN : Date Code RT7306D GSYMDNN Pin Configuration (TOP VIEW) Richtek products are :  RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.  Suitable for use in SnPb or Pb-free soldering processes. 8 HV VDD GND 2 7 GD COMP 3 6 CS DIM 4 5 ZCD SOP-8 Functional Pin Description Pin No. Pin Name Pin Function 1 HV High voltage input for startup. 2 GND Ground of the controller. 3 COMP Compensation node. Output of the internal trans-conductance amplifier. 4 DIM Analog dimming signal input. LED driving current can be adjusted by an analog voltage. 5 ZCD Zero current detection input. This pin is used to sense the voltage at auxiliary winding of the transformer. 6 CS Current sense input. Connect this pin to the current sense resistor. 7 GD Gate driver output for external power MOSFET. 8 VDD Supply voltage (VDD) input. The controller will be enabled when VDD exceeds VTH_ON and disabled when VDD is lower than VTH_OFF. Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 2 is a registered trademark of Richtek Technology Corporation. DS7306D-01 September 2016 RT7306D Functional Block Diagram HV Valley Signal Valley Detector ZCD Clamping Circuit THD Optimizer Feed-Forward Compensator Ramp Generator Starter Circuit ICS Under-Voltage Lockout (16V/9V) UVLO + VDD OVP Constant on-Time Comparator Constant Current Control HV Start-Up Control PWM Control Logic VDD VDD Over-Voltage Protection VCLAMP 13V PWM Output Over-Voltage Protection VCS_CL 1.2V Leading Edge Blanking CS + GD Gate Driver Current-Limit Comparator RGD Output Diode Short-Circuit Protection GND Dimming Control OverTemperature Protection OTP Output OVP COMP DIM Operation Critical-Conduction Mode (CRM) with Constant On-Time Control Figure 1 shows a typical flyback converter with input voltage (VIN). When main switch Q1 is turned on with a fixed on-time (tON), the peak current (IL_PK) of the magnetic inductor (Lm) can be calculated by the following equation : If the input voltage is the output voltage of the full-bridge rectifier with sinusoidal input voltage (VIN_PKsin()), the inductor peak current (IL_PK) can be expressed as the following equation : IL_PK  VIN_PK  sin(θ)  tON Lm When the converter operates in CRM with constant on-time control, the envelope of the peak inductor current will follow the input voltage waveform with V IL_PK  IN  tON Lm in-phase. Thus, high power factor can be achieved, as shown in Figure 2. TX1 NP:NS DOUT IL + COUT Lm VIN VOUT - IOUT ROUT Q1 Figure 1. Typical Flyback Converter Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS7306D-01 September 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 3 RT7306D Voltage Clamping Circuit VIN Input Voltage IL_PK Peak Inductor Current IQ1_DS MOSFET Current Iin_avg Average Input Current IDo Output Diode Current VQ1_GS MOSFET Gate Voltage Figure 2. Inductor Current of CRM with Constant On-Time Control The RT7306D needs no shunt regulator and opto-coupler at the secondary side to achieve the output current regulation. Figure 3 shows several key waveforms of a conventional flyback converter in Quasi-Resonant (QR) mode, in which VAUX is the voltage on the auxiliary winding of the transformer. VDS VIN 0 GD (VGS) VAUX (VOUT + Vf) x Naux / NS 0 VIN x Naux / NP Clamped by Controller The RT7306D provides a voltage clamping circuit at ZCD pin since the voltage on the auxiliary winding is negative when the main switch is turned on. The lowest voltage on ZCD pin is clamped near zero to prevent the IC from being damaged by the negative voltage. Meanwhile, the sourcing ZCD current (IZCD_SH), flowing through the upper resistor (RZCD1), is sampled and held to be a line-voltage-related signal for propagation delay compensation. The RT7306D embeds the programmable propagation delay compensation through CS pin. A sourcing current ICS (equal to IZCD_SH x KPC) applies a voltage offset (ICS x RPC) which is proportional to line voltage on CS to compensate the propagation delay effect. Thus, the output current can be equal at high and low line voltage. Quasi-Resonant Operation Figure 4 illustrates how valley signal triggers PWM. If no valley signal detected for a long time, the next PWM is triggered by a starter circuit at end of the interval (tSTART, 130s typ.) which starts at the rising edge of the previous PWM signal. A blanking time (tS(MIN), 8.5μs typ.), which starts at the rising edge of the previous PWM signal, limits minimum switching period. When the tS(MIN) interval is on-going, all of valley signals are not allowed to trigger the next PWM signal. After the end of the tS(MIN) interval, the coming valley will trigger the next PWM signal. If one or more valley signals are detected during the tS(MIN) interval and no valley is detected after the end of the tS(MIN) interval, the next PWM signal will be triggered automatically at end of the tS(MIN) + 5s (typ.). IQ1 IDOUT Figure 3. Key Waveforms of a Flyback Converter Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 4 is a registered trademark of Richtek Technology Corporation. DS7306D-01 September 2016 RT7306D KCC (V) ～ ～ Valley Signal ～ ～ PWM KCC(MAX) tSTART 0 VDIM_LOW V DIM_HIGH Valley Signal VDIM (V) Figure 5. Dimming Curve Protections PWM tS(MIN) LED Open-Circuit Protection In an event of output open circuit, the converter will be shut down to prevent being damaged, and it will be auto-restarted when the output is recovered. Once the Valley Signal PWM LED is open-circuit, the output voltage keeps rising, causing the voltage on ZCD pin VZCD rising accordingly. tS(MIN) Valley Signal PWM tS(MIN) 5μs When the sample-and-hold ZCD voltage (VZCD_SH) exceeds its OV threshold (VZCD_OVP, 3.2V typ.), output OVP will be activated and the PWM output (GD pin) will be forced low to turn off the main switch. If the output is still open-circuit when the converter restarts, the converter will be shut down again. Figure 4. PWM Triggered Method Output Diode Short-Circuit Protection HV Start-Up Device An in-house design 500V start-up device is integrated in the RT7306D to minimize the power loss and shorten the start-up time. The HV start-up device will be turned on during start-up period and be turned off during normal operation. It provides fast start-up time and no power loss in this path during normal operation. A 10k resistor is recommended to be connected in series with HV pin. Dimming Function An analog dimming function is embedded in the RT7306D. When the voltage on the DIM pin (VDIM) is within VDIM_LOW and VDIM_HIGH, the regulation factor of constant current control (KCC) is linearly proportional to VDIM, as shown in Figure 5. DIM pin sourcing a current (1A typ.) when VDD > VTH_ON, and the sourcing current is shut down after 100ms (typ.) Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS7306D-01 September 2016 When the output diode is damaged as short-circuit, the transformer will be led to magnetic saturation and the main switch will suffer from a high current stress. To avoid the above situation, an output diode short-circuit protection is built-in. When CS voltage VCS exceeds the threshold (VCS_SD 1.7 typ.) of the output diode short-circuit protection, the RT7306D will shut down the PWM output (GD pin) in few cycles to prevent the converter from damage. It will be auto-restarted when the failure condition is recovered. VDD Under-Voltage Lockout (UVLO) and Over-Voltage Protection (VDD OVP) The RT7306D will be enabled when VDD voltage (VDD) exceeds rising UVLO threshold (VTH_ON, 17V typ.) and disabled when VDD is lower than falling UVLO threshold (VTH_OFF, 8.5V typ.). When VDD exceeds its over-voltage threshold (VOVP, 37.4V typ.), the PWM output of the RT7306D is shut down. It will be auto-restarted when the VDD is recovered to a normal level. is a registered trademark of Richtek Technology Corporation. www.richtek.com 5 RT7306D Over-Temperature Protection (OTP) The RT7306D provides an internal OTP function to protect the controller itself from suffering thermal stress and permanent damage. It's not suggested to use the function as precise control of over temperature. Once the junction temperature is higher than the OTP threshold (TSD, 150C typ.), the controller will shut down until the temperature cools down by 30C (typ.). Meanwhile, if VDD reaches falling UVLO threshold voltage (VTH_OFF), the controller will hiccup till the over temperature condition is removed. Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 6 is a registered trademark of Richtek Technology Corporation. DS7306D-01 September 2016 RT7306D Absolute Maximum Ratings (Note 1)  HV Pin------------------------------------------------------------------------------------------------------------------- 0.3V to 500V  Supply Voltage, VDD ------------------------------------------------------------------------------------------------- 0.3V to 40V  Gate Driver Output, GD --------------------------------------------------------------------------------------------- 0.3V to 20V  Other Pins -------------------------------------------------------------------------------------------------------------- 0.3V to 6V  Power Dissipation, PD @ TA = 25C SOP-8 -------------------------------------------------------------------------------------------------------------------- 0.48W  Package Thermal Resistance (Note 2) SOP-8, JA -------------------------------------------------------------------------------------------------------------- 206.9C/W  Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------------- 260C  Junction Temperature ------------------------------------------------------------------------------------------------ 150C  Storage Temperature Range --------------------------------------------------------------------------------------- 65C to 150C  ESD Susceptibility (Note 3) HBM (Human Body Model) (Except HV pin)-------------------------------------------------------------------- 2kV Recommended Operating Conditions (Note 4)  Supply Input Voltage, VDD ----------------------------------------------------------------------------------------- 11V to 34V  COMP Voltage, VCOMP --------------------------------------------------------------------------------------------- 0.7V to 4.3V  Junction Temperature Range -------------------------------------------------------------------------------------- 40C to 125C Electrical Characteristics (VDD = 15V, TA = 25C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit 1 -- -- mA -- -- 30 A 35.4 37.4 39.4 V 16 7.5 17 8.5 18 9.5 V V VTH_FR VDD_ET --- 6 10 --- V V VDD Holdup Mode Ending Point VDD_ED -- 10.5 -- V VDD = 15V, IZCD = 0, GD open -- 2 3 mA VDD = VTH_OFF -- 60 -- A IVDD_ST VDD = VTH_ON  1V -- 15 30 A Lower Clamp Voltage VZCDL IZCD = 0 to 2.5mA 50 0 60 mV ZCD OVP Threshold Voltage VZCD_OVP 3.04 3.2 3.36 V HV Section HV Start-Up Average Current IHV_ST Off State Leakage Current VDD < VTH_ON, VHV = 100V VDD = VTH_ON + 1V, VHV = 500V VDD Section VDD OVP Threshold Voltage VOVP VDD Rising Rising UVLO Threshold Voltage VTH_ON Falling UVLO Threshold Voltage VTH_OFF Fault Released Voltage VDD Holdup Mode Entry Point Operating Current IDD_OP Operating Current at Shutdown Start-Up Current ZCD Section Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS7306D-01 September 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 7 RT7306D Parameter Symbol Test Conditions Min Typ Max Unit 250 300 350 mV -- 2.8 -- V 0.5 1 2 A 246.25 250 253.75 mV 5 5.5 -- V VCOMP(MIN) -- 0.5 -- V ICOMP(MAX) During start-up period -- 100 -- A 240 400 570 ns Peak Current Shutdown Voltage VCS_SD Threshold 1.53 1.7 1.87 V Peak Current Limitation at Normal Operation VCS_CL 1.08 1.2 1.32 V Propagation Delay Compensation Factor KPC ICS = KPC x IZCD, IZCD = 150A -- 0.042 -- A/A Rising Time tR VDD = 15V, CL = 1nF -- 140 250 ns Falling Time tF VDD = 15V, CL = 1nF -- 40 70 ns Gate Output Clamping Voltage VCLAMP VDD = 15V, CL = 1nF 10.8 12 13.2 V Internal Pull Low Resistor RGD -- 40 -- k 0.9 1.25 1.6 s Dimming Control Section Analog Dimming Low Threshold Voltage VDIM_LOW Analog Dimming High Threshold VDIM_HIGH Voltage DIM Sourcing Current Constant Current Control Section Maximum Regulated Factor for Constant-Current Control KCC(MAX) Maximum Comp Voltage VCOMP(MAX Minimum Comp Voltage Maximum Sourcing Current VDIM = 3V ) Current Sense Section Leading Edge Blanking Time tLEB Gate Driver Section Timing Control Section IZCD = 150A Minimum On-Time tON(MIN) Minimum Switching Period tS(MIN) 7 8.5 10 s Duration of Starter at Normal Operation tSTART 75 130 300 s Maximum On-Time tON(MAX) 29 47 65 s Over-Temperature Protection (OTP) Section OTP Temperature Threshold TOTP (Note 5) -- 150 -- C OTP Temperature Hysteresis TOTP-HYS (Note 5) -- 30 -- C Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. JA is measured under natural convection (still air) at TA = 25C with the component mounted on a low effective-thermal-conductivity two-layer test board on a JEDEC thermal measurement standard. Note 3. Devices are ESD sensitive. Handling precaution recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. Guarantee by design. Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 8 is a registered trademark of Richtek Technology Corporation. DS7306D-01 September 2016 RT7306D Typical Application Circuit Flyback Application Circuit RSN3 F1 TX1 BD CSN2 DOUT + Line COUT CIN RHV CSN1 ～ ～ VOUT RSN1 Neutral - DSN Analog Dimming Signal 1 HV 4 DIM 8 GD RG 7 RGP RT7306D VDD CVDD 3 CCOMP 5 Q1 RPC 6 CS COMP ZCD RCS 2 GND DAUX RAUX RZCD1 CZCD RZCD2 Buck-Boost Application Circuit F1 TX1 BD - Line DOUT RHV CIN COUT ～ VOUT ～ + Neutral Analog Dimming Signal 4 8 1 HV 5 Q1 RGP RT7306D VDD CS 3 7 RG DIM CVDD CCOMP GD 6 RCS COMP ZCD RAUX RPC GND 2 DAUX RZCD1 CZCD Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS7306D-01 September 2016 RZCD2 is a registered trademark of Richtek Technology Corporation. www.richtek.com 9 RT7306D Typical Operating Characteristics IHV_ST vs. Junction Temperature VOVP vs. Junction Temperature 36.7 5 36.6 4 VOVP (V) I HV_ST (mA) 36.5 3 2 36.4 36.3 36.2 1 36.1 36.0 0 -50 -25 0 25 50 75 100 -50 125 -25 Junction Temperature (°C) 25 50 75 100 125 VTH_OFF vs. Junction Temperature VTH_ON vs. Junction Temperature 8.60 17.15 17.10 8.56 17.05 VTH_OFF (V) VTH_ON (V) 0 Junction Temperature (°C) 17.00 16.95 8.52 8.48 8.44 16.90 8.40 16.85 -50 -25 0 25 50 75 100 -50 125 -25 Junction Temperature (°C) 0 25 50 75 100 125 Junction Temperature (°C) VZCDL vs. Junction Temperature IDD_OP vs. Junction Temperature 25 2.00 1.95 20 VZCDL (mV) I DD_OP (mA) 1.90 1.85 1.80 15 10 1.75 5 1.70 0 1.65 -50 -25 0 25 50 75 100 Junction Temperature (°C) Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 10 125 -50 -25 0 25 50 75 100 125 Junction Temperature (°C) is a registered trademark of Richtek Technology Corporation. DS7306D-01 September 2016 RT7306D KCC vs. Junction Temperature 260 380 258 KCC (mV) VDIM_LOW (V) VDIM_LOW vs. Junction Temperature 400 360 256 254 340 252 320 -50 -25 0 25 50 75 100 -50 125 -25 25 50 75 100 125 ICOMP(MAX) vs. Junction Temperature VCOMP(MAX) vs. Junction Temperature 5.26 140 5.24 120 5.22 100 I COMP(MAX) (μA) VCOMP(MAX) (V) 0 Junction Temperature (°C) Junction Temperature (°C) 5.20 5.18 80 60 5.16 40 5.14 20 0 5.12 -50 -25 0 25 50 75 100 -50 125 -25 Junction Temperature (°C) 0 25 50 75 100 125 Junction Temperature (°C) VCS_SD vs. Junction Temperature tLEB vs. Junction Temperature 500 1.850 480 VCS_SD (V) tLEB (ns) 1.825 460 440 1.800 1.775 420 400 1.750 -50 -25 0 25 50 75 100 Junction Temperature (°C) Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS7306D-01 September 2016 125 -50 -25 0 25 50 75 100 125 Junction Temperature (°C) is a registered trademark of Richtek Technology Corporation. www.richtek.com 11 RT7306D VCS_CL vs. Junction Temperature KPC vs. Junction Temperature 0.045 1.30 0.044 1.26 KPC (A/A) VCS_CL (V) 1.28 1.24 0.043 0.042 1.22 0.041 1.20 0.040 1.18 -50 -25 0 25 50 75 100 -50 125 -25 Junction Temperature (°C) tON(MIN) vs. Junction Temperature 25 50 75 100 125 tSTART vs. Junction Temperature 1.30 150 1.25 140 130 tSTART (μs) tON(MIN) (μs) 0 Junction Temperature (°C) 1.20 1.15 1.10 120 110 100 1.05 90 -50 -25 0 25 50 75 100 125 Junction Temperature (°C) -50 -25 0 25 50 75 100 125 Junction Temperature (°C) tON(MAX) vs. Junction Temperature 60 tON(MAX) (μs) 50 40 30 20 10 0 -50 -25 0 25 50 75 100 125 Junction Temperature (°C) Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 12 is a registered trademark of Richtek Technology Corporation. DS7306D-01 September 2016 RT7306D Application Information Output Current Setting Considering the conversion efficiency, the programmed DC level of the average output current (IOUT(t)) can be derived as : IOUT_CC  1  NP  KCC  CTRTX1 2 NS RCS CTRTX1  ISEC_PK NS  IPRI_PK NP RCS  1  NP  KCC  CTRTX1 2 NS IOUT_CC Propagation Delay Compensation Design The VCS deviation (VCS) caused by propagation delay effect can be derived as: V  t R VCS  IN D CS , Lm in which tD is the delay period which includes the propagation delay of the RT7306D and the turn-off transition of the main MOSFET. The sourcing current from CS pin of the RT7306D (ICS) can be expressed as : N ICS  KPC  VIN  A  1 NP RZCD1 where NA is the turns number of the auxiliary winding. RPC can be designed by : VCS tD  RCS  RZCD1 NP   ICS Lm  KPC NA When GD pin is turned off, CS pin sources a current (100A, typ.) flowing through RPC and RCS. If the voltage on CS pin is lower than its under voltage threshold (50mV, typ.), CS under voltage protection (UVP) will be triggered and the GD pin will be forced Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS7306D-01 September Thus, RPC must be higher than 750 to prevent false triggering CS UVP. In addition, RPC is recommended to be higher than 1.5k if the ambient temperature will be lower to 40C Feed-Forward Compensation Design in which CTRTX1 is the current transfer ratio of the transformer TX1, ISEC_PK is the peak current of the secondary side, and IPRI_PK is the peak current of the primary side. CTRTX1 can be estimated to be 0.9. According to the above parameters, current sense resistor RCS can be determined as the following equation : RPC  low to turn off the main switch. 2016 The COMP voltage, VCOMP, is a function of the resistor RZCD1 as following : RZCD1  tON   Gm ramp  tON  t  N S     A =  VIN_pk   KIV   NP 2  Cramp   VCOMP  VD    in which KIV, Gmramp, and Cramp are fixed parameters in the RT7306D, and the typical value are : KIV = 2.5V/mA, Gmramp = 8A/V, Cramp = 6.5pF. VD is the offset of the constant on-time comparator, and its typical value is 0.63V. It is recommended to design VCOMP = 2 to 3V. If the COMP voltage is over its recommended operating range (0.7 to 4.3V), output current regulation may be affected. Thus, the resistors RZCD1 can be determined according to the above parameters. Minimum On-Time Setting The RT7306D limits a minimum on-time (tON(MIN)) for each switching cycle. The tON(MIN) can be derived from the following equations. tON(MIN)  IZCD_SH  187.5p  sec  A (typ.) Thus, RZCD1 can be determined by: RZCD1  tON(MIN)  VIN NA  (typ.) 187.5p NP In addition, the current flowing out of ZCD pin must be lower than 2.5mA (typ.). Thus, the RZCD1 is also determined by : RZCD1  2  VAC(MAX) NA  2.5m NP where the VAC(MAX) is maximum input AC voltage. is a registered trademark of Richtek Technology Corporation. www.richtek.com 13 RT7306D Output Over-Voltage Protection Setting Output OVP is achieved by sensing the voltage on the auxiliary winging. It is recommended that output OV level (VOUT_OVP) is set at 120% of nominal output voltage (VOUT). Thus, RZCD1 and RZCD2 can be determined by the equation as : RZCD2 N VOUT  A   120%  3.2V(typ.) NS RZCD1  RZCD2 For continuous operation, the maximum operating junction temperature indicated under Recommended Operating Conditions is 125C. The junction-to-ambient thermal resistance,JA, is highly package dependent. For a SOP-8 package, the thermal resistance, JA, is 206.9°C/W on a standard JEDEC low effective-thermal-conductivity two-layer test board. The maximum power dissipation at TA = 25C can be calculated as below : PD(MAX) = (125C 25C) / (206.9°C/W) = 0.48W for a SOP-8 package. When the MOSFET is turned off, the leakage inductance of the transformer and parasitic capacitance (COSS) of the MOSFET induce resonance waveform on the ZCD pin. The resonance waveform may make the controller false trigger the ZCD OVP, and it may cause the controller operate in unstable condition. As load increases, the resonance time also increases. It is recommended to add a 10pF to 47pF bypass capacitor, and it should be as close to ZCD pin as possible. The larger bypass capacitor may cause phase shift on ZCD waveform, so the MOSFET is not turned on at exact valley point. To avoid the above issue, the RT7306D provides adaptive blanking time (tBK). It varies with the peak voltage of the CS pin (VCS_PK), as shown by the following formula : tBK = 2s + VCS_PK x 2s/V (typ.) The maximum power dissipation depends on the operating ambient temperature for the fixed TJ(MAX) and the thermal resistance, JA. The derating curves in Figure 6 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. 0.6 Maximum Power Dissipation (W)1 Adaptive Blanking Time Two-Layer PCB 0.5 0.4 0.3 0.2 0.1 0.0 0 25 50 75 100 125 Ambient Temperature (°C) Thermal Considerations Figure 6. Derating Curve of Maximum Power The junction temperature should never exceed the absolute maximum junction temperature TJ(MAX), listed Dissipation under Absolute Maximum Ratings, to avoid permanent damage to the device. The maximum allowable power dissipation depends on the thermal resistance of the IC package, the PCB layout, the rate of surrounding airflow, and the difference between the junction and ambient temperatures. The maximum power dissipation can be calculated using the following formula : PD(MAX) = (TJ(MAX) TA) / JA where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and JA is the junction-to-ambient thermal resistance. Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 14 is a registered trademark of Richtek Technology Corporation. DS7306D-01 September 2016 RT7306D Layout Considerations  The path(5) from input capacitor to HV pin is a high voltage loop. Keep a space from path(5) to other low voltage traces.  It is good for reducing noise, output ripple and EMI issue to separate ground traces of input capacitor(a), MOSFET(b), auxiliary winding(c) and IC control circuit(d). Finally, connect them together on input capacitor ground(a). The areas of these ground traces should be kept large.  To minimize parasitic trace inductance and EMI, minimize the area of the loop connecting the secondary winding, the output diode, and the output filter capacitor. In addition, apply sufficient copper A proper PCB layout can abate unknown noise interference and EMI issue in the switching power supply. Please refer to the guidelines when designing a PCB layout for switching power supply :  The current path(1) from input capacitor, transformer, MOSFET, RCS return to input capacitor is a high frequency current loop. The path(2) from GD pin, MOSFET, RCS return to the ground of the IC is also a high frequency current loop. They must be as short as possible to decrease noise coupling and kept a space to other low voltage traces, such as IC control circuit paths, especially. Besides, the path(3) between MOSFET ground(b) and IC ground(d) is recommended to be as short as possible, too.  area at the anode and cathode terminal of the diode for heat-sinking. It is recommended to apply a larger area at the quiet cathode terminal. A large anode area will induce high-frequency radiated EMI. The path(4) from RCD snubber circuit to MOSFET is a high switching loop. Keep it as small as possible. Line ～ ～ CIN Neutral (4) (5) (a) HV GD DM RT7306D VDD CVDD CS CCOMP COMP ZCD (2) (1) GND (d) (3) Input Capacitor Ground (a) (b) Trace Trace IC Ground (d) Trace Auxiliary Ground (c) MOSFET Ground (b) (c) Figure 7. PCB Layout Guide Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS7306D-01 September 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 15 RT7306D Outline Dimension Dimensions In Millimeters Symbol Dimensions In Inches Min Max Min Max A 4.801 5.004 0.189 0.197 B 3.810 3.988 0.150 0.157 C 1.346 1.753 0.053 0.069 D 0.330 0.508 0.013 0.020 F 1.194 1.346 0.047 0.053 H 0.170 0.254 0.007 0.010 I 0.050 0.254 0.002 0.010 J 5.791 6.200 0.228 0.244 M 0.400 1.270 0.016 0.050 8-Lead SOP Plastic Package Copyright © 2016 Richtek Technology Corporation. All rights reserved. www.richtek.com 16 is a registered trademark of Richtek Technology Corporation. DS7306D-01 September 2016 RT7306D Footprint Information Package Footprint Dimension (mm) Number of Pin SOP-8 8 Tolerance P A B C D M 1.27 6.80 4.20 1.30 0.70 4.51 ±0.10 Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. Copyright © 2016 Richtek Technology Corporation. All rights reserved. DS7306D-01 September 2016 is a registered trademark of Richtek Technology Corporation. www.richtek.com 17