RT7737
Programmable Burst Switching Green Mode/Burst Mode
Level Flyback Controller
General Description
Features
The RT7737 series are enhanced high efficient PWM
flyback controller with proprietary SmartJitterTM
technology. The innovative SmartJitterTM technology
not only reduces the EMI emissions of SMPS when the
system enters burst switching green mode, but also
eliminates the output jittering ripple. Also, the RT7737
series feature programmable burst switching green
mode and burst mode level for adopting different
application requirements to optimize the product
performance. To meet the stringent trend toward
performance, the RT7737 series are the best choice for
product designers.
The RT7737 is available in SOT-23-6 package. It is a
current mode PWM controller providing comprehensive
protection functions, including an input Under-Voltage
Lockout (UVLO), a VDD Over-Voltage Protection
(OVP), an Over-Load Protection (OLP), a Secondary
Rectifier Sort Protection (SRSP), a CS pin open
protection and a cycle-by-cycle current limit. With the
Proprietary SmartJitterTM Technology
Reducing EMI Emissions of SMPS
Output Jittering Ripple Elimination
Programmable Burst Switching Green Mode
Level
Programmable Burst Mode Level
Accurate Over Load Protection
Driver Capability : 200mA/300mA
High Noise Immunity
Applications
Switching AC/DC Adaptor
DVD Open Frame Power Supply
Set-Top Box (STB)
ATX Standby Power
TV/Monitor Standby Power
PC Peripherals
NB Adaptor
above features, the RT7737 is a cost-effective and
compact solution for AC/DC products.
Simplified Application Circuit
Vo+
+
+
Mains
(90V to 265V)
Vo-
BURST
VDD
GATE
COMP RT7737
RBS
RCS_RC
CS
GND
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS7737-00
September
2014
is a registered trademark of Richtek Technology Corporation
www.richtek.com
1
RT7737
Marking Information
Ordering Information
RT7737
RT7737GGE
Package Type
E : SOT-23-6
0U=DNN
0U= : Product Code
DNN : Date Code
Lead Plating System
G : Green (Halogen Free and Pb Free)
RT7737LGE
RT7737 Version (Refer to Version Table)
0S=DNN
Note :
0S= : Product Code
DNN : Date Code
Richtek products are :
RT7737AGE
RoHS compliant and compatible with the current
requirements of IPC/JEDEC J-STD-020.
0V=DNN
0V= : Product Code
DNN : Date Code
Suitable for use in SnPb or Pb-free soldering processes.
RT7737HGE
0T=DNN
0T= : Product Code
DNN : Date Code
RT7737 Version Table
Version
RT7737G
RT7737L
RT7737A
RT7737H
Frequency (f OSC)
65kHz
65kHz
65kHz
100kHz
OLP Delay Time @ fOSC
55ms
55ms
28ms
36ms
Internal OVP
Auto Recovery
Latch
Latch
Auto Recovery
OLP & SRSP
Auto Recovery
Auto Recovery
Latch
Auto Recovery
BURST Pin High
Latch
Latch
Latch
Latch
BURST Pin Low
Auto Recovery
Auto Recovery
Latch
Auto Recovery
Pin Configurations
(TOP VIEW)
GATE VDD CS
6
5
4
2
3
GND COMP BURST
SOT-23-6
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is a registered trademark of Richtek Technology Corporation
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RT7737
Functional Pin Description
Pin No.
Pin Name
Pin Function
1
GND
Ground of the Controller.
2
COMP
Feedback Voltage Input. Connect an opto-coupler to close the control loop and
achieve output voltage regulation.
3
BURST
Burst Mode Level Setting.
4
CS
Current Sense Input. The current sense resistor between this pin and GND is used
for current limit setting.
5
VDD
Supply Voltage Input. The controller will be enabled when VDD exceeds V TH_ON
and disabled when VDD decreases lower than VTH_OFF.
6
GATE
Gate Driver Output for External Power MOSFET.
Function Block Diagram
VDD
IBias
VL_TH
+
OVP
-
BURST
-
+
VH_TH
VOVP
POR
-
Shutdown
Logic
Secondary Rectifier
Short Protection
-
VSRSP_TH
+
OTP
+
UVLO
-
VTH_ON/OFF
Bias &
Bandgap
+
Counter
COMP Open
Sensing
Dmax
Constant
Power
VCOMP_OP
CS
Oscillator
OLP
Burst Switching
Green Mode
Selector
Soft Driver
S
COMP
Slope
Ramp
+
PWM
Comparator
Q
GND
Burst Switching
Green Mode
LEB
X3
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS7737-00
September
2014
GATE
R
COMP
VBURL
VBURH
VDD
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3
RT7737
Preliminary
Operation
Burst Switching Green Mode
BURST Pin – Programmable Burst Mode Level
The burst mode is designed to reduce switching loss at
light load condition. When the output load gets light, the
COMP voltage drops and reaches VBURL, the controller
will cease switching. After the output voltage drops and
the COMP voltage goes up to VBURH, the controller will
resume switching.
The burst mode level can be set by connecting a
recommended resistor on the BURST pin and GND to
decide the burst mode threshold.
VDD Holdup Mode
The RT7737 provides a unique operation mode at
almost no load condition named VDD holdup mode.
Under the VDD holdup mode, the RT7737 forces PWM
switching to maintain VDD voltage between VDD_ET and
VDD_ED. The benefit of the VDD holdup mode is to
avoid the VDD drops to VTH_OFF due to the long burst
mode period at no load or load transient moment.
Therefore, this function makes bias winging design and
transient design easier and compacter.
Oscillator
The oscillator runs at 65kHz and features frequency
jittering function. The saw-tooth slope compensation,
maximum duty cycle pulse and over-load protection
slope are built-in. Its jitter depth is proportion of
oscillator frequency where f is frequency jittering
range, and TJIT is frequency jittering period.
Leading Edge Blanking (LEB)
To prevent unexpectedly gate switching interruption
from the initial spike on CS pin, the LEB delay is
designed to block this spike at the beginning of gate
switching.
Gate Driver
A totem pole gate driver is designed to meet both EMI
and efficiency requirements in low power applications.
An internal pull-low circuit is activated after pretty low
VDD to prevent external MOSFET from accidentally
turning on during UVLO.
Programmable Burst Switching Green Mode Level
The burst switching green mode level can be set by
connecting a recommended resistor between the CS
pin and the current sense resistor.
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Over-Load Protection
In over-load conditions, current limit for a long time will
lead to system thermal stress problem. To further
protect the system, the RT7737 is designed with a
proprietary prolonged turn-off period during hiccup. The
power loss and temperature during OLP are averaged
to an acceptable level over the ON/OFF cycle.
CS Pin Open Protection
When the CS pin is opened, the controller will shut
down after a few cycles.
Internal VDD Over-Voltage Protection
Output voltage can be roughly sensed by the VDD pin.
If the sensed voltage reaches VOVP threshold, the
controller shuts down after deglitch delay.
Feedback Open or Opto-Coupler Short
If the output voltage feedback loop is open or the
opto-coupler is shorted, the OVP/OLP function will be
triggered depending on which one occurs first.
Secondary Rectifier Short Protection
The current spike during secondary rectifier short test
is extremely high because of the saturated main
transformer. Meanwhile, the transformer acts like a
leakage inductance. During high line, the current in
power MOSFET is sometimes too high in OLP delay
time. To offer better and easier protection design, the
RT7737 shuts down after a few of cycles before fuse is
impacted.
Output Short Protection
The RT7737 implements output short protection by
detecting GATE width and delay time. It can minimize
the power loss and temperature during output short,
especially at high line input voltage.
is a registered trademark of Richtek Technology Corporation
DS7737-00
September 2014
RT7737
Absolute Maximum Ratings
(Note 1)
Supply Input Voltage, VDD to GND ------------------------------------------------------------------------------- 0.3V to 30V
GATE to GND ---------------------------------------------------------------------------------------------------------- 0.3V to 16.5V
BURST, COMP, CS to GND ---------------------------------------------------------------------------------------- 0.3V to 6.5V
Power Dissipation, PD @ TA = 25C
SOT-23-6 ---------------------------------------------------------------------------------------------------------------- 0.38W
Package Thermal Resistance
(Note 2)
SOT-23-6, θJA ---------------------------------------------------------------------------------------------------------- 260.7C/W
Junction Temperature ------------------------------------------------------------------------------------------------ 150C
Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------------- 260C
Storage Temperature Range --------------------------------------------------------------------------------------- 65C to 150C
ESD Susceptibility
(Note 3)
HBM (Human Body Model) ----------------------------------------------------------------------------------------- 2.5kV
MM (Machine Model) ------------------------------------------------------------------------------------------------- 250V
Recommended Operating Conditions
(Note 4)
Supply Input Voltage, VDD ------------------------------------------------------------------------------------------- 12V to 25V
Recommended Resistance on the BURST Pin ----------------------------------------------------------------- 10k to 60k
Junction Temperature Range---------------------------------------------------------------------------------------- 40C to 125C
Ambient Temperature Range ---------------------------------------------------------------------------------------- 40C to 85C
Electrical Characteristics
(VDD = 15V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
VDD Section
VDD Over-Voltage Protection
Level
VOVP
26
27
28
V
VDD Zener Clamp
VZ
29
--
--
V
On Threshold Voltage
VTH_ON
RT7737G/L/H
12.5
13.5
14.5
RT7737A
14.5
15.5
16.5
Off Threshold Voltage
VTH_OFF
8.5
9
9.5
V
VDD Holdup Mode Entry Point
VDD_ET
VCOMP < 1.3V
9.5
10
10.5
V
VDD Holdup Mode Ending
Point
VDD_ED
VCOMP < 1.3V
10
10.5
11
V
Latch-off Clamping Voltage
VDD_LH
--
6
--
V
--
5.5
--
V
Threshold Voltage for Latch-off
VLH_OFF
Release
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
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2014
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RT7737
Preliminary
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Start-up Current
IDD_ST
VDD < VTH_ON 0.1V， RT7737G/L/H
TA = 40C to 85C
RT7737A
--
5
10
--
5
12
Latch-off Operating Current
IDD_LH
TA = 40C to 85C
RT7737G/L/H
--
--
10
RT7737A
--
--
12
IDD_OP1
GATE pin open，VCOMP = 2.5V
--
1
--
IDD_OP2
GATE pin open，VCOMP = 1.7V
--
0.9
--
IDD_ARP
During entering auto recovery
protection, TA = 40C to 85C
350
550
750
Normal PWM Frequency
fOSC
VCOMP > VBS_ET
RT7737G/L/A
60
65
70
RT7737H
92
100
108
Maximum Duty Cycle
DCYmax
70
75
80
Minimum Burst Switching
Frequency
f BS_MIN
18.5
22
25.5
20
25
30
PWM Frequency Jittering
Range
f
--
±6
--
PWM Frequency Jittering
Period
TJIT
fOSC = 65kHz
--
16
--
fOSC = 100kHz
--
10.4
--
Frequency Variation
VDD Deviation
f DV
VDD = 9V to 23V
--
--
2
%
TA = 30C to 105C
--
--
5
%
5
5.2
5.4
V
0.24
0.29
0.34
mA
Operating Supply Current
IDD Sinking Current
A
A
mA
A
Oscillator Section
Versus
Frequency Variation Versus
f DT
Temperature Deviation
RT7737G/L/A
VCOMP < VBS_ED
RT7737H
kHz
%
kHz
%
ms
COMP Input Section
Open Loop Voltage
VCOMP_OP COMP pin open
Short Circuit Current of COMP IZERO
Delay Time of COMP
Open-loop Protection
Burst Switching Green Mode
Entry Voltage
Burst Switching Green Mode
Ending Voltage
TOLP
VBS_ET
VBS_ED
VCOMP = 0V
fOSC = 65kHz
RT7737G/L
--
55
--
fOSC = 65kHz
RT7737A
--
28
--
fOSC = 100kHz
RT7737H
--
36
--
RCS_RC = 750
--
2.75
--
RCS_RC = 510
--
2.65
--
RCS_RC = 330
--
2.55
--
RCS_RC = 200
--
2.45
--
RCS_RC = 100
--
2.35
--
RCS_RC = 750
--
2.35
--
RCS_RC = 510
--
2.25
--
RCS_RC = 330
--
2.15
--
RCS_RC = 200
--
2.05
--
RCS_RC = 100
--
1.95
--
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
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ms
V
V
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RT7737
Parameter
Symbol
Delay Time of Output Short
Protection
TD_OSP
Test Conditions
Min
Typ
Max
RT7737G/L/A; f OSC = 65kHz
--
8
--
RT7737H; f OSC = 100kHz
--
5.2
--
Unit
ms
Current Sense Section
Maximum Current Limit
VCS_MAX
(Note 6)
1.05
1.1
1.15
V
Leading Edge Blanking Time
TLEB
(Note 5)
250
400
550
ns
Internal
Time
TPD
(Note 5)
--
100
--
ns
350
500
650
ns
1.9
2
2.1
2.5
2.6
2.7
fOSC = 65kHz
0.9
1.1
1.3
fOSC = 100kHz
0.5
0.65
0.8
Propagation
Delay
Minimum On-Time
TON_MIN
SRSP Threshold Voltage
VSRSP_TH
Detection On-Time of Output
Short Protection
TON_OSP
RT7737G/L/A
RT7737H
(Note 6)
(Note 6)
V
s
GATE Section
Rising Time
TR
CL = 1nF
--
250
--
ns
Falling Time
TF
CL = 1nF
--
40
--
ns
VDD = 23V
--
14
--
V
Gate Output Clamping Voltage VCLAMP
BURST Pin
High-Level Threshold Voltage
VH_TH
2.95
3
3.05
V
Low-Level Threshold Voltage
VL_TH
0.25
0.3
0.35
V
Burst Mode Entry Voltage
VBURST_ET
RBS = 60k
--
1.65
--
RBS = 10k
--
1.15
--
Burst Mode Ending Voltage
VBURST_ED
RBS = 60k VBURST_ED =
RBS = 10k VBURST_ET + 0.2V
--
1.85
--
--
1.35
--
V
V
Over-Temperature Protection (OTP) Section
OTP Before Turn On
TOTP_INTH Built-in OTP
(Note 6)
--
120
--
C
OTP After Turn On
TOTP_STTH Built-in OTP
(Note 6)
--
140
--
C
Note 1. Stresses beyond those listed ”Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect
device reliability.
Note 2. θJA is measured in natural convection (still air) at TA = 25°C with the component mounted on a low effective thermal
conductivity test board of JEDEC 51-3 thermal measurement standard.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. Leading edge blanking time and internal propagation delay time are guaranteed by design.
Note 6. Guaranteed by design.
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS7737-00
September
2014
is a registered trademark of Richtek Technology Corporation
www.richtek.com
7
RT7737
Preliminary
Typical Application Circuit
Vo+
+
+
Mains
(90V to 265V)
Vo-
(Optional)
5
VDD
RBS
3 BURST
GATE 6
2
COMP RT7737
CS 4
RCS_RC
GND
1
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is a registered trademark of Richtek Technology Corporation
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September 2014
RT7737
Typical Operating Characteristics
IDD_ST vs. VDD
IDD_ST vs. Temperature
10
3.0
2.5
8
I DD_ST (µA)
I DD_ST (µA)
2.0
1.5
1.0
6
4
2
0.5
0
0.0
0
3
6
9
12
-50
15
-25
0
VDD (V)
25
50
75
100
125
Temperature (°C)
IDD_LH vs. Temperature
VDD_LH & VLH_OFF vs. Temperature
8
6.8
VDD_LH & VLH_OFF (V)
6.6
I DD_LH (µA)
6
4
2
6.4
6.2
VDD_LH
6.0
5.8
5.6
5.4
VLH_OFF
5.2
5.0
0
4.8
-50
-25
0
25
50
75
100
125
-50
-25
0
Temperature (°C)
25
50
75
100
125
100
125
Temperature (°C)
VTH_ON vs. Temperature
VTH_OFF vs. Temperature
16.0
10.0
15.5
9.5
VTH_OFF (V)
VTH_ON (V)
15.0
14.5
14.0
9.0
8.5
13.5
13.0
8.0
-50
-25
0
25
50
75
100
Temperature (°C)
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS7737-00
September
2014
125
-50
-25
0
25
50
75
Temperature (°C)
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RT7737
Preliminary
IDD_OP1 vs. Temperature
IDD_OP2 vs. Temperature
1200
1000
950
900
I DD_OP2 (µA)
I DD_OP1 (µA)
1100
1000
900
850
800
800
750
700
700
-50
-25
0
25
50
75
100
125
-50
-25
0
Temperature (°C)
25
50
75
100
125
100
125
Temperature (°C)
IDD_ARP vs. Temperature
VOVP vs. Temperature
28.0
650
600
VOVP (V)
I DD_ARP (µA)
27.5
550
500
27.0
450
26.5
400
26.0
350
-50
-25
0
25
50
75
100
-50
125
-25
0
25
50
75
Temperature (°C)
Temperature (°C)
fOSC vs. VDD
fOSC vs. Temperature
66.0
68
RT7737G/L/A
RT7737G/L/A
66
f OSC (kHz)
f OSC (kHz) 1
65.5
65.0
64.5
62
64.0
60
10
12.5
15
17.5
20
22.5
VDD (V)
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10
64
25
-50
-25
0
25
50
75
100
125
Temperature (°C)
is a registered trademark of Richtek Technology Corporation
DS7737-00
September 2014
RT7737
fOSC vs. VDD
fOSC vs. Temperature
101.0
106
RT7737H
RT7737H
102
f OSC (kHz)
f OSC (kHz)
100.5
100.0
99.5
98
94
99.0
90
10
12.5
15
17.5
20
22.5
25
-50
-25
0
VDD (V)
fBS_MIN vs. Temperature
75
100
125
28
RT7737G/L/A
RT7737H
24
26
f BS_MIN (KHz)
f BS_MIN (kHz)
50
fBS_MIN vs. Temperature
26
22
20
24
22
18
20
-50
-25
0
25
50
75
100
125
-50
-25
0
Temperature (°C)
25
50
75
100
125
100
125
Temperature (°C)
VCOMP_OP vs. Temperature
IZERO vs. Temperature
5.6
320
5.4
300
I ZERO (µA)
VCOMP_OP (V)
25
Temperature (°C)
5.2
280
260
5.0
240
4.8
-50
-25
0
25
50
75
100
Temperature (°C)
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS7737-00
September
2014
125
-50
-25
0
25
50
75
Temperature (°C)
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11
RT7737
Preliminary
TOLP vs. Temperature
TOLP vs. Temperature
65
44
RT7737H
RT7737G/L
60
TOLP (ms)
TOLP (ms)
40
55
36
32
50
-50
-25
0
25
50
75
100
-50
125
-25
0
50
75
100
125
100
125
VH_TH vs. Temperature
TOLP vs. Temperature
35.0
3.2
RT7737A
32.5
3.1
VH_TH (V)
TOLP (ms)
25
Temperature (°C)
Temperature (°C)
30.0
27.5
3.0
2.9
25.0
2.8
-50
-25
0
25
50
75
100
125
Temperature (°C)
-50
-25
0
25
50
75
Temperature (°C)
VL_TH vs. Temperature
0.40
VL_TH (V)
0.35
0.30
0.25
0.20
-50
-25
0
25
50
75
100
125
Temperature (°C)
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is a registered trademark of Richtek Technology Corporation
DS7737-00
September 2014
RT7737
Application Information
SmartJitterTM Technology
VCOMP and the PWM switching frequency, and a new
The RT7737 series applies RICHTEK proprietary
SmartJitterTM technology.
stable equilibrium point is eventually reached after
back-and-forth adjustments. It is mutually-affected by
VCOMP and PWM switching frequency and limits the
frequency jittering. As a result, EMI improvement
function worsens, as show in Figure 1.
In order to reduce switching loss for lower power
consumption during light load or no load, general PWM
controllers have green mode function.
The output power equation is :
2
x V
PO_DCM (VCOMP ) 1 Lp ( 1 COMP ) fS (VCOMP ) η
2
RCS
Where LP is the magnetizing inductance of the
transformer, RCS is the current sense resistor, VCOMP
is the feedback voltage of the COMP pin. f S is the
switching frequency of the power switch, is the
conversion efficiency, and x 1 is a constant coefficient.
Output power is a function of feedback voltage VCOMP.
Frequency jittering technique is typically used to
improve EMI problems in general PWM controllers, and
the frequency jittering period is based on PWM
switching frequency.
The innovative SmartJitterTM technology not only helps
reduce EMI emissions of SMPS when the system
enters green mode, but also eliminates output jittering
ripple.
Accurate Over-Load Protection and Tight Current
Limit Tolerance
Generally, the saw current limit is applied to low cost
flyback controllers because of simple design. The
RT7737 series applies RICHTEK proprietary
technology through well foundry control, design and
test/trim mode in final test to make the current limit
tolerance tight enough to make design and mass
production easier, and it provides accurate over-load
protection.
When the system enters green mode, a output power
relationship is formed between the feedback voltage
Jittering Freq.
General PWM Controller
Normal Operating
RT7737
Normal Operating
fs mean = 64.85kHz
Jittering Range =
Jittering Freq.
Jittering Freq.
fs mean = 64.61kHz
Jittering Range =
6.3%
General PWM Controller
Green Mode
Jittering Freq.
6.0%
RT7737
Green Mode
fs mean = 42.99kHz
Jittering Range =
3.3%
fs mean = 42.58kHz
Jittering Range =
7.7%
Figure 1. Frequency Jittering Range During Green Mode : General PWM Controller vs. RT7737
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS7737-00
September
2014
is a registered trademark of Richtek Technology Corporation
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13
RT7737
Preliminary
CS Pin - Programmable Burst Switching Green
Mode Level
When the VDD reaches the threshold voltage VTH_ON,
the RT7737 starts to operate. Before the GATE starts
to operate, the RT7737 sets the burst switching green
mode thresholds (VBS_ET and VBS_ED) first. The IC
provides a sourcing current from CS pin, and the
voltage can be calculated as current value times
resistance. When the setting voltage is higher, the
burst switching green mode entry threshold is higher;
when the setting voltage is lower, the burst switching
green mode entry threshold voltage is lower. The
RT7737 has five burst switching green mode levels
as shown in Table 1.
The 1% or 5% RCS_RC tolerance should be chosen
for burst switching green mode level setting.
Designers can use RCS_RC = 330 as initial burst
switching green mode level setting, and find the
BURST Pin - Programmable Burst Mode Level
The RT7737 provides a BURST pin to program the
burst mode level by connecting a resistor, RBS, with a
range of 10k to 60k between the BURST pin and
ground. The voltage on the BURST pin should be
between VL_TH and VH_TH for normal operating as
shown in Figure 2. Designers can program the burst
mode entry voltage VBURST_ET according to Figure 3,
and the burst mode ending voltage VBURST_ED =
VBURST _ET + 0.2V.
The 1% or 5% RBS_RC tolerance should be chosen for
burst mode level setting. Designers should use
RBS_RC = 33k as initial burst mode level setting, and
adjust burst mode level setting according to power
consumption requirement under highest input voltage
and no load.
Besides achieving optimized average efficiency, for
When the RBS_RC is larger, the quicker the IC enters
burst mode which means the current is also larger. It
turns out that the average frequency decreases under
burst mode and the same load conditions. It
decreases the switching losses under high input
voltage, light load or no load conditions and further
decreases power consumption efficiently. On the
contrary, When the RBS_RC is smaller, the slower the
strict limit audio frequency product applications, the
programmable burst switching green mode provides
five levels for designers to avoid some specific
frequencies under specific loads to fulfill product
application requirements.
IC enters burst mode which means the current is also
smaller. As a result, the average frequency increases
under burst mode and the same load conditions, and
it increases the switching losses under high input
voltage, light load or no load conditions.
Table 1. Programmable Burst Switching Green
Mode Level Setting
Audio noise is related to frequency and sound
intensity, and the human ear can’t hear a sound
below 17kHz. The minimum frequency, f BS_MIN, of the
RT7737 is 22kHz which may not be heard by the
human ear. Because of stricter energy regulations
and pursuit of green performance, the requirements
of light load and no load power consumption are lower
and stricter. The RT7737 uses the control method to
enter burst mode under light load or no load condition
to efficiently decrease the switching losses to lower
power consumption. However, the higher RBS
resistance value which make operating frequency
most close to f BS_MIN under highest input voltage and
25% nominal load. The better four loads
(100%/75%/50%/25%
nominal
load)
average
frequency can be achieved by this design.
Burst Switching Green Mode Setting
GATE
RT7737
RCS_RC
CS
GND
RCS_RC ()
VBS_ET (V)
VBS_ED (V)
750
2.75
2.35
510
2.65
2.25
330
2.55
2.15
200
2.45
2.05
100
2.35
1.95
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
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14
resistance is not the better. Although it can decrease
the average frequency in burst mode, it also
increases the cycle-by-cycle current which means the
sound intensity is relatively larger. Also, the difference
is a registered trademark of Richtek Technology Corporation
DS7737-00
September 2014
RT7737
VBURST
frequency of burst mode low frequency and the
minimum frequency of the RT7737 falls to frequency
that is available to human ear, ant it may cause audio
noise problem.
Protection
(Latch)
VH_TH
Normal Operating
(Setting Burst Mode Threshold )
As a result, designers should be aware of product
audio noise while pursuing lower power consumption.
VL_TH
The advantages of programmable burst mode are
that it can not only decreases power consumption
The BURST pin can be used for programmable burst
mode level setting and can also act as over-voltage
protection or IC on/off control application with external
application circuits, as shown in Figure 4 to 6. The
application circuit design concept is shown in Figure 2.
If the BURST voltage is lower than VL_TH after
deglitch time (30s, typ.), the controller shuts down
and stops switching. The BURST pin features an
internal bias current (30A, typ.). Bypassing the bias
current can decrease the voltage on the BURST pin.
The range of the BURST pin series resistance is from
10k to 60k. Providing supply current from 260A
to 10A from application circuit can raise the voltage
on the BUSRT pin. The selection of application circuit
components should take component leakage and
thermal effect into account.
The programmable burst mode voltage should be
between VL_TH and VH_TH for normal operation, so
the BURST pin cannot be open. If designers want to
connect a bypass capacitor to the BURST pin, the
Figure 2. BURST Pin Operation
Burst Mode Entry Level vs. RBS
Burst Mode Entry Level (V)
under light load and no load conditions but also
provides linear entry level setting for those
applications which strict frequency limitations have to
choose from, or avoid some specific frequencies.
Protection
(Auto Recovery/Latch)
1.80
1.75
1.70
1.65
1.60
1.55
1.50
1.45
1.40
1.35
1.30
1.25
1.20
1.15
1.10
1.05
1.00
y = 0.01x + 1.05
0
10
20
30
40
50
60
70
RBS (kΩ)
Figure 3. Burst Mode Entry Level vs. RBS
VDD
BURST
RBS
(Option)
Figure 4. VDD OVP Application Circuit
VDD
BURST
capacitance should be less than 1nF.
The difference between the burst switching green
mode ending voltage (VBS_ED) and the burst mode
ending voltage (VBURST_ED) should be more than
50mV to prevent the burst switching green mode from
suddenly dropping to burst mode, causing audio
noise.
RBS
(Option)
Figure 5. VDD OVP Application Circuit
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS7737-00
September
2014
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www.richtek.com
15
RT7737
Preliminary
BURST
(Option)
quickly. Figure 7 shows IDD_Avg vs. RBleeding curve.
Users can apply this curve to design the adequate
bleeding resistors.
VO+
(Option)
RBS
Figure 6. Output OVP Application Circuit
Start-Up Circuit
To minimize power loss, it's recommended to connect
the start-up circuit to the bleeding resistors. It's power
saving and also could reset latch mode protection
In order to prolong turn-off period and minimize the
power loss and thermal rising during hiccup, the
controller is designed to have smaller sinking current
during entering auto-recovery protection, IDD_ARP.
Therefore, the start-up current at maximum AC line
input voltage must be smaller than IDD_ARP
(IDD_ARP(min) = 350A). Otherwise, when the controller
enters auto-recovery protection, the VDD capacitor
won't be dropped down to VTH_OFF by IC's sinking
current and then restart. The controller behaves like
latch protection or triggers the SCR of VDD.
IDD_Avg vs. RBleeding Curve
IDD_Avg vs. RBleeding Curve
250
90
RBleeding
80
RBleeding
60
VDD
50
90Vac
85Vac
80Vac
40
IDD_Avg
RBleeding
200
I DD_Avg (μA)
I DD_Avg (μA)
70
RBleeding
225
IDD_Avg
175
VDD
150
265Vac
230Vac
125
30
100
20
75
50
10
0.6
1.0
1.4
1.8
2.2
2.6
3.0
0.6
1.0
1.4
1.8
2.2
2.6
3.0
RBleeding (M)
RBleeding (M)
Figure 7. IDD_Avg vs. RBleeding Curve
VDD Discharge Time in Auto Recovery Mode
Figure 8 shows the VDD and VGATE waveforms during
an auto recovery protection (e.g., OLP). In this mode,
the start-up resistors, VDD sinking current and VDD
decoupling capacitor will affect the restart time. The
VDD voltage discharge time tD_Discharge can be
calculated by the following equation :
tD_Discharge
CVDD (VDD_DIS VTH_OFF )
IDD_ARP IST
Where the CVDD is the VDD decoupling capacitor, the
VDD_DIS is the initial VDD voltage after entering the
auto recovery mode, the VTH_OFF (9V typ.) is the
falling UVLO voltage threshold of the controller, the
IDD_ARP (550A typ.) is the sinking current of the VDD
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
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16
pin in the auto recovery mode, and IST is the start-up
current of the power system.
Please note that the start-up current at high input
voltage must be smaller than the IDD_ARP. Otherwise,
the VDD voltage can't reach the VTH_OFF to activate
the next start-up process after an auto recovery
protection. Therefore, the system behavior resembles
the behavior of latch mode.
VDD
VDD_DIS
VTH_ON
VTH_OFF
t
VGATE
OLP Delay
Time
tD_Discharge
t
Figure 8. Auto Recovery Mode (e.g., OLP)
is a registered trademark of Richtek Technology Corporation
DS7737-00
September 2014
RT7737
VDD Holdup Mode
The VDD holdup mode is only designed to prevent
VDD from decreasing to the turn-off threshold voltage,
VTH_OFF, under light load or load transient. Compare
to burst mode, the VDD holdup mode brings higher
switching. Hence, it is highly recommended that the
system should avoid operating at this mode during
light load or no load conditions.
Output Short Protection
The RT7737 implements output short protection by
detecting GATE width TON_OSP and delay time
TD_OSP. It can minimize the power loss during output
short, especially at high line input voltage.
Because it is hard to distinguish the difference
between output short and big capacitance load, circuit
design must be careful to make sure GATE width is
larger than TON_OSP (TON > TON_OSP(MAX)) after
delay time TD_OSP during start-up.
Resistors on GATE Pin
In Figure 9, RG is applied to alleviate ringing spike of
gate drive loop in typical application circuits. The
value of RG must be considered carefully with respect
to EMI and efficiency for the system.
AC Mains
(90V to 265V)
The RT7737 build in a internal discharge-resistor to
prevent the MOSFET at any uncertain conditions.
CGD
RT7737
Soft
Driver
GATE
RG
RID
RED
CS
GND
Recommend to add the external dischargeresistor to avoid MOSFET falsely triggering.
Figure 9. Resistors on Gate Pin
Feedback Resistor
In order to enhance light load efficiency, the loss of
the feedback resistor in parallel with photo-coupler is
reduced, as shown in Figure 10. Due to small
feedback resistor current, shunt regulator selection
(e.g. TL-431) and minimum regulation current design
must be considered carefully to make sure it's able to
regulate under low cathode current.
The built-in internal discharge resistor RID in parallel
+
GATE pin and the Gate of the MOSFET is
disconnected, the MOSFET will be false triggered by
Vo+
+
with GATE pin prevents the MOSFET from any
uncertain condition. If the connection between the
Vo-
the residual energy through the Gate-to-Drain
parasitic capacitor CGD of the MOSFET and the
system will be damaged. Therefore, it’s highly
recommended to add an external discharge-resistor
RED connected between the Gate of MOSFET and
GND terminals. The energy through the CGD is
discharged by the external discharge-resistor to avoid
MOSFET false triggering.
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
DS7737-00
September
2014
Feedback
Resistor
Figure 10. Feedback Resistor
is a registered trademark of Richtek Technology Corporation
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17
RT7737
Preliminary
Negative Voltage Spike on Each Pin
Thermal Considerations
Negative voltage (< 0.3V) to the controller pins will
cause substrate injection and lead to controller
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the
damage or circuit false triggering. For example, the
negative spike voltage at the CS pin may come from
improper PCB layout or inductive current sense
resistor. Therefore, it is highly recommended to add
an R-C filter to avoid the CS pin damage, as shown in
Figure 11. Proper PCB layout and component
selection should be considered during circuit design.
Mains
(90V to 265V)
IC package, PCB layout, rate of surrounding airflow,
and difference between junction and ambient
temperature. The maximum power dissipation can be
calculated by the following formula :
PD(MAX) = (TJ(MAX) TA) / JA
where TJ(MAX) is the maximum junction temperature,
TA is the ambient temperature, and JA is the junction
to ambient thermal resistance.
For recommended operating condition specifications,
the maximum junction temperature is 125C. The
junction to ambient thermal resistance, JA, is layout
dependent. For SOT-23-6 package, the thermal
resistance, JA, is 260.7C/W on a standard JEDEC
51-3 single-layer thermal test board. The maximum
GATE
RT7737
COMP
CS
power dissipation at TA = 25C can be calculated by
the following formula :
GND
R-C Filter
Figure 11. R-C Filter on CS Pin
Over-Temperature Protection (OTP)
The RT7737 provides OTP function to prevent
permanent damage. It is not recommended to apply
this function to accurate temperature control.
When the IC turns on, the controller detects around
temperature before it starts switching. If the
temperature is higher than TOTP_INTH (typ. 120C),
the controller triggers OTP, and there is no output
signal. If the temperature is lower than TOTP_INTH, the
controller starts operation and the OTP threshold is
automatically set to TOTP_STTH (typ. 140C), which
means when the controller starts switching, the OTP
threshold is TOTP_STTH.
When the controller triggers OTP, the controller will
be shut down and cease switching. At the same time,
VDD drops below VDD off threshold VTH_OFF, the
controller enters hiccup mode. Until the OTP is
released, the controller resumes operation.
PD(MAX) = (125C 25C) / (260.7C/W) = 0.38W for
SOT-23-6 package
The maximum power dissipation depends on the
operating ambient temperature for fixed TJ(MAX) and
thermal resistance, JA. The derating curve in Figure
12 allows the designer to see the effect of rising
ambient temperature on the maximum power
dissipation.
0.5
Maximum Power Dissipation (W)1
VDD
BURST
Signal-Layer PCB
0.4
0.3
0.2
0.1
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 12. Derating Curve of Maximum Power
Dissipation
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18
is a registered trademark of Richtek Technology Corporation
DS7737-00
September 2014
RT7737
Layout Consideration
A proper PCB layout can abate unknown noise
interference and EMI issue in the switching power
supply. Please refer to the guidelines when you want
to design PCB layout for switching power supply :
capacitor ground (a). The areas of these ground
traces should be large enough.
The current path (1) through bulk capacitor,
transformer, MOSFET, RCS returns to bulk
capacitor is a high frequency current loop. It must
be as short as possible to decrease noise coupling
and keep away from other low voltage traces, such
as IC control circuit paths, especially.
Separate the ground traces of bulk capacitor(a),
MOSFET(b), auxiliary winding(c) and IC control
circuit(d) for reducing noise, output ripple and EMI
issue. Connect these ground traces together at bulk
The path (2) of the RCD snubber circuit is also a
high switching loop. Keep it as small as possible.
Place the bypass capacitor as close to the
controller as possible.
In order to reduce reflected trace inductance and
EMI, minimize the area of the loop connecting the
secondary winding, output diode and output filter
capacitor. In additional, apply sufficient copper area
at the anode and cathode terminal of the diode for
heatsinking.
CBULK
Mains
(90V to 265V)
(2)
(a)
CBULK Ground (a)
VDD
(c)
GATE
BURST
RT7737
COMP
CS
(1)
Trace
IC
Ground (d)
Trace
Auxiliary
Ground (c)
Trace
MOSFET
Ground (b)
GND
(b)
(d)
Figure 13. PCB Layout Guide
Copyright © 2014 Richtek Technology Corporation. All rights reserved.
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September
2014
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19
RT7737
Preliminary
Outline Dimension
Symbol
Dimensions In Millimeters
Dimensions In Inches
Min
Max
Min
Max
A
0.889
1.295
0.031
0.051
A1
0.000
0.152
0.000
0.006
B
1.397
1.803
0.055
0.071
b
0.250
0.560
0.010
0.022
C
2.591
2.997
0.102
0.118
D
2.692
3.099
0.106
0.122
e
0.838
1.041
0.033
0.041
H
0.080
0.254
0.003
0.010
L
0.300
0.610
0.012
0.024
SOT-23-6 Surface Mount Package
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume
responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and
reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
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is a registered trademark of Richtek Technology Corporation
DS7737-00
September 2014
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